/drivers/video/omap2/dss/venc.c
C | 924 lines | 734 code | 157 blank | 33 comment | 60 complexity | 46005988e00b93b8add1f9edb009b20d MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "VENC"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/mutex.h>
30#include <linux/completion.h>
31#include <linux/delay.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
36#include <linux/pm_runtime.h>
37
38#include <video/omapdss.h>
39#include <plat/cpu.h>
40
41#include "dss.h"
42#include "dss_features.h"
43
44/* Venc registers */
45#define VENC_REV_ID 0x00
46#define VENC_STATUS 0x04
47#define VENC_F_CONTROL 0x08
48#define VENC_VIDOUT_CTRL 0x10
49#define VENC_SYNC_CTRL 0x14
50#define VENC_LLEN 0x1C
51#define VENC_FLENS 0x20
52#define VENC_HFLTR_CTRL 0x24
53#define VENC_CC_CARR_WSS_CARR 0x28
54#define VENC_C_PHASE 0x2C
55#define VENC_GAIN_U 0x30
56#define VENC_GAIN_V 0x34
57#define VENC_GAIN_Y 0x38
58#define VENC_BLACK_LEVEL 0x3C
59#define VENC_BLANK_LEVEL 0x40
60#define VENC_X_COLOR 0x44
61#define VENC_M_CONTROL 0x48
62#define VENC_BSTAMP_WSS_DATA 0x4C
63#define VENC_S_CARR 0x50
64#define VENC_LINE21 0x54
65#define VENC_LN_SEL 0x58
66#define VENC_L21__WC_CTL 0x5C
67#define VENC_HTRIGGER_VTRIGGER 0x60
68#define VENC_SAVID__EAVID 0x64
69#define VENC_FLEN__FAL 0x68
70#define VENC_LAL__PHASE_RESET 0x6C
71#define VENC_HS_INT_START_STOP_X 0x70
72#define VENC_HS_EXT_START_STOP_X 0x74
73#define VENC_VS_INT_START_X 0x78
74#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77#define VENC_VS_EXT_STOP_Y 0x88
78#define VENC_AVID_START_STOP_X 0x90
79#define VENC_AVID_START_STOP_Y 0x94
80#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83#define VENC_TVDETGP_INT_START_STOP_X 0xB0
84#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85#define VENC_GEN_CTRL 0xB8
86#define VENC_OUTPUT_CONTROL 0xC4
87#define VENC_OUTPUT_TEST 0xC8
88#define VENC_DAC_B__DAC_C 0xC8
89
90struct venc_config {
91 u32 f_control;
92 u32 vidout_ctrl;
93 u32 sync_ctrl;
94 u32 llen;
95 u32 flens;
96 u32 hfltr_ctrl;
97 u32 cc_carr_wss_carr;
98 u32 c_phase;
99 u32 gain_u;
100 u32 gain_v;
101 u32 gain_y;
102 u32 black_level;
103 u32 blank_level;
104 u32 x_color;
105 u32 m_control;
106 u32 bstamp_wss_data;
107 u32 s_carr;
108 u32 line21;
109 u32 ln_sel;
110 u32 l21__wc_ctl;
111 u32 htrigger_vtrigger;
112 u32 savid__eavid;
113 u32 flen__fal;
114 u32 lal__phase_reset;
115 u32 hs_int_start_stop_x;
116 u32 hs_ext_start_stop_x;
117 u32 vs_int_start_x;
118 u32 vs_int_stop_x__vs_int_start_y;
119 u32 vs_int_stop_y__vs_ext_start_x;
120 u32 vs_ext_stop_x__vs_ext_start_y;
121 u32 vs_ext_stop_y;
122 u32 avid_start_stop_x;
123 u32 avid_start_stop_y;
124 u32 fid_int_start_x__fid_int_start_y;
125 u32 fid_int_offset_y__fid_ext_start_x;
126 u32 fid_ext_start_y__fid_ext_offset_y;
127 u32 tvdetgp_int_start_stop_x;
128 u32 tvdetgp_int_start_stop_y;
129 u32 gen_ctrl;
130};
131
132/* from TRM */
133static const struct venc_config venc_config_pal_trm = {
134 .f_control = 0,
135 .vidout_ctrl = 1,
136 .sync_ctrl = 0x40,
137 .llen = 0x35F, /* 863 */
138 .flens = 0x270, /* 624 */
139 .hfltr_ctrl = 0,
140 .cc_carr_wss_carr = 0x2F7225ED,
141 .c_phase = 0,
142 .gain_u = 0x111,
143 .gain_v = 0x181,
144 .gain_y = 0x140,
145 .black_level = 0x3B,
146 .blank_level = 0x3B,
147 .x_color = 0x7,
148 .m_control = 0x2,
149 .bstamp_wss_data = 0x3F,
150 .s_carr = 0x2A098ACB,
151 .line21 = 0,
152 .ln_sel = 0x01290015,
153 .l21__wc_ctl = 0x0000F603,
154 .htrigger_vtrigger = 0,
155
156 .savid__eavid = 0x06A70108,
157 .flen__fal = 0x00180270,
158 .lal__phase_reset = 0x00040135,
159 .hs_int_start_stop_x = 0x00880358,
160 .hs_ext_start_stop_x = 0x000F035F,
161 .vs_int_start_x = 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
165 .vs_ext_stop_y = 0x00000025,
166 .avid_start_stop_x = 0x03530083,
167 .avid_start_stop_y = 0x026C002E,
168 .fid_int_start_x__fid_int_start_y = 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
171
172 .tvdetgp_int_start_stop_x = 0x00140001,
173 .tvdetgp_int_start_stop_y = 0x00010001,
174 .gen_ctrl = 0x00FF0000,
175};
176
177/* from TRM */
178static const struct venc_config venc_config_ntsc_trm = {
179 .f_control = 0,
180 .vidout_ctrl = 1,
181 .sync_ctrl = 0x8040,
182 .llen = 0x359,
183 .flens = 0x20C,
184 .hfltr_ctrl = 0,
185 .cc_carr_wss_carr = 0x043F2631,
186 .c_phase = 0,
187 .gain_u = 0x102,
188 .gain_v = 0x16C,
189 .gain_y = 0x12F,
190 .black_level = 0x43,
191 .blank_level = 0x38,
192 .x_color = 0x7,
193 .m_control = 0x1,
194 .bstamp_wss_data = 0x38,
195 .s_carr = 0x21F07C1F,
196 .line21 = 0,
197 .ln_sel = 0x01310011,
198 .l21__wc_ctl = 0x0000F003,
199 .htrigger_vtrigger = 0,
200
201 .savid__eavid = 0x069300F4,
202 .flen__fal = 0x0016020C,
203 .lal__phase_reset = 0x00060107,
204 .hs_int_start_stop_x = 0x008E0350,
205 .hs_ext_start_stop_x = 0x000F0359,
206 .vs_int_start_x = 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
210 .vs_ext_stop_y = 0x00000006,
211 .avid_start_stop_x = 0x03480078,
212 .avid_start_stop_y = 0x02060024,
213 .fid_int_start_x__fid_int_start_y = 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
216
217 .tvdetgp_int_start_stop_x = 0x00140001,
218 .tvdetgp_int_start_stop_y = 0x00010001,
219 .gen_ctrl = 0x00F90000,
220};
221
222static const struct venc_config venc_config_pal_bdghi = {
223 .f_control = 0,
224 .vidout_ctrl = 0,
225 .sync_ctrl = 0,
226 .hfltr_ctrl = 0,
227 .x_color = 0,
228 .line21 = 0,
229 .ln_sel = 21,
230 .htrigger_vtrigger = 0,
231 .tvdetgp_int_start_stop_x = 0x00140001,
232 .tvdetgp_int_start_stop_y = 0x00010001,
233 .gen_ctrl = 0x00FB0000,
234
235 .llen = 864-1,
236 .flens = 625-1,
237 .cc_carr_wss_carr = 0x2F7625ED,
238 .c_phase = 0xDF,
239 .gain_u = 0x111,
240 .gain_v = 0x181,
241 .gain_y = 0x140,
242 .black_level = 0x3e,
243 .blank_level = 0x3e,
244 .m_control = 0<<2 | 1<<1,
245 .bstamp_wss_data = 0x42,
246 .s_carr = 0x2a098acb,
247 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid = 0x06A70108,
249 .flen__fal = 23<<16 | 624<<0,
250 .lal__phase_reset = 2<<17 | 310<<0,
251 .hs_int_start_stop_x = 0x00920358,
252 .hs_ext_start_stop_x = 0x000F035F,
253 .vs_int_start_x = 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
257 .vs_ext_stop_y = 0x05,
258 .avid_start_stop_x = 0x03530082,
259 .avid_start_stop_y = 0x0270002E,
260 .fid_int_start_x__fid_int_start_y = 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263};
264
265const struct omap_video_timings omap_dss_pal_timings = {
266 .x_res = 720,
267 .y_res = 574,
268 .pixel_clock = 13500,
269 .hsw = 64,
270 .hfp = 12,
271 .hbp = 68,
272 .vsw = 5,
273 .vfp = 5,
274 .vbp = 41,
275};
276EXPORT_SYMBOL(omap_dss_pal_timings);
277
278const struct omap_video_timings omap_dss_ntsc_timings = {
279 .x_res = 720,
280 .y_res = 482,
281 .pixel_clock = 13500,
282 .hsw = 64,
283 .hfp = 16,
284 .hbp = 58,
285 .vsw = 6,
286 .vfp = 6,
287 .vbp = 31,
288};
289EXPORT_SYMBOL(omap_dss_ntsc_timings);
290
291static struct {
292 struct platform_device *pdev;
293 void __iomem *base;
294 struct mutex venc_lock;
295 u32 wss_data;
296 struct regulator *vdda_dac_reg;
297
298 struct mutex runtime_lock;
299 int runtime_count;
300
301 struct clk *tv_clk;
302 struct clk *tv_dac_clk;
303} venc;
304
305static inline void venc_write_reg(int idx, u32 val)
306{
307 __raw_writel(val, venc.base + idx);
308}
309
310static inline u32 venc_read_reg(int idx)
311{
312 u32 l = __raw_readl(venc.base + idx);
313 return l;
314}
315
316static void venc_write_config(const struct venc_config *config)
317{
318 DSSDBG("write venc conf\n");
319
320 venc_write_reg(VENC_LLEN, config->llen);
321 venc_write_reg(VENC_FLENS, config->flens);
322 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
323 venc_write_reg(VENC_C_PHASE, config->c_phase);
324 venc_write_reg(VENC_GAIN_U, config->gain_u);
325 venc_write_reg(VENC_GAIN_V, config->gain_v);
326 venc_write_reg(VENC_GAIN_Y, config->gain_y);
327 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
328 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
329 venc_write_reg(VENC_M_CONTROL, config->m_control);
330 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
331 venc.wss_data);
332 venc_write_reg(VENC_S_CARR, config->s_carr);
333 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
334 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
335 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
336 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
337 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
338 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
339 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
340 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
341 config->vs_int_stop_x__vs_int_start_y);
342 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
343 config->vs_int_stop_y__vs_ext_start_x);
344 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
345 config->vs_ext_stop_x__vs_ext_start_y);
346 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
347 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
348 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
349 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
350 config->fid_int_start_x__fid_int_start_y);
351 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
352 config->fid_int_offset_y__fid_ext_start_x);
353 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
354 config->fid_ext_start_y__fid_ext_offset_y);
355
356 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
357 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
358 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
359 venc_write_reg(VENC_X_COLOR, config->x_color);
360 venc_write_reg(VENC_LINE21, config->line21);
361 venc_write_reg(VENC_LN_SEL, config->ln_sel);
362 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
363 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
364 config->tvdetgp_int_start_stop_x);
365 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
366 config->tvdetgp_int_start_stop_y);
367 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
368 venc_write_reg(VENC_F_CONTROL, config->f_control);
369 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
370}
371
372static void venc_reset(void)
373{
374 int t = 1000;
375
376 venc_write_reg(VENC_F_CONTROL, 1<<8);
377 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
378 if (--t == 0) {
379 DSSERR("Failed to reset venc\n");
380 return;
381 }
382 }
383
384#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
385 /* the magical sleep that makes things work */
386 /* XXX more info? What bug this circumvents? */
387 msleep(20);
388#endif
389}
390
391static int venc_runtime_get(void)
392{
393 int r;
394
395 mutex_lock(&venc.runtime_lock);
396
397 if (venc.runtime_count++ == 0) {
398 DSSDBG("venc_runtime_get\n");
399
400 r = dss_runtime_get();
401 if (r)
402 goto err_get_dss;
403
404 r = dispc_runtime_get();
405 if (r)
406 goto err_get_dispc;
407
408 clk_enable(venc.tv_clk);
409 if (venc.tv_dac_clk)
410 clk_enable(venc.tv_dac_clk);
411
412 r = pm_runtime_get_sync(&venc.pdev->dev);
413 WARN_ON(r);
414 if (r < 0)
415 goto err_runtime_get;
416 }
417
418 mutex_unlock(&venc.runtime_lock);
419
420 return 0;
421
422err_runtime_get:
423 clk_disable(venc.tv_clk);
424 if (venc.tv_dac_clk)
425 clk_disable(venc.tv_dac_clk);
426 dispc_runtime_put();
427err_get_dispc:
428 dss_runtime_put();
429err_get_dss:
430 mutex_unlock(&venc.runtime_lock);
431
432 return r;
433}
434
435static void venc_runtime_put(void)
436{
437 mutex_lock(&venc.runtime_lock);
438
439 if (--venc.runtime_count == 0) {
440 int r;
441
442 DSSDBG("venc_runtime_put\n");
443
444 r = pm_runtime_put_sync(&venc.pdev->dev);
445 WARN_ON(r);
446
447 clk_disable(venc.tv_clk);
448 if (venc.tv_dac_clk)
449 clk_disable(venc.tv_dac_clk);
450
451 dispc_runtime_put();
452 dss_runtime_put();
453 }
454
455 mutex_unlock(&venc.runtime_lock);
456}
457
458static const struct venc_config *venc_timings_to_config(
459 struct omap_video_timings *timings)
460{
461 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
462 return &venc_config_pal_trm;
463
464 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
465 return &venc_config_ntsc_trm;
466
467 BUG();
468}
469
470static void venc_power_on(struct omap_dss_device *dssdev)
471{
472 u32 l;
473
474 venc_reset();
475 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
476
477 dss_set_venc_output(dssdev->phy.venc.type);
478 dss_set_dac_pwrdn_bgz(1);
479
480 l = 0;
481
482 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
483 l |= 1 << 1;
484 else /* S-Video */
485 l |= (1 << 0) | (1 << 2);
486
487 if (dssdev->phy.venc.invert_polarity == false)
488 l |= 1 << 3;
489
490 venc_write_reg(VENC_OUTPUT_CONTROL, l);
491
492 dispc_set_digit_size(dssdev->panel.timings.x_res,
493 dssdev->panel.timings.y_res/2);
494
495 regulator_enable(venc.vdda_dac_reg);
496
497 if (dssdev->platform_enable)
498 dssdev->platform_enable(dssdev);
499
500 dssdev->manager->enable(dssdev->manager);
501}
502
503static void venc_power_off(struct omap_dss_device *dssdev)
504{
505 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
506 dss_set_dac_pwrdn_bgz(0);
507
508 dssdev->manager->disable(dssdev->manager);
509
510 if (dssdev->platform_disable)
511 dssdev->platform_disable(dssdev);
512
513 regulator_disable(venc.vdda_dac_reg);
514}
515
516
517
518
519
520/* driver */
521static int venc_panel_probe(struct omap_dss_device *dssdev)
522{
523 dssdev->panel.timings = omap_dss_pal_timings;
524
525 return 0;
526}
527
528static void venc_panel_remove(struct omap_dss_device *dssdev)
529{
530}
531
532static int venc_panel_enable(struct omap_dss_device *dssdev)
533{
534 int r = 0;
535
536 DSSDBG("venc_enable_display\n");
537
538 mutex_lock(&venc.venc_lock);
539
540 r = omap_dss_start_device(dssdev);
541 if (r) {
542 DSSERR("failed to start device\n");
543 goto err0;
544 }
545
546 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
547 r = -EINVAL;
548 goto err1;
549 }
550
551 r = venc_runtime_get();
552 if (r)
553 goto err1;
554
555 venc_power_on(dssdev);
556
557 venc.wss_data = 0;
558
559 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
560
561 mutex_unlock(&venc.venc_lock);
562 return 0;
563err1:
564 omap_dss_stop_device(dssdev);
565err0:
566 mutex_unlock(&venc.venc_lock);
567
568 return r;
569}
570
571static void venc_panel_disable(struct omap_dss_device *dssdev)
572{
573 DSSDBG("venc_disable_display\n");
574
575 mutex_lock(&venc.venc_lock);
576
577 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
578 goto end;
579
580 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
581 /* suspended is the same as disabled with venc */
582 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
583 goto end;
584 }
585
586 venc_power_off(dssdev);
587
588 venc_runtime_put();
589
590 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
591
592 omap_dss_stop_device(dssdev);
593end:
594 mutex_unlock(&venc.venc_lock);
595}
596
597static int venc_panel_suspend(struct omap_dss_device *dssdev)
598{
599 venc_panel_disable(dssdev);
600 return 0;
601}
602
603static int venc_panel_resume(struct omap_dss_device *dssdev)
604{
605 return venc_panel_enable(dssdev);
606}
607
608static enum omap_dss_update_mode venc_get_update_mode(
609 struct omap_dss_device *dssdev)
610{
611 return OMAP_DSS_UPDATE_AUTO;
612}
613
614static int venc_set_update_mode(struct omap_dss_device *dssdev,
615 enum omap_dss_update_mode mode)
616{
617 if (mode != OMAP_DSS_UPDATE_AUTO)
618 return -EINVAL;
619 return 0;
620}
621
622static void venc_get_timings(struct omap_dss_device *dssdev,
623 struct omap_video_timings *timings)
624{
625 *timings = dssdev->panel.timings;
626}
627
628static void venc_set_timings(struct omap_dss_device *dssdev,
629 struct omap_video_timings *timings)
630{
631 DSSDBG("venc_set_timings\n");
632
633 /* Reset WSS data when the TV standard changes. */
634 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
635 venc.wss_data = 0;
636
637 dssdev->panel.timings = *timings;
638 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
639 /* turn the venc off and on to get new timings to use */
640 venc_panel_disable(dssdev);
641 venc_panel_enable(dssdev);
642 }
643}
644
645static int venc_check_timings(struct omap_dss_device *dssdev,
646 struct omap_video_timings *timings)
647{
648 DSSDBG("venc_check_timings\n");
649
650 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
651 return 0;
652
653 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
654 return 0;
655
656 return -EINVAL;
657}
658
659static u32 venc_get_wss(struct omap_dss_device *dssdev)
660{
661 /* Invert due to VENC_L21_WC_CTL:INV=1 */
662 return (venc.wss_data >> 8) ^ 0xfffff;
663}
664
665static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
666{
667 const struct venc_config *config;
668 int r;
669
670 DSSDBG("venc_set_wss\n");
671
672 mutex_lock(&venc.venc_lock);
673
674 config = venc_timings_to_config(&dssdev->panel.timings);
675
676 /* Invert due to VENC_L21_WC_CTL:INV=1 */
677 venc.wss_data = (wss ^ 0xfffff) << 8;
678
679 r = venc_runtime_get();
680 if (r)
681 goto err;
682
683 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
684 venc.wss_data);
685
686 venc_runtime_put();
687
688err:
689 mutex_unlock(&venc.venc_lock);
690
691 return r;
692}
693
694static struct omap_dss_driver venc_driver = {
695 .probe = venc_panel_probe,
696 .remove = venc_panel_remove,
697
698 .enable = venc_panel_enable,
699 .disable = venc_panel_disable,
700 .suspend = venc_panel_suspend,
701 .resume = venc_panel_resume,
702
703 .get_resolution = omapdss_default_get_resolution,
704 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
705
706 .set_update_mode = venc_set_update_mode,
707 .get_update_mode = venc_get_update_mode,
708
709 .get_timings = venc_get_timings,
710 .set_timings = venc_set_timings,
711 .check_timings = venc_check_timings,
712
713 .get_wss = venc_get_wss,
714 .set_wss = venc_set_wss,
715
716 .driver = {
717 .name = "venc",
718 .owner = THIS_MODULE,
719 },
720};
721/* driver end */
722
723int venc_init_display(struct omap_dss_device *dssdev)
724{
725 DSSDBG("init_display\n");
726
727 if (venc.vdda_dac_reg == NULL) {
728 struct regulator *vdda_dac;
729
730 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
731
732 if (IS_ERR(vdda_dac)) {
733 DSSERR("can't get VDDA_DAC regulator\n");
734 return PTR_ERR(vdda_dac);
735 }
736
737 venc.vdda_dac_reg = vdda_dac;
738 }
739
740 return 0;
741}
742
743void venc_dump_regs(struct seq_file *s)
744{
745#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
746
747 if (venc_runtime_get())
748 return;
749
750 DUMPREG(VENC_F_CONTROL);
751 DUMPREG(VENC_VIDOUT_CTRL);
752 DUMPREG(VENC_SYNC_CTRL);
753 DUMPREG(VENC_LLEN);
754 DUMPREG(VENC_FLENS);
755 DUMPREG(VENC_HFLTR_CTRL);
756 DUMPREG(VENC_CC_CARR_WSS_CARR);
757 DUMPREG(VENC_C_PHASE);
758 DUMPREG(VENC_GAIN_U);
759 DUMPREG(VENC_GAIN_V);
760 DUMPREG(VENC_GAIN_Y);
761 DUMPREG(VENC_BLACK_LEVEL);
762 DUMPREG(VENC_BLANK_LEVEL);
763 DUMPREG(VENC_X_COLOR);
764 DUMPREG(VENC_M_CONTROL);
765 DUMPREG(VENC_BSTAMP_WSS_DATA);
766 DUMPREG(VENC_S_CARR);
767 DUMPREG(VENC_LINE21);
768 DUMPREG(VENC_LN_SEL);
769 DUMPREG(VENC_L21__WC_CTL);
770 DUMPREG(VENC_HTRIGGER_VTRIGGER);
771 DUMPREG(VENC_SAVID__EAVID);
772 DUMPREG(VENC_FLEN__FAL);
773 DUMPREG(VENC_LAL__PHASE_RESET);
774 DUMPREG(VENC_HS_INT_START_STOP_X);
775 DUMPREG(VENC_HS_EXT_START_STOP_X);
776 DUMPREG(VENC_VS_INT_START_X);
777 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
778 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
779 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
780 DUMPREG(VENC_VS_EXT_STOP_Y);
781 DUMPREG(VENC_AVID_START_STOP_X);
782 DUMPREG(VENC_AVID_START_STOP_Y);
783 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
784 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
785 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
786 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
787 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
788 DUMPREG(VENC_GEN_CTRL);
789 DUMPREG(VENC_OUTPUT_CONTROL);
790 DUMPREG(VENC_OUTPUT_TEST);
791
792 venc_runtime_put();
793
794#undef DUMPREG
795}
796
797static int venc_get_clocks(struct platform_device *pdev)
798{
799 struct clk *clk;
800
801 clk = clk_get(&pdev->dev, "tv_clk");
802 if (IS_ERR(clk)) {
803 DSSERR("can't get tv_clk\n");
804 return PTR_ERR(clk);
805 }
806
807 venc.tv_clk = clk;
808
809 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
810 clk = clk_get(&pdev->dev, "tv_dac_clk");
811 if (IS_ERR(clk)) {
812 DSSERR("can't get tv_dac_clk\n");
813 clk_put(venc.tv_clk);
814 return PTR_ERR(clk);
815 }
816 } else {
817 clk = NULL;
818 }
819
820 venc.tv_dac_clk = clk;
821
822 return 0;
823}
824
825static void venc_put_clocks(void)
826{
827 if (venc.tv_clk)
828 clk_put(venc.tv_clk);
829 if (venc.tv_dac_clk)
830 clk_put(venc.tv_dac_clk);
831}
832
833/* VENC HW IP initialisation */
834static int omap_venchw_probe(struct platform_device *pdev)
835{
836 u8 rev_id;
837 struct resource *venc_mem;
838 int r;
839
840 venc.pdev = pdev;
841
842 mutex_init(&venc.venc_lock);
843
844 venc.wss_data = 0;
845
846 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
847 if (!venc_mem) {
848 DSSERR("can't get IORESOURCE_MEM VENC\n");
849 r = -EINVAL;
850 goto err_ioremap;
851 }
852 venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
853 if (!venc.base) {
854 DSSERR("can't ioremap VENC\n");
855 r = -ENOMEM;
856 goto err_ioremap;
857 }
858
859 r = venc_get_clocks(pdev);
860 if (r)
861 goto err_get_clk;
862
863 mutex_init(&venc.runtime_lock);
864 pm_runtime_enable(&pdev->dev);
865
866 r = venc_runtime_get();
867 if (r)
868 goto err_get_venc;
869
870 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
871 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
872
873 venc_runtime_put();
874
875 return omap_dss_register_driver(&venc_driver);
876
877err_get_venc:
878 pm_runtime_disable(&pdev->dev);
879 venc_put_clocks();
880err_get_clk:
881 iounmap(venc.base);
882err_ioremap:
883 return r;
884}
885
886static int omap_venchw_remove(struct platform_device *pdev)
887{
888 if (venc.vdda_dac_reg != NULL) {
889 regulator_put(venc.vdda_dac_reg);
890 venc.vdda_dac_reg = NULL;
891 }
892 omap_dss_unregister_driver(&venc_driver);
893
894 pm_runtime_disable(&pdev->dev);
895 venc_put_clocks();
896
897 iounmap(venc.base);
898 return 0;
899}
900
901static struct platform_driver omap_venchw_driver = {
902 .probe = omap_venchw_probe,
903 .remove = omap_venchw_remove,
904 .driver = {
905 .name = "omapdss_venc",
906 .owner = THIS_MODULE,
907 },
908};
909
910int venc_init_platform_driver(void)
911{
912 if (cpu_is_omap44xx())
913 return 0;
914
915 return platform_driver_register(&omap_venchw_driver);
916}
917
918void venc_uninit_platform_driver(void)
919{
920 if (cpu_is_omap44xx())
921 return;
922
923 return platform_driver_unregister(&omap_venchw_driver);
924}