/drivers/video/omap2/dss/venc.c

https://bitbucket.org/wisechild/galaxy-nexus · C · 924 lines · 734 code · 157 blank · 33 comment · 60 complexity · 46005988e00b93b8add1f9edb009b20d MD5 · raw file

  1. /*
  2. * linux/drivers/video/omap2/dss/venc.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * VENC settings from TI's DSS driver
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published by
  11. * the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but WITHOUT
  14. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16. * more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along with
  19. * this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #define DSS_SUBSYS_NAME "VENC"
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/clk.h>
  25. #include <linux/err.h>
  26. #include <linux/io.h>
  27. #include <linux/mutex.h>
  28. #include <linux/completion.h>
  29. #include <linux/delay.h>
  30. #include <linux/string.h>
  31. #include <linux/seq_file.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/regulator/consumer.h>
  34. #include <linux/pm_runtime.h>
  35. #include <video/omapdss.h>
  36. #include <plat/cpu.h>
  37. #include "dss.h"
  38. #include "dss_features.h"
  39. /* Venc registers */
  40. #define VENC_REV_ID 0x00
  41. #define VENC_STATUS 0x04
  42. #define VENC_F_CONTROL 0x08
  43. #define VENC_VIDOUT_CTRL 0x10
  44. #define VENC_SYNC_CTRL 0x14
  45. #define VENC_LLEN 0x1C
  46. #define VENC_FLENS 0x20
  47. #define VENC_HFLTR_CTRL 0x24
  48. #define VENC_CC_CARR_WSS_CARR 0x28
  49. #define VENC_C_PHASE 0x2C
  50. #define VENC_GAIN_U 0x30
  51. #define VENC_GAIN_V 0x34
  52. #define VENC_GAIN_Y 0x38
  53. #define VENC_BLACK_LEVEL 0x3C
  54. #define VENC_BLANK_LEVEL 0x40
  55. #define VENC_X_COLOR 0x44
  56. #define VENC_M_CONTROL 0x48
  57. #define VENC_BSTAMP_WSS_DATA 0x4C
  58. #define VENC_S_CARR 0x50
  59. #define VENC_LINE21 0x54
  60. #define VENC_LN_SEL 0x58
  61. #define VENC_L21__WC_CTL 0x5C
  62. #define VENC_HTRIGGER_VTRIGGER 0x60
  63. #define VENC_SAVID__EAVID 0x64
  64. #define VENC_FLEN__FAL 0x68
  65. #define VENC_LAL__PHASE_RESET 0x6C
  66. #define VENC_HS_INT_START_STOP_X 0x70
  67. #define VENC_HS_EXT_START_STOP_X 0x74
  68. #define VENC_VS_INT_START_X 0x78
  69. #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
  70. #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
  71. #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
  72. #define VENC_VS_EXT_STOP_Y 0x88
  73. #define VENC_AVID_START_STOP_X 0x90
  74. #define VENC_AVID_START_STOP_Y 0x94
  75. #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
  76. #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
  77. #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
  78. #define VENC_TVDETGP_INT_START_STOP_X 0xB0
  79. #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
  80. #define VENC_GEN_CTRL 0xB8
  81. #define VENC_OUTPUT_CONTROL 0xC4
  82. #define VENC_OUTPUT_TEST 0xC8
  83. #define VENC_DAC_B__DAC_C 0xC8
  84. struct venc_config {
  85. u32 f_control;
  86. u32 vidout_ctrl;
  87. u32 sync_ctrl;
  88. u32 llen;
  89. u32 flens;
  90. u32 hfltr_ctrl;
  91. u32 cc_carr_wss_carr;
  92. u32 c_phase;
  93. u32 gain_u;
  94. u32 gain_v;
  95. u32 gain_y;
  96. u32 black_level;
  97. u32 blank_level;
  98. u32 x_color;
  99. u32 m_control;
  100. u32 bstamp_wss_data;
  101. u32 s_carr;
  102. u32 line21;
  103. u32 ln_sel;
  104. u32 l21__wc_ctl;
  105. u32 htrigger_vtrigger;
  106. u32 savid__eavid;
  107. u32 flen__fal;
  108. u32 lal__phase_reset;
  109. u32 hs_int_start_stop_x;
  110. u32 hs_ext_start_stop_x;
  111. u32 vs_int_start_x;
  112. u32 vs_int_stop_x__vs_int_start_y;
  113. u32 vs_int_stop_y__vs_ext_start_x;
  114. u32 vs_ext_stop_x__vs_ext_start_y;
  115. u32 vs_ext_stop_y;
  116. u32 avid_start_stop_x;
  117. u32 avid_start_stop_y;
  118. u32 fid_int_start_x__fid_int_start_y;
  119. u32 fid_int_offset_y__fid_ext_start_x;
  120. u32 fid_ext_start_y__fid_ext_offset_y;
  121. u32 tvdetgp_int_start_stop_x;
  122. u32 tvdetgp_int_start_stop_y;
  123. u32 gen_ctrl;
  124. };
  125. /* from TRM */
  126. static const struct venc_config venc_config_pal_trm = {
  127. .f_control = 0,
  128. .vidout_ctrl = 1,
  129. .sync_ctrl = 0x40,
  130. .llen = 0x35F, /* 863 */
  131. .flens = 0x270, /* 624 */
  132. .hfltr_ctrl = 0,
  133. .cc_carr_wss_carr = 0x2F7225ED,
  134. .c_phase = 0,
  135. .gain_u = 0x111,
  136. .gain_v = 0x181,
  137. .gain_y = 0x140,
  138. .black_level = 0x3B,
  139. .blank_level = 0x3B,
  140. .x_color = 0x7,
  141. .m_control = 0x2,
  142. .bstamp_wss_data = 0x3F,
  143. .s_carr = 0x2A098ACB,
  144. .line21 = 0,
  145. .ln_sel = 0x01290015,
  146. .l21__wc_ctl = 0x0000F603,
  147. .htrigger_vtrigger = 0,
  148. .savid__eavid = 0x06A70108,
  149. .flen__fal = 0x00180270,
  150. .lal__phase_reset = 0x00040135,
  151. .hs_int_start_stop_x = 0x00880358,
  152. .hs_ext_start_stop_x = 0x000F035F,
  153. .vs_int_start_x = 0x01A70000,
  154. .vs_int_stop_x__vs_int_start_y = 0x000001A7,
  155. .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
  156. .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
  157. .vs_ext_stop_y = 0x00000025,
  158. .avid_start_stop_x = 0x03530083,
  159. .avid_start_stop_y = 0x026C002E,
  160. .fid_int_start_x__fid_int_start_y = 0x0001008A,
  161. .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
  162. .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
  163. .tvdetgp_int_start_stop_x = 0x00140001,
  164. .tvdetgp_int_start_stop_y = 0x00010001,
  165. .gen_ctrl = 0x00FF0000,
  166. };
  167. /* from TRM */
  168. static const struct venc_config venc_config_ntsc_trm = {
  169. .f_control = 0,
  170. .vidout_ctrl = 1,
  171. .sync_ctrl = 0x8040,
  172. .llen = 0x359,
  173. .flens = 0x20C,
  174. .hfltr_ctrl = 0,
  175. .cc_carr_wss_carr = 0x043F2631,
  176. .c_phase = 0,
  177. .gain_u = 0x102,
  178. .gain_v = 0x16C,
  179. .gain_y = 0x12F,
  180. .black_level = 0x43,
  181. .blank_level = 0x38,
  182. .x_color = 0x7,
  183. .m_control = 0x1,
  184. .bstamp_wss_data = 0x38,
  185. .s_carr = 0x21F07C1F,
  186. .line21 = 0,
  187. .ln_sel = 0x01310011,
  188. .l21__wc_ctl = 0x0000F003,
  189. .htrigger_vtrigger = 0,
  190. .savid__eavid = 0x069300F4,
  191. .flen__fal = 0x0016020C,
  192. .lal__phase_reset = 0x00060107,
  193. .hs_int_start_stop_x = 0x008E0350,
  194. .hs_ext_start_stop_x = 0x000F0359,
  195. .vs_int_start_x = 0x01A00000,
  196. .vs_int_stop_x__vs_int_start_y = 0x020701A0,
  197. .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
  198. .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
  199. .vs_ext_stop_y = 0x00000006,
  200. .avid_start_stop_x = 0x03480078,
  201. .avid_start_stop_y = 0x02060024,
  202. .fid_int_start_x__fid_int_start_y = 0x0001008A,
  203. .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
  204. .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
  205. .tvdetgp_int_start_stop_x = 0x00140001,
  206. .tvdetgp_int_start_stop_y = 0x00010001,
  207. .gen_ctrl = 0x00F90000,
  208. };
  209. static const struct venc_config venc_config_pal_bdghi = {
  210. .f_control = 0,
  211. .vidout_ctrl = 0,
  212. .sync_ctrl = 0,
  213. .hfltr_ctrl = 0,
  214. .x_color = 0,
  215. .line21 = 0,
  216. .ln_sel = 21,
  217. .htrigger_vtrigger = 0,
  218. .tvdetgp_int_start_stop_x = 0x00140001,
  219. .tvdetgp_int_start_stop_y = 0x00010001,
  220. .gen_ctrl = 0x00FB0000,
  221. .llen = 864-1,
  222. .flens = 625-1,
  223. .cc_carr_wss_carr = 0x2F7625ED,
  224. .c_phase = 0xDF,
  225. .gain_u = 0x111,
  226. .gain_v = 0x181,
  227. .gain_y = 0x140,
  228. .black_level = 0x3e,
  229. .blank_level = 0x3e,
  230. .m_control = 0<<2 | 1<<1,
  231. .bstamp_wss_data = 0x42,
  232. .s_carr = 0x2a098acb,
  233. .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
  234. .savid__eavid = 0x06A70108,
  235. .flen__fal = 23<<16 | 624<<0,
  236. .lal__phase_reset = 2<<17 | 310<<0,
  237. .hs_int_start_stop_x = 0x00920358,
  238. .hs_ext_start_stop_x = 0x000F035F,
  239. .vs_int_start_x = 0x1a7<<16,
  240. .vs_int_stop_x__vs_int_start_y = 0x000601A7,
  241. .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
  242. .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
  243. .vs_ext_stop_y = 0x05,
  244. .avid_start_stop_x = 0x03530082,
  245. .avid_start_stop_y = 0x0270002E,
  246. .fid_int_start_x__fid_int_start_y = 0x0005008A,
  247. .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
  248. .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
  249. };
  250. const struct omap_video_timings omap_dss_pal_timings = {
  251. .x_res = 720,
  252. .y_res = 574,
  253. .pixel_clock = 13500,
  254. .hsw = 64,
  255. .hfp = 12,
  256. .hbp = 68,
  257. .vsw = 5,
  258. .vfp = 5,
  259. .vbp = 41,
  260. };
  261. EXPORT_SYMBOL(omap_dss_pal_timings);
  262. const struct omap_video_timings omap_dss_ntsc_timings = {
  263. .x_res = 720,
  264. .y_res = 482,
  265. .pixel_clock = 13500,
  266. .hsw = 64,
  267. .hfp = 16,
  268. .hbp = 58,
  269. .vsw = 6,
  270. .vfp = 6,
  271. .vbp = 31,
  272. };
  273. EXPORT_SYMBOL(omap_dss_ntsc_timings);
  274. static struct {
  275. struct platform_device *pdev;
  276. void __iomem *base;
  277. struct mutex venc_lock;
  278. u32 wss_data;
  279. struct regulator *vdda_dac_reg;
  280. struct mutex runtime_lock;
  281. int runtime_count;
  282. struct clk *tv_clk;
  283. struct clk *tv_dac_clk;
  284. } venc;
  285. static inline void venc_write_reg(int idx, u32 val)
  286. {
  287. __raw_writel(val, venc.base + idx);
  288. }
  289. static inline u32 venc_read_reg(int idx)
  290. {
  291. u32 l = __raw_readl(venc.base + idx);
  292. return l;
  293. }
  294. static void venc_write_config(const struct venc_config *config)
  295. {
  296. DSSDBG("write venc conf\n");
  297. venc_write_reg(VENC_LLEN, config->llen);
  298. venc_write_reg(VENC_FLENS, config->flens);
  299. venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
  300. venc_write_reg(VENC_C_PHASE, config->c_phase);
  301. venc_write_reg(VENC_GAIN_U, config->gain_u);
  302. venc_write_reg(VENC_GAIN_V, config->gain_v);
  303. venc_write_reg(VENC_GAIN_Y, config->gain_y);
  304. venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
  305. venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
  306. venc_write_reg(VENC_M_CONTROL, config->m_control);
  307. venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
  308. venc.wss_data);
  309. venc_write_reg(VENC_S_CARR, config->s_carr);
  310. venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
  311. venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
  312. venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
  313. venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
  314. venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
  315. venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
  316. venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
  317. venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
  318. config->vs_int_stop_x__vs_int_start_y);
  319. venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
  320. config->vs_int_stop_y__vs_ext_start_x);
  321. venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
  322. config->vs_ext_stop_x__vs_ext_start_y);
  323. venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
  324. venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
  325. venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
  326. venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
  327. config->fid_int_start_x__fid_int_start_y);
  328. venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
  329. config->fid_int_offset_y__fid_ext_start_x);
  330. venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
  331. config->fid_ext_start_y__fid_ext_offset_y);
  332. venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
  333. venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
  334. venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
  335. venc_write_reg(VENC_X_COLOR, config->x_color);
  336. venc_write_reg(VENC_LINE21, config->line21);
  337. venc_write_reg(VENC_LN_SEL, config->ln_sel);
  338. venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
  339. venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
  340. config->tvdetgp_int_start_stop_x);
  341. venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
  342. config->tvdetgp_int_start_stop_y);
  343. venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
  344. venc_write_reg(VENC_F_CONTROL, config->f_control);
  345. venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
  346. }
  347. static void venc_reset(void)
  348. {
  349. int t = 1000;
  350. venc_write_reg(VENC_F_CONTROL, 1<<8);
  351. while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
  352. if (--t == 0) {
  353. DSSERR("Failed to reset venc\n");
  354. return;
  355. }
  356. }
  357. #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
  358. /* the magical sleep that makes things work */
  359. /* XXX more info? What bug this circumvents? */
  360. msleep(20);
  361. #endif
  362. }
  363. static int venc_runtime_get(void)
  364. {
  365. int r;
  366. mutex_lock(&venc.runtime_lock);
  367. if (venc.runtime_count++ == 0) {
  368. DSSDBG("venc_runtime_get\n");
  369. r = dss_runtime_get();
  370. if (r)
  371. goto err_get_dss;
  372. r = dispc_runtime_get();
  373. if (r)
  374. goto err_get_dispc;
  375. clk_enable(venc.tv_clk);
  376. if (venc.tv_dac_clk)
  377. clk_enable(venc.tv_dac_clk);
  378. r = pm_runtime_get_sync(&venc.pdev->dev);
  379. WARN_ON(r);
  380. if (r < 0)
  381. goto err_runtime_get;
  382. }
  383. mutex_unlock(&venc.runtime_lock);
  384. return 0;
  385. err_runtime_get:
  386. clk_disable(venc.tv_clk);
  387. if (venc.tv_dac_clk)
  388. clk_disable(venc.tv_dac_clk);
  389. dispc_runtime_put();
  390. err_get_dispc:
  391. dss_runtime_put();
  392. err_get_dss:
  393. mutex_unlock(&venc.runtime_lock);
  394. return r;
  395. }
  396. static void venc_runtime_put(void)
  397. {
  398. mutex_lock(&venc.runtime_lock);
  399. if (--venc.runtime_count == 0) {
  400. int r;
  401. DSSDBG("venc_runtime_put\n");
  402. r = pm_runtime_put_sync(&venc.pdev->dev);
  403. WARN_ON(r);
  404. clk_disable(venc.tv_clk);
  405. if (venc.tv_dac_clk)
  406. clk_disable(venc.tv_dac_clk);
  407. dispc_runtime_put();
  408. dss_runtime_put();
  409. }
  410. mutex_unlock(&venc.runtime_lock);
  411. }
  412. static const struct venc_config *venc_timings_to_config(
  413. struct omap_video_timings *timings)
  414. {
  415. if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
  416. return &venc_config_pal_trm;
  417. if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
  418. return &venc_config_ntsc_trm;
  419. BUG();
  420. }
  421. static void venc_power_on(struct omap_dss_device *dssdev)
  422. {
  423. u32 l;
  424. venc_reset();
  425. venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
  426. dss_set_venc_output(dssdev->phy.venc.type);
  427. dss_set_dac_pwrdn_bgz(1);
  428. l = 0;
  429. if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
  430. l |= 1 << 1;
  431. else /* S-Video */
  432. l |= (1 << 0) | (1 << 2);
  433. if (dssdev->phy.venc.invert_polarity == false)
  434. l |= 1 << 3;
  435. venc_write_reg(VENC_OUTPUT_CONTROL, l);
  436. dispc_set_digit_size(dssdev->panel.timings.x_res,
  437. dssdev->panel.timings.y_res/2);
  438. regulator_enable(venc.vdda_dac_reg);
  439. if (dssdev->platform_enable)
  440. dssdev->platform_enable(dssdev);
  441. dssdev->manager->enable(dssdev->manager);
  442. }
  443. static void venc_power_off(struct omap_dss_device *dssdev)
  444. {
  445. venc_write_reg(VENC_OUTPUT_CONTROL, 0);
  446. dss_set_dac_pwrdn_bgz(0);
  447. dssdev->manager->disable(dssdev->manager);
  448. if (dssdev->platform_disable)
  449. dssdev->platform_disable(dssdev);
  450. regulator_disable(venc.vdda_dac_reg);
  451. }
  452. /* driver */
  453. static int venc_panel_probe(struct omap_dss_device *dssdev)
  454. {
  455. dssdev->panel.timings = omap_dss_pal_timings;
  456. return 0;
  457. }
  458. static void venc_panel_remove(struct omap_dss_device *dssdev)
  459. {
  460. }
  461. static int venc_panel_enable(struct omap_dss_device *dssdev)
  462. {
  463. int r = 0;
  464. DSSDBG("venc_enable_display\n");
  465. mutex_lock(&venc.venc_lock);
  466. r = omap_dss_start_device(dssdev);
  467. if (r) {
  468. DSSERR("failed to start device\n");
  469. goto err0;
  470. }
  471. if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
  472. r = -EINVAL;
  473. goto err1;
  474. }
  475. r = venc_runtime_get();
  476. if (r)
  477. goto err1;
  478. venc_power_on(dssdev);
  479. venc.wss_data = 0;
  480. dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
  481. mutex_unlock(&venc.venc_lock);
  482. return 0;
  483. err1:
  484. omap_dss_stop_device(dssdev);
  485. err0:
  486. mutex_unlock(&venc.venc_lock);
  487. return r;
  488. }
  489. static void venc_panel_disable(struct omap_dss_device *dssdev)
  490. {
  491. DSSDBG("venc_disable_display\n");
  492. mutex_lock(&venc.venc_lock);
  493. if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
  494. goto end;
  495. if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
  496. /* suspended is the same as disabled with venc */
  497. dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
  498. goto end;
  499. }
  500. venc_power_off(dssdev);
  501. venc_runtime_put();
  502. dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
  503. omap_dss_stop_device(dssdev);
  504. end:
  505. mutex_unlock(&venc.venc_lock);
  506. }
  507. static int venc_panel_suspend(struct omap_dss_device *dssdev)
  508. {
  509. venc_panel_disable(dssdev);
  510. return 0;
  511. }
  512. static int venc_panel_resume(struct omap_dss_device *dssdev)
  513. {
  514. return venc_panel_enable(dssdev);
  515. }
  516. static enum omap_dss_update_mode venc_get_update_mode(
  517. struct omap_dss_device *dssdev)
  518. {
  519. return OMAP_DSS_UPDATE_AUTO;
  520. }
  521. static int venc_set_update_mode(struct omap_dss_device *dssdev,
  522. enum omap_dss_update_mode mode)
  523. {
  524. if (mode != OMAP_DSS_UPDATE_AUTO)
  525. return -EINVAL;
  526. return 0;
  527. }
  528. static void venc_get_timings(struct omap_dss_device *dssdev,
  529. struct omap_video_timings *timings)
  530. {
  531. *timings = dssdev->panel.timings;
  532. }
  533. static void venc_set_timings(struct omap_dss_device *dssdev,
  534. struct omap_video_timings *timings)
  535. {
  536. DSSDBG("venc_set_timings\n");
  537. /* Reset WSS data when the TV standard changes. */
  538. if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
  539. venc.wss_data = 0;
  540. dssdev->panel.timings = *timings;
  541. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  542. /* turn the venc off and on to get new timings to use */
  543. venc_panel_disable(dssdev);
  544. venc_panel_enable(dssdev);
  545. }
  546. }
  547. static int venc_check_timings(struct omap_dss_device *dssdev,
  548. struct omap_video_timings *timings)
  549. {
  550. DSSDBG("venc_check_timings\n");
  551. if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
  552. return 0;
  553. if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
  554. return 0;
  555. return -EINVAL;
  556. }
  557. static u32 venc_get_wss(struct omap_dss_device *dssdev)
  558. {
  559. /* Invert due to VENC_L21_WC_CTL:INV=1 */
  560. return (venc.wss_data >> 8) ^ 0xfffff;
  561. }
  562. static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
  563. {
  564. const struct venc_config *config;
  565. int r;
  566. DSSDBG("venc_set_wss\n");
  567. mutex_lock(&venc.venc_lock);
  568. config = venc_timings_to_config(&dssdev->panel.timings);
  569. /* Invert due to VENC_L21_WC_CTL:INV=1 */
  570. venc.wss_data = (wss ^ 0xfffff) << 8;
  571. r = venc_runtime_get();
  572. if (r)
  573. goto err;
  574. venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
  575. venc.wss_data);
  576. venc_runtime_put();
  577. err:
  578. mutex_unlock(&venc.venc_lock);
  579. return r;
  580. }
  581. static struct omap_dss_driver venc_driver = {
  582. .probe = venc_panel_probe,
  583. .remove = venc_panel_remove,
  584. .enable = venc_panel_enable,
  585. .disable = venc_panel_disable,
  586. .suspend = venc_panel_suspend,
  587. .resume = venc_panel_resume,
  588. .get_resolution = omapdss_default_get_resolution,
  589. .get_recommended_bpp = omapdss_default_get_recommended_bpp,
  590. .set_update_mode = venc_set_update_mode,
  591. .get_update_mode = venc_get_update_mode,
  592. .get_timings = venc_get_timings,
  593. .set_timings = venc_set_timings,
  594. .check_timings = venc_check_timings,
  595. .get_wss = venc_get_wss,
  596. .set_wss = venc_set_wss,
  597. .driver = {
  598. .name = "venc",
  599. .owner = THIS_MODULE,
  600. },
  601. };
  602. /* driver end */
  603. int venc_init_display(struct omap_dss_device *dssdev)
  604. {
  605. DSSDBG("init_display\n");
  606. if (venc.vdda_dac_reg == NULL) {
  607. struct regulator *vdda_dac;
  608. vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
  609. if (IS_ERR(vdda_dac)) {
  610. DSSERR("can't get VDDA_DAC regulator\n");
  611. return PTR_ERR(vdda_dac);
  612. }
  613. venc.vdda_dac_reg = vdda_dac;
  614. }
  615. return 0;
  616. }
  617. void venc_dump_regs(struct seq_file *s)
  618. {
  619. #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
  620. if (venc_runtime_get())
  621. return;
  622. DUMPREG(VENC_F_CONTROL);
  623. DUMPREG(VENC_VIDOUT_CTRL);
  624. DUMPREG(VENC_SYNC_CTRL);
  625. DUMPREG(VENC_LLEN);
  626. DUMPREG(VENC_FLENS);
  627. DUMPREG(VENC_HFLTR_CTRL);
  628. DUMPREG(VENC_CC_CARR_WSS_CARR);
  629. DUMPREG(VENC_C_PHASE);
  630. DUMPREG(VENC_GAIN_U);
  631. DUMPREG(VENC_GAIN_V);
  632. DUMPREG(VENC_GAIN_Y);
  633. DUMPREG(VENC_BLACK_LEVEL);
  634. DUMPREG(VENC_BLANK_LEVEL);
  635. DUMPREG(VENC_X_COLOR);
  636. DUMPREG(VENC_M_CONTROL);
  637. DUMPREG(VENC_BSTAMP_WSS_DATA);
  638. DUMPREG(VENC_S_CARR);
  639. DUMPREG(VENC_LINE21);
  640. DUMPREG(VENC_LN_SEL);
  641. DUMPREG(VENC_L21__WC_CTL);
  642. DUMPREG(VENC_HTRIGGER_VTRIGGER);
  643. DUMPREG(VENC_SAVID__EAVID);
  644. DUMPREG(VENC_FLEN__FAL);
  645. DUMPREG(VENC_LAL__PHASE_RESET);
  646. DUMPREG(VENC_HS_INT_START_STOP_X);
  647. DUMPREG(VENC_HS_EXT_START_STOP_X);
  648. DUMPREG(VENC_VS_INT_START_X);
  649. DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
  650. DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
  651. DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
  652. DUMPREG(VENC_VS_EXT_STOP_Y);
  653. DUMPREG(VENC_AVID_START_STOP_X);
  654. DUMPREG(VENC_AVID_START_STOP_Y);
  655. DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
  656. DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
  657. DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
  658. DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
  659. DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
  660. DUMPREG(VENC_GEN_CTRL);
  661. DUMPREG(VENC_OUTPUT_CONTROL);
  662. DUMPREG(VENC_OUTPUT_TEST);
  663. venc_runtime_put();
  664. #undef DUMPREG
  665. }
  666. static int venc_get_clocks(struct platform_device *pdev)
  667. {
  668. struct clk *clk;
  669. clk = clk_get(&pdev->dev, "tv_clk");
  670. if (IS_ERR(clk)) {
  671. DSSERR("can't get tv_clk\n");
  672. return PTR_ERR(clk);
  673. }
  674. venc.tv_clk = clk;
  675. if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
  676. clk = clk_get(&pdev->dev, "tv_dac_clk");
  677. if (IS_ERR(clk)) {
  678. DSSERR("can't get tv_dac_clk\n");
  679. clk_put(venc.tv_clk);
  680. return PTR_ERR(clk);
  681. }
  682. } else {
  683. clk = NULL;
  684. }
  685. venc.tv_dac_clk = clk;
  686. return 0;
  687. }
  688. static void venc_put_clocks(void)
  689. {
  690. if (venc.tv_clk)
  691. clk_put(venc.tv_clk);
  692. if (venc.tv_dac_clk)
  693. clk_put(venc.tv_dac_clk);
  694. }
  695. /* VENC HW IP initialisation */
  696. static int omap_venchw_probe(struct platform_device *pdev)
  697. {
  698. u8 rev_id;
  699. struct resource *venc_mem;
  700. int r;
  701. venc.pdev = pdev;
  702. mutex_init(&venc.venc_lock);
  703. venc.wss_data = 0;
  704. venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
  705. if (!venc_mem) {
  706. DSSERR("can't get IORESOURCE_MEM VENC\n");
  707. r = -EINVAL;
  708. goto err_ioremap;
  709. }
  710. venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
  711. if (!venc.base) {
  712. DSSERR("can't ioremap VENC\n");
  713. r = -ENOMEM;
  714. goto err_ioremap;
  715. }
  716. r = venc_get_clocks(pdev);
  717. if (r)
  718. goto err_get_clk;
  719. mutex_init(&venc.runtime_lock);
  720. pm_runtime_enable(&pdev->dev);
  721. r = venc_runtime_get();
  722. if (r)
  723. goto err_get_venc;
  724. rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
  725. dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
  726. venc_runtime_put();
  727. return omap_dss_register_driver(&venc_driver);
  728. err_get_venc:
  729. pm_runtime_disable(&pdev->dev);
  730. venc_put_clocks();
  731. err_get_clk:
  732. iounmap(venc.base);
  733. err_ioremap:
  734. return r;
  735. }
  736. static int omap_venchw_remove(struct platform_device *pdev)
  737. {
  738. if (venc.vdda_dac_reg != NULL) {
  739. regulator_put(venc.vdda_dac_reg);
  740. venc.vdda_dac_reg = NULL;
  741. }
  742. omap_dss_unregister_driver(&venc_driver);
  743. pm_runtime_disable(&pdev->dev);
  744. venc_put_clocks();
  745. iounmap(venc.base);
  746. return 0;
  747. }
  748. static struct platform_driver omap_venchw_driver = {
  749. .probe = omap_venchw_probe,
  750. .remove = omap_venchw_remove,
  751. .driver = {
  752. .name = "omapdss_venc",
  753. .owner = THIS_MODULE,
  754. },
  755. };
  756. int venc_init_platform_driver(void)
  757. {
  758. if (cpu_is_omap44xx())
  759. return 0;
  760. return platform_driver_register(&omap_venchw_driver);
  761. }
  762. void venc_uninit_platform_driver(void)
  763. {
  764. if (cpu_is_omap44xx())
  765. return;
  766. return platform_driver_unregister(&omap_venchw_driver);
  767. }