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/drivers/video/i810/i810.h

https://bitbucket.org/wisechild/galaxy-nexus
C++ Header | 299 lines | 234 code | 33 blank | 32 comment | 0 complexity | bb4550151d4dec60da467903e05c0bd6 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*-*- linux-c -*-
  2. * linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
  3. *
  4. * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
  5. * All Rights Reserved
  6. *
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file COPYING in the main directory of this archive for
  10. * more details.
  11. */
  12. #ifndef __I810_H__
  13. #define __I810_H__
  14. #include <linux/list.h>
  15. #include <linux/agp_backend.h>
  16. #include <linux/fb.h>
  17. #include <linux/i2c.h>
  18. #include <linux/i2c-algo-bit.h>
  19. #include <video/vga.h>
  20. /* Fence */
  21. #define TILEWALK_X (0 << 12)
  22. #define TILEWALK_Y (1 << 12)
  23. /* Raster ops */
  24. #define COLOR_COPY_ROP 0xF0
  25. #define PAT_COPY_ROP 0xCC
  26. #define CLEAR_ROP 0x00
  27. #define WHITE_ROP 0xFF
  28. #define INVERT_ROP 0x55
  29. #define XOR_ROP 0x5A
  30. /* 2D Engine definitions */
  31. #define SOLIDPATTERN 0x80000000
  32. #define NONSOLID 0x00000000
  33. #define BPP8 (0 << 24)
  34. #define BPP16 (1 << 24)
  35. #define BPP24 (2 << 24)
  36. #define PIXCONF8 (2 << 16)
  37. #define PIXCONF15 (4 << 16)
  38. #define PIXCONF16 (5 << 16)
  39. #define PIXCONF24 (6 << 16)
  40. #define PIXCONF32 (7 << 16)
  41. #define DYN_COLOR_EN (1 << 26)
  42. #define DYN_COLOR_DIS (0 << 26)
  43. #define INCREMENT 0x00000000
  44. #define DECREMENT (0x01 << 30)
  45. #define ARB_ON 0x00000001
  46. #define ARB_OFF 0x00000000
  47. #define SYNC_FLIP 0x00000000
  48. #define ASYNC_FLIP 0x00000040
  49. #define OPTYPE_MASK 0xE0000000
  50. #define PARSER_MASK 0x001F8000
  51. #define D2_MASK 0x001FC000 /* 2D mask */
  52. /* Instruction type */
  53. /* There are more but pertains to 3D */
  54. #define PARSER 0x00000000
  55. #define BLIT (0x02 << 29)
  56. #define RENDER (0x03 << 29)
  57. /* Parser */
  58. #define NOP 0x00 /* No operation, padding */
  59. #define BP_INT (0x01 << 23) /* Breakpoint interrupt */
  60. #define USR_INT (0x02 << 23) /* User interrupt */
  61. #define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
  62. #define FLUSH (0x04 << 23)
  63. #define CONTEXT_SEL (0x05 << 23)
  64. #define REPORT_HEAD (0x07 << 23)
  65. #define ARB_ON_OFF (0x08 << 23)
  66. #define OVERLAY_FLIP (0x11 << 23)
  67. #define LOAD_SCAN_INC (0x12 << 23)
  68. #define LOAD_SCAN_EX (0x13 << 23)
  69. #define FRONT_BUFFER (0x14 << 23)
  70. #define DEST_BUFFER (0x15 << 23)
  71. #define Z_BUFFER (0x16 << 23)
  72. #define STORE_DWORD_IMM (0x20 << 23)
  73. #define STORE_DWORD_IDX (0x21 << 23)
  74. #define BATCH_BUFFER (0x30 << 23)
  75. /* Blit */
  76. #define SETUP_BLIT 0x00
  77. #define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
  78. #define PIXEL_BLT (0x20 << 22)
  79. #define SCANLINE_BLT (0x21 << 22)
  80. #define TEXT_BLT (0x22 << 22)
  81. #define TEXT_IMM_BLT (0x30 << 22)
  82. #define COLOR_BLT (0x40 << 22)
  83. #define MONO_PAT_BLIT (0x42 << 22)
  84. #define SOURCE_COPY_BLIT (0x43 << 22)
  85. #define MONO_SOURCE_COPY_BLIT (0x44 << 22)
  86. #define SOURCE_COPY_IMMEDIATE (0x60 << 22)
  87. #define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
  88. #define VERSION_MAJOR 0
  89. #define VERSION_MINOR 9
  90. #define VERSION_TEENIE 0
  91. #define BRANCH_VERSION ""
  92. /* mvo: intel i815 */
  93. #ifndef PCI_DEVICE_ID_INTEL_82815_100
  94. #define PCI_DEVICE_ID_INTEL_82815_100 0x1102
  95. #endif
  96. #ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
  97. #define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
  98. #endif
  99. #ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
  100. #define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
  101. #endif
  102. /* General Defines */
  103. #define I810_PAGESIZE 4096
  104. #define MAX_DMA_SIZE (1024 * 4096)
  105. #define SAREA_SIZE 4096
  106. #define PCI_I810_MISCC 0x72
  107. #define MMIO_SIZE (512*1024)
  108. #define GTT_SIZE (16*1024)
  109. #define RINGBUFFER_SIZE (64*1024)
  110. #define CURSOR_SIZE 4096
  111. #define OFF 0
  112. #define ON 1
  113. #define MAX_KEY 256
  114. #define WAIT_COUNT 10000000
  115. #define IRING_PAD 8
  116. #define FONTDATAMAX 8192
  117. /* Masks (AND ops) and OR's */
  118. #define FB_START_MASK (0x3f << (32 - 6))
  119. #define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
  120. #define FREQ_MASK (1 << 4)
  121. #define SCR_OFF 0x20
  122. #define DRAM_ON 0x08
  123. #define DRAM_OFF 0xE7
  124. #define PG_ENABLE_MASK 0x01
  125. #define RING_SIZE_MASK (RINGBUFFER_SIZE - 1);
  126. /* defines for restoring registers partially */
  127. #define ADDR_MAP_MASK (0x07 << 5)
  128. #define DISP_CTRL ~0
  129. #define PIXCONF_0 (0x64 << 8)
  130. #define PIXCONF_2 (0xF3 << 24)
  131. #define PIXCONF_1 (0xF0 << 16)
  132. #define MN_MASK 0x3FF03FF
  133. #define P_OR (0x7 << 4)
  134. #define DAC_BIT (1 << 16)
  135. #define INTERLACE_BIT (1 << 7)
  136. #define IER_MASK (3 << 13)
  137. #define IMR_MASK (3 << 13)
  138. /* Power Management */
  139. #define DPMS_MASK 0xF0000
  140. #define POWERON 0x00000
  141. #define STANDBY 0x20000
  142. #define SUSPEND 0x80000
  143. #define POWERDOWN 0xA0000
  144. #define EMR_MASK ~0x3F
  145. #define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
  146. /* Ringbuffer */
  147. #define RBUFFER_START_MASK 0xFFFFF000
  148. #define RBUFFER_SIZE_MASK 0x001FF000
  149. #define RBUFFER_HEAD_MASK 0x001FFFFC
  150. #define RBUFFER_TAIL_MASK 0x001FFFF8
  151. /* Video Timings */
  152. #define REF_FREQ 24000000
  153. #define TARGET_N_MAX 30
  154. #define MAX_PIXELCLOCK 230000000
  155. #define MIN_PIXELCLOCK 15000000
  156. #define VFMAX 60
  157. #define VFMIN 60
  158. #define HFMAX 30000
  159. #define HFMIN 29000
  160. /* Cursor */
  161. #define CURSOR_ENABLE_MASK 0x1000
  162. #define CURSOR_MODE_64_TRANS 4
  163. #define CURSOR_MODE_64_XOR 5
  164. #define CURSOR_MODE_64_3C 6
  165. #define COORD_INACTIVE 0
  166. #define COORD_ACTIVE (1 << 4)
  167. #define EXTENDED_PALETTE 1
  168. /* AGP Memory Types*/
  169. #define AGP_NORMAL_MEMORY 0
  170. #define AGP_DCACHE_MEMORY 1
  171. #define AGP_PHYSICAL_MEMORY 2
  172. /* Allocated resource Flags */
  173. #define FRAMEBUFFER_REQ 1
  174. #define MMIO_REQ 2
  175. #define PCI_DEVICE_ENABLED 4
  176. #define HAS_FONTCACHE 8
  177. /* driver flags */
  178. #define HAS_MTRR 1
  179. #define HAS_ACCELERATION 2
  180. #define ALWAYS_SYNC 4
  181. #define LOCKUP 8
  182. struct gtt_data {
  183. struct agp_memory *i810_fb_memory;
  184. struct agp_memory *i810_cursor_memory;
  185. };
  186. struct mode_registers {
  187. u32 pixclock, M, N, P;
  188. u8 cr00, cr01, cr02, cr03;
  189. u8 cr04, cr05, cr06, cr07;
  190. u8 cr09, cr10, cr11, cr12;
  191. u8 cr13, cr15, cr16, cr30;
  192. u8 cr31, cr32, cr33, cr35, cr39;
  193. u32 bpp8_100, bpp16_100;
  194. u32 bpp24_100, bpp8_133;
  195. u32 bpp16_133, bpp24_133;
  196. u8 msr;
  197. };
  198. struct heap_data {
  199. unsigned long physical;
  200. __u8 __iomem *virtual;
  201. u32 offset;
  202. u32 size;
  203. };
  204. struct state_registers {
  205. u32 dclk_1d, dclk_2d, dclk_0ds;
  206. u32 pixconf, fw_blc, pgtbl_ctl;
  207. u32 fence0, hws_pga, dplystas;
  208. u16 bltcntl, hwstam, ier, iir, imr;
  209. u8 cr00, cr01, cr02, cr03, cr04;
  210. u8 cr05, cr06, cr07, cr08, cr09;
  211. u8 cr10, cr11, cr12, cr13, cr14;
  212. u8 cr15, cr16, cr17, cr80, gr10;
  213. u8 cr30, cr31, cr32, cr33, cr35;
  214. u8 cr39, cr41, cr70, sr01, msr;
  215. };
  216. struct i810fb_par;
  217. struct i810fb_i2c_chan {
  218. struct i810fb_par *par;
  219. struct i2c_adapter adapter;
  220. struct i2c_algo_bit_data algo;
  221. unsigned long ddc_base;
  222. };
  223. struct i810fb_par {
  224. struct mode_registers regs;
  225. struct state_registers hw_state;
  226. struct gtt_data i810_gtt;
  227. struct fb_ops i810fb_ops;
  228. struct pci_dev *dev;
  229. struct heap_data aperture;
  230. struct heap_data fb;
  231. struct heap_data iring;
  232. struct heap_data cursor_heap;
  233. struct vgastate state;
  234. struct i810fb_i2c_chan chan[3];
  235. struct mutex open_lock;
  236. unsigned int use_count;
  237. u32 pseudo_palette[16];
  238. unsigned long mmio_start_phys;
  239. u8 __iomem *mmio_start_virtual;
  240. u8 *edid;
  241. u32 pitch;
  242. u32 pixconf;
  243. u32 watermark;
  244. u32 mem_freq;
  245. u32 res_flags;
  246. u32 dev_flags;
  247. u32 cur_tail;
  248. u32 depth;
  249. u32 blit_bpp;
  250. u32 ovract;
  251. u32 cur_state;
  252. u32 ddc_num;
  253. int mtrr_reg;
  254. u16 bltcntl;
  255. u8 interlace;
  256. };
  257. /*
  258. * Register I/O
  259. */
  260. #define i810_readb(where, mmio) readb(mmio + where)
  261. #define i810_readw(where, mmio) readw(mmio + where)
  262. #define i810_readl(where, mmio) readl(mmio + where)
  263. #define i810_writeb(where, mmio, val) writeb(val, mmio + where)
  264. #define i810_writew(where, mmio, val) writew(val, mmio + where)
  265. #define i810_writel(where, mmio, val) writel(val, mmio + where)
  266. #endif /* __I810_H__ */