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/drivers/media/video/pvrusb2/pvrusb2-hdw.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 5322 lines | 4253 code | 603 blank | 466 comment | 711 complexity | 7c94954335ac73ba1975e7d8876f4c34 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/*
   2 *
   3 *
   4 *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 *  You should have received a copy of the GNU General Public License
  16 *  along with this program; if not, write to the Free Software
  17 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18 *
  19 */
  20
  21#include <linux/errno.h>
  22#include <linux/string.h>
  23#include <linux/slab.h>
  24#include <linux/firmware.h>
  25#include <linux/videodev2.h>
  26#include <media/v4l2-common.h>
  27#include <media/tuner.h>
  28#include "pvrusb2.h"
  29#include "pvrusb2-std.h"
  30#include "pvrusb2-util.h"
  31#include "pvrusb2-hdw.h"
  32#include "pvrusb2-i2c-core.h"
  33#include "pvrusb2-eeprom.h"
  34#include "pvrusb2-hdw-internal.h"
  35#include "pvrusb2-encoder.h"
  36#include "pvrusb2-debug.h"
  37#include "pvrusb2-fx2-cmd.h"
  38#include "pvrusb2-wm8775.h"
  39#include "pvrusb2-video-v4l.h"
  40#include "pvrusb2-cx2584x-v4l.h"
  41#include "pvrusb2-cs53l32a.h"
  42#include "pvrusb2-audio.h"
  43
  44#define TV_MIN_FREQ     55250000L
  45#define TV_MAX_FREQ    850000000L
  46
  47/* This defines a minimum interval that the decoder must remain quiet
  48   before we are allowed to start it running. */
  49#define TIME_MSEC_DECODER_WAIT 50
  50
  51/* This defines a minimum interval that the decoder must be allowed to run
  52   before we can safely begin using its streaming output. */
  53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  54
  55/* This defines a minimum interval that the encoder must remain quiet
  56   before we are allowed to configure it. */
  57#define TIME_MSEC_ENCODER_WAIT 50
  58
  59/* This defines the minimum interval that the encoder must successfully run
  60   before we consider that the encoder has run at least once since its
  61   firmware has been loaded.  This measurement is in important for cases
  62   where we can't do something until we know that the encoder has been run
  63   at least once. */
  64#define TIME_MSEC_ENCODER_OK 250
  65
  66static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  67static DEFINE_MUTEX(pvr2_unit_mtx);
  68
  69static int ctlchg;
  70static int procreload;
  71static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  72static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  73static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  74static int init_pause_msec;
  75
  76module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  77MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  78module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  79MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  80module_param(procreload, int, S_IRUGO|S_IWUSR);
  81MODULE_PARM_DESC(procreload,
  82		 "Attempt init failure recovery with firmware reload");
  83module_param_array(tuner,    int, NULL, 0444);
  84MODULE_PARM_DESC(tuner,"specify installed tuner type");
  85module_param_array(video_std,    int, NULL, 0444);
  86MODULE_PARM_DESC(video_std,"specify initial video standard");
  87module_param_array(tolerance,    int, NULL, 0444);
  88MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  89
  90/* US Broadcast channel 3 (61.25 MHz), to help with testing */
  91static int default_tv_freq    = 61250000L;
  92/* 104.3 MHz, a usable FM station for my area */
  93static int default_radio_freq = 104300000L;
  94
  95module_param_named(tv_freq, default_tv_freq, int, 0444);
  96MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  97module_param_named(radio_freq, default_radio_freq, int, 0444);
  98MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  99
 100#define PVR2_CTL_WRITE_ENDPOINT  0x01
 101#define PVR2_CTL_READ_ENDPOINT   0x81
 102
 103#define PVR2_GPIO_IN 0x9008
 104#define PVR2_GPIO_OUT 0x900c
 105#define PVR2_GPIO_DIR 0x9020
 106
 107#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 108
 109#define PVR2_FIRMWARE_ENDPOINT   0x02
 110
 111/* size of a firmware chunk */
 112#define FIRMWARE_CHUNK_SIZE 0x2000
 113
 114typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 115					struct v4l2_subdev *);
 116
 117static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 118	[PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 119	[PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 120	[PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 121	[PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 122	[PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 123};
 124
 125static const char *module_names[] = {
 126	[PVR2_CLIENT_ID_MSP3400] = "msp3400",
 127	[PVR2_CLIENT_ID_CX25840] = "cx25840",
 128	[PVR2_CLIENT_ID_SAA7115] = "saa7115",
 129	[PVR2_CLIENT_ID_TUNER] = "tuner",
 130	[PVR2_CLIENT_ID_DEMOD] = "tuner",
 131	[PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 132	[PVR2_CLIENT_ID_WM8775] = "wm8775",
 133};
 134
 135
 136static const unsigned char *module_i2c_addresses[] = {
 137	[PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 138	[PVR2_CLIENT_ID_DEMOD] = "\x43",
 139	[PVR2_CLIENT_ID_MSP3400] = "\x40",
 140	[PVR2_CLIENT_ID_SAA7115] = "\x21",
 141	[PVR2_CLIENT_ID_WM8775] = "\x1b",
 142	[PVR2_CLIENT_ID_CX25840] = "\x44",
 143	[PVR2_CLIENT_ID_CS53L32A] = "\x11",
 144};
 145
 146
 147static const char *ir_scheme_names[] = {
 148	[PVR2_IR_SCHEME_NONE] = "none",
 149	[PVR2_IR_SCHEME_29XXX] = "29xxx",
 150	[PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 151	[PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 152	[PVR2_IR_SCHEME_ZILOG] = "Zilog",
 153};
 154
 155
 156/* Define the list of additional controls we'll dynamically construct based
 157   on query of the cx2341x module. */
 158struct pvr2_mpeg_ids {
 159	const char *strid;
 160	int id;
 161};
 162static const struct pvr2_mpeg_ids mpeg_ids[] = {
 163	{
 164		.strid = "audio_layer",
 165		.id = V4L2_CID_MPEG_AUDIO_ENCODING,
 166	},{
 167		.strid = "audio_bitrate",
 168		.id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 169	},{
 170		/* Already using audio_mode elsewhere :-( */
 171		.strid = "mpeg_audio_mode",
 172		.id = V4L2_CID_MPEG_AUDIO_MODE,
 173	},{
 174		.strid = "mpeg_audio_mode_extension",
 175		.id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 176	},{
 177		.strid = "audio_emphasis",
 178		.id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 179	},{
 180		.strid = "audio_crc",
 181		.id = V4L2_CID_MPEG_AUDIO_CRC,
 182	},{
 183		.strid = "video_aspect",
 184		.id = V4L2_CID_MPEG_VIDEO_ASPECT,
 185	},{
 186		.strid = "video_b_frames",
 187		.id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 188	},{
 189		.strid = "video_gop_size",
 190		.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 191	},{
 192		.strid = "video_gop_closure",
 193		.id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 194	},{
 195		.strid = "video_bitrate_mode",
 196		.id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 197	},{
 198		.strid = "video_bitrate",
 199		.id = V4L2_CID_MPEG_VIDEO_BITRATE,
 200	},{
 201		.strid = "video_bitrate_peak",
 202		.id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 203	},{
 204		.strid = "video_temporal_decimation",
 205		.id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 206	},{
 207		.strid = "stream_type",
 208		.id = V4L2_CID_MPEG_STREAM_TYPE,
 209	},{
 210		.strid = "video_spatial_filter_mode",
 211		.id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 212	},{
 213		.strid = "video_spatial_filter",
 214		.id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 215	},{
 216		.strid = "video_luma_spatial_filter_type",
 217		.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 218	},{
 219		.strid = "video_chroma_spatial_filter_type",
 220		.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 221	},{
 222		.strid = "video_temporal_filter_mode",
 223		.id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 224	},{
 225		.strid = "video_temporal_filter",
 226		.id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 227	},{
 228		.strid = "video_median_filter_type",
 229		.id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 230	},{
 231		.strid = "video_luma_median_filter_top",
 232		.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 233	},{
 234		.strid = "video_luma_median_filter_bottom",
 235		.id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 236	},{
 237		.strid = "video_chroma_median_filter_top",
 238		.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 239	},{
 240		.strid = "video_chroma_median_filter_bottom",
 241		.id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 242	}
 243};
 244#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 245
 246
 247static const char *control_values_srate[] = {
 248	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 249	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 250	[V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 251};
 252
 253
 254
 255static const char *control_values_input[] = {
 256	[PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 257	[PVR2_CVAL_INPUT_DTV]       = "dtv",
 258	[PVR2_CVAL_INPUT_RADIO]     = "radio",
 259	[PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 260	[PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 261};
 262
 263
 264static const char *control_values_audiomode[] = {
 265	[V4L2_TUNER_MODE_MONO]   = "Mono",
 266	[V4L2_TUNER_MODE_STEREO] = "Stereo",
 267	[V4L2_TUNER_MODE_LANG1]  = "Lang1",
 268	[V4L2_TUNER_MODE_LANG2]  = "Lang2",
 269	[V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 270};
 271
 272
 273static const char *control_values_hsm[] = {
 274	[PVR2_CVAL_HSM_FAIL] = "Fail",
 275	[PVR2_CVAL_HSM_HIGH] = "High",
 276	[PVR2_CVAL_HSM_FULL] = "Full",
 277};
 278
 279
 280static const char *pvr2_state_names[] = {
 281	[PVR2_STATE_NONE] =    "none",
 282	[PVR2_STATE_DEAD] =    "dead",
 283	[PVR2_STATE_COLD] =    "cold",
 284	[PVR2_STATE_WARM] =    "warm",
 285	[PVR2_STATE_ERROR] =   "error",
 286	[PVR2_STATE_READY] =   "ready",
 287	[PVR2_STATE_RUN] =     "run",
 288};
 289
 290
 291struct pvr2_fx2cmd_descdef {
 292	unsigned char id;
 293	unsigned char *desc;
 294};
 295
 296static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 297	{FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 298	{FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 299	{FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 300	{FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 301	{FX2CMD_REG_WRITE, "write encoder register"},
 302	{FX2CMD_REG_READ, "read encoder register"},
 303	{FX2CMD_MEMSEL, "encoder memsel"},
 304	{FX2CMD_I2C_WRITE, "i2c write"},
 305	{FX2CMD_I2C_READ, "i2c read"},
 306	{FX2CMD_GET_USB_SPEED, "get USB speed"},
 307	{FX2CMD_STREAMING_ON, "stream on"},
 308	{FX2CMD_STREAMING_OFF, "stream off"},
 309	{FX2CMD_FWPOST1, "fwpost1"},
 310	{FX2CMD_POWER_OFF, "power off"},
 311	{FX2CMD_POWER_ON, "power on"},
 312	{FX2CMD_DEEP_RESET, "deep reset"},
 313	{FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 314	{FX2CMD_GET_IR_CODE, "get IR code"},
 315	{FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 316	{FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 317	{FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 318	{FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 319	{FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 320	{FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 321	{FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 322};
 323
 324
 325static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 326static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 327static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 328static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 329static void pvr2_hdw_worker_poll(struct work_struct *work);
 330static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 331static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 332static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 333static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 334static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 335static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 336static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 337static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 338static void pvr2_hdw_quiescent_timeout(unsigned long);
 339static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 340static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 341static void pvr2_hdw_encoder_run_timeout(unsigned long);
 342static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 343static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 344				unsigned int timeout,int probe_fl,
 345				void *write_data,unsigned int write_len,
 346				void *read_data,unsigned int read_len);
 347static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 348
 349
 350static void trace_stbit(const char *name,int val)
 351{
 352	pvr2_trace(PVR2_TRACE_STBITS,
 353		   "State bit %s <-- %s",
 354		   name,(val ? "true" : "false"));
 355}
 356
 357static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 358{
 359	struct pvr2_hdw *hdw = cptr->hdw;
 360	if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 361		*vp = hdw->freqTable[hdw->freqProgSlot-1];
 362	} else {
 363		*vp = 0;
 364	}
 365	return 0;
 366}
 367
 368static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 369{
 370	struct pvr2_hdw *hdw = cptr->hdw;
 371	unsigned int slotId = hdw->freqProgSlot;
 372	if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 373		hdw->freqTable[slotId-1] = v;
 374		/* Handle side effects correctly - if we're tuned to this
 375		   slot, then forgot the slot id relation since the stored
 376		   frequency has been changed. */
 377		if (hdw->freqSelector) {
 378			if (hdw->freqSlotRadio == slotId) {
 379				hdw->freqSlotRadio = 0;
 380			}
 381		} else {
 382			if (hdw->freqSlotTelevision == slotId) {
 383				hdw->freqSlotTelevision = 0;
 384			}
 385		}
 386	}
 387	return 0;
 388}
 389
 390static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 391{
 392	*vp = cptr->hdw->freqProgSlot;
 393	return 0;
 394}
 395
 396static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 397{
 398	struct pvr2_hdw *hdw = cptr->hdw;
 399	if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 400		hdw->freqProgSlot = v;
 401	}
 402	return 0;
 403}
 404
 405static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 406{
 407	struct pvr2_hdw *hdw = cptr->hdw;
 408	*vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 409	return 0;
 410}
 411
 412static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 413{
 414	unsigned freq = 0;
 415	struct pvr2_hdw *hdw = cptr->hdw;
 416	if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 417	if (slotId > 0) {
 418		freq = hdw->freqTable[slotId-1];
 419		if (!freq) return 0;
 420		pvr2_hdw_set_cur_freq(hdw,freq);
 421	}
 422	if (hdw->freqSelector) {
 423		hdw->freqSlotRadio = slotId;
 424	} else {
 425		hdw->freqSlotTelevision = slotId;
 426	}
 427	return 0;
 428}
 429
 430static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 431{
 432	*vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 433	return 0;
 434}
 435
 436static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 437{
 438	return cptr->hdw->freqDirty != 0;
 439}
 440
 441static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 442{
 443	cptr->hdw->freqDirty = 0;
 444}
 445
 446static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 447{
 448	pvr2_hdw_set_cur_freq(cptr->hdw,v);
 449	return 0;
 450}
 451
 452static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 453{
 454	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 455	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 456	if (stat != 0) {
 457		return stat;
 458	}
 459	*left = cap->bounds.left;
 460	return 0;
 461}
 462
 463static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 464{
 465	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 466	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 467	if (stat != 0) {
 468		return stat;
 469	}
 470	*left = cap->bounds.left;
 471	if (cap->bounds.width > cptr->hdw->cropw_val) {
 472		*left += cap->bounds.width - cptr->hdw->cropw_val;
 473	}
 474	return 0;
 475}
 476
 477static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 478{
 479	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 480	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 481	if (stat != 0) {
 482		return stat;
 483	}
 484	*top = cap->bounds.top;
 485	return 0;
 486}
 487
 488static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 489{
 490	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 491	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 492	if (stat != 0) {
 493		return stat;
 494	}
 495	*top = cap->bounds.top;
 496	if (cap->bounds.height > cptr->hdw->croph_val) {
 497		*top += cap->bounds.height - cptr->hdw->croph_val;
 498	}
 499	return 0;
 500}
 501
 502static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 503{
 504	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 505	int stat, bleftend, cleft;
 506
 507	stat = pvr2_hdw_check_cropcap(cptr->hdw);
 508	if (stat != 0) {
 509		return stat;
 510	}
 511	bleftend = cap->bounds.left+cap->bounds.width;
 512	cleft = cptr->hdw->cropl_val;
 513
 514	*width = cleft < bleftend ? bleftend-cleft : 0;
 515	return 0;
 516}
 517
 518static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 519{
 520	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521	int stat, btopend, ctop;
 522
 523	stat = pvr2_hdw_check_cropcap(cptr->hdw);
 524	if (stat != 0) {
 525		return stat;
 526	}
 527	btopend = cap->bounds.top+cap->bounds.height;
 528	ctop = cptr->hdw->cropt_val;
 529
 530	*height = ctop < btopend ? btopend-ctop : 0;
 531	return 0;
 532}
 533
 534static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 535{
 536	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 537	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 538	if (stat != 0) {
 539		return stat;
 540	}
 541	*val = cap->bounds.left;
 542	return 0;
 543}
 544
 545static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 546{
 547	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 548	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 549	if (stat != 0) {
 550		return stat;
 551	}
 552	*val = cap->bounds.top;
 553	return 0;
 554}
 555
 556static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 557{
 558	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 559	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 560	if (stat != 0) {
 561		return stat;
 562	}
 563	*val = cap->bounds.width;
 564	return 0;
 565}
 566
 567static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 568{
 569	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 570	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 571	if (stat != 0) {
 572		return stat;
 573	}
 574	*val = cap->bounds.height;
 575	return 0;
 576}
 577
 578static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 579{
 580	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 581	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 582	if (stat != 0) {
 583		return stat;
 584	}
 585	*val = cap->defrect.left;
 586	return 0;
 587}
 588
 589static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 590{
 591	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 592	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 593	if (stat != 0) {
 594		return stat;
 595	}
 596	*val = cap->defrect.top;
 597	return 0;
 598}
 599
 600static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 601{
 602	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 603	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 604	if (stat != 0) {
 605		return stat;
 606	}
 607	*val = cap->defrect.width;
 608	return 0;
 609}
 610
 611static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 612{
 613	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 614	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 615	if (stat != 0) {
 616		return stat;
 617	}
 618	*val = cap->defrect.height;
 619	return 0;
 620}
 621
 622static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 623{
 624	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 625	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 626	if (stat != 0) {
 627		return stat;
 628	}
 629	*val = cap->pixelaspect.numerator;
 630	return 0;
 631}
 632
 633static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 634{
 635	struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 636	int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 637	if (stat != 0) {
 638		return stat;
 639	}
 640	*val = cap->pixelaspect.denominator;
 641	return 0;
 642}
 643
 644static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 645{
 646	/* Actual maximum depends on the video standard in effect. */
 647	if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 648		*vp = 480;
 649	} else {
 650		*vp = 576;
 651	}
 652	return 0;
 653}
 654
 655static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 656{
 657	/* Actual minimum depends on device digitizer type. */
 658	if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 659		*vp = 75;
 660	} else {
 661		*vp = 17;
 662	}
 663	return 0;
 664}
 665
 666static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 667{
 668	*vp = cptr->hdw->input_val;
 669	return 0;
 670}
 671
 672static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 673{
 674	return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 675}
 676
 677static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 678{
 679	return pvr2_hdw_set_input(cptr->hdw,v);
 680}
 681
 682static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 683{
 684	return cptr->hdw->input_dirty != 0;
 685}
 686
 687static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 688{
 689	cptr->hdw->input_dirty = 0;
 690}
 691
 692
 693static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 694{
 695	unsigned long fv;
 696	struct pvr2_hdw *hdw = cptr->hdw;
 697	if (hdw->tuner_signal_stale) {
 698		pvr2_hdw_status_poll(hdw);
 699	}
 700	fv = hdw->tuner_signal_info.rangehigh;
 701	if (!fv) {
 702		/* Safety fallback */
 703		*vp = TV_MAX_FREQ;
 704		return 0;
 705	}
 706	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 707		fv = (fv * 125) / 2;
 708	} else {
 709		fv = fv * 62500;
 710	}
 711	*vp = fv;
 712	return 0;
 713}
 714
 715static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 716{
 717	unsigned long fv;
 718	struct pvr2_hdw *hdw = cptr->hdw;
 719	if (hdw->tuner_signal_stale) {
 720		pvr2_hdw_status_poll(hdw);
 721	}
 722	fv = hdw->tuner_signal_info.rangelow;
 723	if (!fv) {
 724		/* Safety fallback */
 725		*vp = TV_MIN_FREQ;
 726		return 0;
 727	}
 728	if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 729		fv = (fv * 125) / 2;
 730	} else {
 731		fv = fv * 62500;
 732	}
 733	*vp = fv;
 734	return 0;
 735}
 736
 737static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 738{
 739	return cptr->hdw->enc_stale != 0;
 740}
 741
 742static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 743{
 744	cptr->hdw->enc_stale = 0;
 745	cptr->hdw->enc_unsafe_stale = 0;
 746}
 747
 748static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 749{
 750	int ret;
 751	struct v4l2_ext_controls cs;
 752	struct v4l2_ext_control c1;
 753	memset(&cs,0,sizeof(cs));
 754	memset(&c1,0,sizeof(c1));
 755	cs.controls = &c1;
 756	cs.count = 1;
 757	c1.id = cptr->info->v4l_id;
 758	ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 759				VIDIOC_G_EXT_CTRLS);
 760	if (ret) return ret;
 761	*vp = c1.value;
 762	return 0;
 763}
 764
 765static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 766{
 767	int ret;
 768	struct pvr2_hdw *hdw = cptr->hdw;
 769	struct v4l2_ext_controls cs;
 770	struct v4l2_ext_control c1;
 771	memset(&cs,0,sizeof(cs));
 772	memset(&c1,0,sizeof(c1));
 773	cs.controls = &c1;
 774	cs.count = 1;
 775	c1.id = cptr->info->v4l_id;
 776	c1.value = v;
 777	ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 778				hdw->state_encoder_run, &cs,
 779				VIDIOC_S_EXT_CTRLS);
 780	if (ret == -EBUSY) {
 781		/* Oops.  cx2341x is telling us it's not safe to change
 782		   this control while we're capturing.  Make a note of this
 783		   fact so that the pipeline will be stopped the next time
 784		   controls are committed.  Then go on ahead and store this
 785		   change anyway. */
 786		ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 787					0, &cs,
 788					VIDIOC_S_EXT_CTRLS);
 789		if (!ret) hdw->enc_unsafe_stale = !0;
 790	}
 791	if (ret) return ret;
 792	hdw->enc_stale = !0;
 793	return 0;
 794}
 795
 796static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 797{
 798	struct v4l2_queryctrl qctrl;
 799	struct pvr2_ctl_info *info;
 800	qctrl.id = cptr->info->v4l_id;
 801	cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 802	/* Strip out the const so we can adjust a function pointer.  It's
 803	   OK to do this here because we know this is a dynamically created
 804	   control, so the underlying storage for the info pointer is (a)
 805	   private to us, and (b) not in read-only storage.  Either we do
 806	   this or we significantly complicate the underlying control
 807	   implementation. */
 808	info = (struct pvr2_ctl_info *)(cptr->info);
 809	if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 810		if (info->set_value) {
 811			info->set_value = NULL;
 812		}
 813	} else {
 814		if (!(info->set_value)) {
 815			info->set_value = ctrl_cx2341x_set;
 816		}
 817	}
 818	return qctrl.flags;
 819}
 820
 821static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 822{
 823	*vp = cptr->hdw->state_pipeline_req;
 824	return 0;
 825}
 826
 827static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 828{
 829	*vp = cptr->hdw->master_state;
 830	return 0;
 831}
 832
 833static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 834{
 835	int result = pvr2_hdw_is_hsm(cptr->hdw);
 836	*vp = PVR2_CVAL_HSM_FULL;
 837	if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 838	if (result) *vp = PVR2_CVAL_HSM_HIGH;
 839	return 0;
 840}
 841
 842static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 843{
 844	*vp = cptr->hdw->std_mask_avail;
 845	return 0;
 846}
 847
 848static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 849{
 850	struct pvr2_hdw *hdw = cptr->hdw;
 851	v4l2_std_id ns;
 852	ns = hdw->std_mask_avail;
 853	ns = (ns & ~m) | (v & m);
 854	if (ns == hdw->std_mask_avail) return 0;
 855	hdw->std_mask_avail = ns;
 856	pvr2_hdw_internal_set_std_avail(hdw);
 857	pvr2_hdw_internal_find_stdenum(hdw);
 858	return 0;
 859}
 860
 861static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 862			       char *bufPtr,unsigned int bufSize,
 863			       unsigned int *len)
 864{
 865	*len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 866	return 0;
 867}
 868
 869static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 870			       const char *bufPtr,unsigned int bufSize,
 871			       int *mskp,int *valp)
 872{
 873	int ret;
 874	v4l2_std_id id;
 875	ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 876	if (ret < 0) return ret;
 877	if (mskp) *mskp = id;
 878	if (valp) *valp = id;
 879	return 0;
 880}
 881
 882static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 883{
 884	*vp = cptr->hdw->std_mask_cur;
 885	return 0;
 886}
 887
 888static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 889{
 890	struct pvr2_hdw *hdw = cptr->hdw;
 891	v4l2_std_id ns;
 892	ns = hdw->std_mask_cur;
 893	ns = (ns & ~m) | (v & m);
 894	if (ns == hdw->std_mask_cur) return 0;
 895	hdw->std_mask_cur = ns;
 896	hdw->std_dirty = !0;
 897	pvr2_hdw_internal_find_stdenum(hdw);
 898	return 0;
 899}
 900
 901static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 902{
 903	return cptr->hdw->std_dirty != 0;
 904}
 905
 906static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 907{
 908	cptr->hdw->std_dirty = 0;
 909}
 910
 911static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 912{
 913	struct pvr2_hdw *hdw = cptr->hdw;
 914	pvr2_hdw_status_poll(hdw);
 915	*vp = hdw->tuner_signal_info.signal;
 916	return 0;
 917}
 918
 919static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 920{
 921	int val = 0;
 922	unsigned int subchan;
 923	struct pvr2_hdw *hdw = cptr->hdw;
 924	pvr2_hdw_status_poll(hdw);
 925	subchan = hdw->tuner_signal_info.rxsubchans;
 926	if (subchan & V4L2_TUNER_SUB_MONO) {
 927		val |= (1 << V4L2_TUNER_MODE_MONO);
 928	}
 929	if (subchan & V4L2_TUNER_SUB_STEREO) {
 930		val |= (1 << V4L2_TUNER_MODE_STEREO);
 931	}
 932	if (subchan & V4L2_TUNER_SUB_LANG1) {
 933		val |= (1 << V4L2_TUNER_MODE_LANG1);
 934	}
 935	if (subchan & V4L2_TUNER_SUB_LANG2) {
 936		val |= (1 << V4L2_TUNER_MODE_LANG2);
 937	}
 938	*vp = val;
 939	return 0;
 940}
 941
 942
 943static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 944{
 945	struct pvr2_hdw *hdw = cptr->hdw;
 946	if (v < 0) return -EINVAL;
 947	if (v > hdw->std_enum_cnt) return -EINVAL;
 948	hdw->std_enum_cur = v;
 949	if (!v) return 0;
 950	v--;
 951	if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 952	hdw->std_mask_cur = hdw->std_defs[v].id;
 953	hdw->std_dirty = !0;
 954	return 0;
 955}
 956
 957
 958static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 959{
 960	*vp = cptr->hdw->std_enum_cur;
 961	return 0;
 962}
 963
 964
 965static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 966{
 967	return cptr->hdw->std_dirty != 0;
 968}
 969
 970
 971static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 972{
 973	cptr->hdw->std_dirty = 0;
 974}
 975
 976
 977#define DEFINT(vmin,vmax) \
 978	.type = pvr2_ctl_int, \
 979	.def.type_int.min_value = vmin, \
 980	.def.type_int.max_value = vmax
 981
 982#define DEFENUM(tab) \
 983	.type = pvr2_ctl_enum, \
 984	.def.type_enum.count = ARRAY_SIZE(tab), \
 985	.def.type_enum.value_names = tab
 986
 987#define DEFBOOL \
 988	.type = pvr2_ctl_bool
 989
 990#define DEFMASK(msk,tab) \
 991	.type = pvr2_ctl_bitmask, \
 992	.def.type_bitmask.valid_bits = msk, \
 993	.def.type_bitmask.bit_names = tab
 994
 995#define DEFREF(vname) \
 996	.set_value = ctrl_set_##vname, \
 997	.get_value = ctrl_get_##vname, \
 998	.is_dirty = ctrl_isdirty_##vname, \
 999	.clear_dirty = ctrl_cleardirty_##vname
1000
1001
1002#define VCREATE_FUNCS(vname) \
1003static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1004{*vp = cptr->hdw->vname##_val; return 0;} \
1005static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1006{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1007static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1008{return cptr->hdw->vname##_dirty != 0;} \
1009static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1010{cptr->hdw->vname##_dirty = 0;}
1011
1012VCREATE_FUNCS(brightness)
1013VCREATE_FUNCS(contrast)
1014VCREATE_FUNCS(saturation)
1015VCREATE_FUNCS(hue)
1016VCREATE_FUNCS(volume)
1017VCREATE_FUNCS(balance)
1018VCREATE_FUNCS(bass)
1019VCREATE_FUNCS(treble)
1020VCREATE_FUNCS(mute)
1021VCREATE_FUNCS(cropl)
1022VCREATE_FUNCS(cropt)
1023VCREATE_FUNCS(cropw)
1024VCREATE_FUNCS(croph)
1025VCREATE_FUNCS(audiomode)
1026VCREATE_FUNCS(res_hor)
1027VCREATE_FUNCS(res_ver)
1028VCREATE_FUNCS(srate)
1029
1030/* Table definition of all controls which can be manipulated */
1031static const struct pvr2_ctl_info control_defs[] = {
1032	{
1033		.v4l_id = V4L2_CID_BRIGHTNESS,
1034		.desc = "Brightness",
1035		.name = "brightness",
1036		.default_value = 128,
1037		DEFREF(brightness),
1038		DEFINT(0,255),
1039	},{
1040		.v4l_id = V4L2_CID_CONTRAST,
1041		.desc = "Contrast",
1042		.name = "contrast",
1043		.default_value = 68,
1044		DEFREF(contrast),
1045		DEFINT(0,127),
1046	},{
1047		.v4l_id = V4L2_CID_SATURATION,
1048		.desc = "Saturation",
1049		.name = "saturation",
1050		.default_value = 64,
1051		DEFREF(saturation),
1052		DEFINT(0,127),
1053	},{
1054		.v4l_id = V4L2_CID_HUE,
1055		.desc = "Hue",
1056		.name = "hue",
1057		.default_value = 0,
1058		DEFREF(hue),
1059		DEFINT(-128,127),
1060	},{
1061		.v4l_id = V4L2_CID_AUDIO_VOLUME,
1062		.desc = "Volume",
1063		.name = "volume",
1064		.default_value = 62000,
1065		DEFREF(volume),
1066		DEFINT(0,65535),
1067	},{
1068		.v4l_id = V4L2_CID_AUDIO_BALANCE,
1069		.desc = "Balance",
1070		.name = "balance",
1071		.default_value = 0,
1072		DEFREF(balance),
1073		DEFINT(-32768,32767),
1074	},{
1075		.v4l_id = V4L2_CID_AUDIO_BASS,
1076		.desc = "Bass",
1077		.name = "bass",
1078		.default_value = 0,
1079		DEFREF(bass),
1080		DEFINT(-32768,32767),
1081	},{
1082		.v4l_id = V4L2_CID_AUDIO_TREBLE,
1083		.desc = "Treble",
1084		.name = "treble",
1085		.default_value = 0,
1086		DEFREF(treble),
1087		DEFINT(-32768,32767),
1088	},{
1089		.v4l_id = V4L2_CID_AUDIO_MUTE,
1090		.desc = "Mute",
1091		.name = "mute",
1092		.default_value = 0,
1093		DEFREF(mute),
1094		DEFBOOL,
1095	}, {
1096		.desc = "Capture crop left margin",
1097		.name = "crop_left",
1098		.internal_id = PVR2_CID_CROPL,
1099		.default_value = 0,
1100		DEFREF(cropl),
1101		DEFINT(-129, 340),
1102		.get_min_value = ctrl_cropl_min_get,
1103		.get_max_value = ctrl_cropl_max_get,
1104		.get_def_value = ctrl_get_cropcapdl,
1105	}, {
1106		.desc = "Capture crop top margin",
1107		.name = "crop_top",
1108		.internal_id = PVR2_CID_CROPT,
1109		.default_value = 0,
1110		DEFREF(cropt),
1111		DEFINT(-35, 544),
1112		.get_min_value = ctrl_cropt_min_get,
1113		.get_max_value = ctrl_cropt_max_get,
1114		.get_def_value = ctrl_get_cropcapdt,
1115	}, {
1116		.desc = "Capture crop width",
1117		.name = "crop_width",
1118		.internal_id = PVR2_CID_CROPW,
1119		.default_value = 720,
1120		DEFREF(cropw),
1121		DEFINT(0, 864),
1122		.get_max_value = ctrl_cropw_max_get,
1123		.get_def_value = ctrl_get_cropcapdw,
1124	}, {
1125		.desc = "Capture crop height",
1126		.name = "crop_height",
1127		.internal_id = PVR2_CID_CROPH,
1128		.default_value = 480,
1129		DEFREF(croph),
1130		DEFINT(0, 576),
1131		.get_max_value = ctrl_croph_max_get,
1132		.get_def_value = ctrl_get_cropcapdh,
1133	}, {
1134		.desc = "Capture capability pixel aspect numerator",
1135		.name = "cropcap_pixel_numerator",
1136		.internal_id = PVR2_CID_CROPCAPPAN,
1137		.get_value = ctrl_get_cropcappan,
1138	}, {
1139		.desc = "Capture capability pixel aspect denominator",
1140		.name = "cropcap_pixel_denominator",
1141		.internal_id = PVR2_CID_CROPCAPPAD,
1142		.get_value = ctrl_get_cropcappad,
1143	}, {
1144		.desc = "Capture capability bounds top",
1145		.name = "cropcap_bounds_top",
1146		.internal_id = PVR2_CID_CROPCAPBT,
1147		.get_value = ctrl_get_cropcapbt,
1148	}, {
1149		.desc = "Capture capability bounds left",
1150		.name = "cropcap_bounds_left",
1151		.internal_id = PVR2_CID_CROPCAPBL,
1152		.get_value = ctrl_get_cropcapbl,
1153	}, {
1154		.desc = "Capture capability bounds width",
1155		.name = "cropcap_bounds_width",
1156		.internal_id = PVR2_CID_CROPCAPBW,
1157		.get_value = ctrl_get_cropcapbw,
1158	}, {
1159		.desc = "Capture capability bounds height",
1160		.name = "cropcap_bounds_height",
1161		.internal_id = PVR2_CID_CROPCAPBH,
1162		.get_value = ctrl_get_cropcapbh,
1163	},{
1164		.desc = "Video Source",
1165		.name = "input",
1166		.internal_id = PVR2_CID_INPUT,
1167		.default_value = PVR2_CVAL_INPUT_TV,
1168		.check_value = ctrl_check_input,
1169		DEFREF(input),
1170		DEFENUM(control_values_input),
1171	},{
1172		.desc = "Audio Mode",
1173		.name = "audio_mode",
1174		.internal_id = PVR2_CID_AUDIOMODE,
1175		.default_value = V4L2_TUNER_MODE_STEREO,
1176		DEFREF(audiomode),
1177		DEFENUM(control_values_audiomode),
1178	},{
1179		.desc = "Horizontal capture resolution",
1180		.name = "resolution_hor",
1181		.internal_id = PVR2_CID_HRES,
1182		.default_value = 720,
1183		DEFREF(res_hor),
1184		DEFINT(19,720),
1185	},{
1186		.desc = "Vertical capture resolution",
1187		.name = "resolution_ver",
1188		.internal_id = PVR2_CID_VRES,
1189		.default_value = 480,
1190		DEFREF(res_ver),
1191		DEFINT(17,576),
1192		/* Hook in check for video standard and adjust maximum
1193		   depending on the standard. */
1194		.get_max_value = ctrl_vres_max_get,
1195		.get_min_value = ctrl_vres_min_get,
1196	},{
1197		.v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1198		.default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1199		.desc = "Audio Sampling Frequency",
1200		.name = "srate",
1201		DEFREF(srate),
1202		DEFENUM(control_values_srate),
1203	},{
1204		.desc = "Tuner Frequency (Hz)",
1205		.name = "frequency",
1206		.internal_id = PVR2_CID_FREQUENCY,
1207		.default_value = 0,
1208		.set_value = ctrl_freq_set,
1209		.get_value = ctrl_freq_get,
1210		.is_dirty = ctrl_freq_is_dirty,
1211		.clear_dirty = ctrl_freq_clear_dirty,
1212		DEFINT(0,0),
1213		/* Hook in check for input value (tv/radio) and adjust
1214		   max/min values accordingly */
1215		.get_max_value = ctrl_freq_max_get,
1216		.get_min_value = ctrl_freq_min_get,
1217	},{
1218		.desc = "Channel",
1219		.name = "channel",
1220		.set_value = ctrl_channel_set,
1221		.get_value = ctrl_channel_get,
1222		DEFINT(0,FREQTABLE_SIZE),
1223	},{
1224		.desc = "Channel Program Frequency",
1225		.name = "freq_table_value",
1226		.set_value = ctrl_channelfreq_set,
1227		.get_value = ctrl_channelfreq_get,
1228		DEFINT(0,0),
1229		/* Hook in check for input value (tv/radio) and adjust
1230		   max/min values accordingly */
1231		.get_max_value = ctrl_freq_max_get,
1232		.get_min_value = ctrl_freq_min_get,
1233	},{
1234		.desc = "Channel Program ID",
1235		.name = "freq_table_channel",
1236		.set_value = ctrl_channelprog_set,
1237		.get_value = ctrl_channelprog_get,
1238		DEFINT(0,FREQTABLE_SIZE),
1239	},{
1240		.desc = "Streaming Enabled",
1241		.name = "streaming_enabled",
1242		.get_value = ctrl_streamingenabled_get,
1243		DEFBOOL,
1244	},{
1245		.desc = "USB Speed",
1246		.name = "usb_speed",
1247		.get_value = ctrl_hsm_get,
1248		DEFENUM(control_values_hsm),
1249	},{
1250		.desc = "Master State",
1251		.name = "master_state",
1252		.get_value = ctrl_masterstate_get,
1253		DEFENUM(pvr2_state_names),
1254	},{
1255		.desc = "Signal Present",
1256		.name = "signal_present",
1257		.get_value = ctrl_signal_get,
1258		DEFINT(0,65535),
1259	},{
1260		.desc = "Audio Modes Present",
1261		.name = "audio_modes_present",
1262		.get_value = ctrl_audio_modes_present_get,
1263		/* For this type we "borrow" the V4L2_TUNER_MODE enum from
1264		   v4l.  Nothing outside of this module cares about this,
1265		   but I reuse it in order to also reuse the
1266		   control_values_audiomode string table. */
1267		DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1268			 (1 << V4L2_TUNER_MODE_STEREO)|
1269			 (1 << V4L2_TUNER_MODE_LANG1)|
1270			 (1 << V4L2_TUNER_MODE_LANG2)),
1271			control_values_audiomode),
1272	},{
1273		.desc = "Video Standards Available Mask",
1274		.name = "video_standard_mask_available",
1275		.internal_id = PVR2_CID_STDAVAIL,
1276		.skip_init = !0,
1277		.get_value = ctrl_stdavail_get,
1278		.set_value = ctrl_stdavail_set,
1279		.val_to_sym = ctrl_std_val_to_sym,
1280		.sym_to_val = ctrl_std_sym_to_val,
1281		.type = pvr2_ctl_bitmask,
1282	},{
1283		.desc = "Video Standards In Use Mask",
1284		.name = "video_standard_mask_active",
1285		.internal_id = PVR2_CID_STDCUR,
1286		.skip_init = !0,
1287		.get_value = ctrl_stdcur_get,
1288		.set_value = ctrl_stdcur_set,
1289		.is_dirty = ctrl_stdcur_is_dirty,
1290		.clear_dirty = ctrl_stdcur_clear_dirty,
1291		.val_to_sym = ctrl_std_val_to_sym,
1292		.sym_to_val = ctrl_std_sym_to_val,
1293		.type = pvr2_ctl_bitmask,
1294	},{
1295		.desc = "Video Standard Name",
1296		.name = "video_standard",
1297		.internal_id = PVR2_CID_STDENUM,
1298		.skip_init = !0,
1299		.get_value = ctrl_stdenumcur_get,
1300		.set_value = ctrl_stdenumcur_set,
1301		.is_dirty = ctrl_stdenumcur_is_dirty,
1302		.clear_dirty = ctrl_stdenumcur_clear_dirty,
1303		.type = pvr2_ctl_enum,
1304	}
1305};
1306
1307#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1308
1309
1310const char *pvr2_config_get_name(enum pvr2_config cfg)
1311{
1312	switch (cfg) {
1313	case pvr2_config_empty: return "empty";
1314	case pvr2_config_mpeg: return "mpeg";
1315	case pvr2_config_vbi: return "vbi";
1316	case pvr2_config_pcm: return "pcm";
1317	case pvr2_config_rawvideo: return "raw video";
1318	}
1319	return "<unknown>";
1320}
1321
1322
1323struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1324{
1325	return hdw->usb_dev;
1326}
1327
1328
1329unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1330{
1331	return hdw->serial_number;
1332}
1333
1334
1335const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1336{
1337	return hdw->bus_info;
1338}
1339
1340
1341const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1342{
1343	return hdw->identifier;
1344}
1345
1346
1347unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1348{
1349	return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1350}
1351
1352/* Set the currently tuned frequency and account for all possible
1353   driver-core side effects of this action. */
1354static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1355{
1356	if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1357		if (hdw->freqSelector) {
1358			/* Swing over to radio frequency selection */
1359			hdw->freqSelector = 0;
1360			hdw->freqDirty = !0;
1361		}
1362		if (hdw->freqValRadio != val) {
1363			hdw->freqValRadio = val;
1364			hdw->freqSlotRadio = 0;
1365			hdw->freqDirty = !0;
1366		}
1367	} else {
1368		if (!(hdw->freqSelector)) {
1369			/* Swing over to television frequency selection */
1370			hdw->freqSelector = 1;
1371			hdw->freqDirty = !0;
1372		}
1373		if (hdw->freqValTelevision != val) {
1374			hdw->freqValTelevision = val;
1375			hdw->freqSlotTelevision = 0;
1376			hdw->freqDirty = !0;
1377		}
1378	}
1379}
1380
1381int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1382{
1383	return hdw->unit_number;
1384}
1385
1386
1387/* Attempt to locate one of the given set of files.  Messages are logged
1388   appropriate to what has been found.  The return value will be 0 or
1389   greater on success (it will be the index of the file name found) and
1390   fw_entry will be filled in.  Otherwise a negative error is returned on
1391   failure.  If the return value is -ENOENT then no viable firmware file
1392   could be located. */
1393static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1394				const struct firmware **fw_entry,
1395				const char *fwtypename,
1396				unsigned int fwcount,
1397				const char *fwnames[])
1398{
1399	unsigned int idx;
1400	int ret = -EINVAL;
1401	for (idx = 0; idx < fwcount; idx++) {
1402		ret = request_firmware(fw_entry,
1403				       fwnames[idx],
1404				       &hdw->usb_dev->dev);
1405		if (!ret) {
1406			trace_firmware("Located %s firmware: %s;"
1407				       " uploading...",
1408				       fwtypename,
1409				       fwnames[idx]);
1410			return idx;
1411		}
1412		if (ret == -ENOENT) continue;
1413		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414			   "request_firmware fatal error with code=%d",ret);
1415		return ret;
1416	}
1417	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418		   "***WARNING***"
1419		   " Device %s firmware"
1420		   " seems to be missing.",
1421		   fwtypename);
1422	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1423		   "Did you install the pvrusb2 firmware files"
1424		   " in their proper location?");
1425	if (fwcount == 1) {
1426		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427			   "request_firmware unable to locate %s file %s",
1428			   fwtypename,fwnames[0]);
1429	} else {
1430		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1431			   "request_firmware unable to locate"
1432			   " one of the following %s files:",
1433			   fwtypename);
1434		for (idx = 0; idx < fwcount; idx++) {
1435			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1436				   "request_firmware: Failed to find %s",
1437				   fwnames[idx]);
1438		}
1439	}
1440	return ret;
1441}
1442
1443
1444/*
1445 * pvr2_upload_firmware1().
1446 *
1447 * Send the 8051 firmware to the device.  After the upload, arrange for
1448 * device to re-enumerate.
1449 *
1450 * NOTE : the pointer to the firmware data given by request_firmware()
1451 * is not suitable for an usb transaction.
1452 *
1453 */
1454static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1455{
1456	const struct firmware *fw_entry = NULL;
1457	void  *fw_ptr;
1458	unsigned int pipe;
1459	unsigned int fwsize;
1460	int ret;
1461	u16 address;
1462
1463	if (!hdw->hdw_desc->fx2_firmware.cnt) {
1464		hdw->fw1_state = FW1_STATE_OK;
1465		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1466			   "Connected device type defines"
1467			   " no firmware to upload; ignoring firmware");
1468		return -ENOTTY;
1469	}
1470
1471	hdw->fw1_state = FW1_STATE_FAILED; // default result
1472
1473	trace_firmware("pvr2_upload_firmware1");
1474
1475	ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1476				   hdw->hdw_desc->fx2_firmware.cnt,
1477				   hdw->hdw_desc->fx2_firmware.lst);
1478	if (ret < 0) {
1479		if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1480		return ret;
1481	}
1482
1483	usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1484
1485	pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1486	fwsize = fw_entry->size;
1487
1488	if ((fwsize != 0x2000) &&
1489	    (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1490		if (hdw->hdw_desc->flag_fx2_16kb) {
1491			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1492				   "Wrong fx2 firmware size"
1493				   " (expected 8192 or 16384, got %u)",
1494				   fwsize);
1495		} else {
1496			pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1497				   "Wrong fx2 firmware size"
1498				   " (expected 8192, got %u)",
1499				   fwsize);
1500		}
1501		release_firmware(fw_entry);
1502		return -ENOMEM;
1503	}
1504
1505	fw_ptr = kmalloc(0x800, GFP_KERNEL);
1506	if (fw_ptr == NULL){
1507		release_firmware(fw_entry);
1508		return -ENOMEM;
1509	}
1510
1511	/* We have to hold the CPU during firmware upload. */
1512	pvr2_hdw_cpureset_assert(hdw,1);
1513
1514	/* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1515	   chunk. */
1516
1517	ret = 0;
1518	for (address = 0; address < fwsize; address += 0x800) {
1519		memcpy(fw_ptr, fw_entry->data + address, 0x800);
1520		ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1521				       0, fw_ptr, 0x800, HZ);
1522	}
1523
1524	trace_firmware("Upload done, releasing device's CPU");
1525
1526	/* Now release the CPU.  It will disconnect and reconnect later. */
1527	pvr2_hdw_cpureset_assert(hdw,0);
1528
1529	kfree(fw_ptr);
1530	release_firmware(fw_entry);
1531
1532	trace_firmware("Upload done (%d bytes sent)",ret);
1533
1534	/* We should have written fwsize bytes */
1535	if (ret == fwsize) {
1536		hdw->fw1_state = FW1_STATE_RELOAD;
1537		return 0;
1538	}
1539
1540	return -EIO;
1541}
1542
1543
1544/*
1545 * pvr2_upload_firmware2()
1546 *
1547 * This uploads encoder firmware on endpoint 2.
1548 *
1549 */
1550
1551int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1552{
1553	const struct firmware *fw_entry = NULL;
1554	void  *fw_ptr;
1555	unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1556	int actual_length;
1557	int ret = 0;
1558	int fwidx;
1559	static const char *fw_files[] = {
1560		CX2341X_FIRM_ENC_FILENAME,
1561	};
1562
1563	if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1564		return 0;
1565	}
1566
1567	trace_firmware("pvr2_upload_firmware2");
1568
1569	ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1570				   ARRAY_SIZE(fw_files), fw_files);
1571	if (ret < 0) return ret;
1572	fwidx = ret;
1573	ret = 0;
1574	/* Since we're about to completely reinitialize the encoder,
1575	   invalidate our cached copy of its configuration state.  Next
1576	   time we configure the encoder, then we'll fully configure it. */
1577	hdw->enc_cur_valid = 0;
1578
1579	/* Encoder is about to be reset so note that as far as we're
1580	   concerned now, the encoder has never been run. */
1581	del_timer_sync(&hdw->encoder_run_timer);
1582	if (hdw->state_encoder_runok) {
1583		hdw->state_encoder_runok = 0;
1584		trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1585	}
1586
1587	/* First prepare firmware loading */
1588	ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1589	ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1590	ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1591	ret |= pvr2_hdw_cmd_deep_reset(hdw);
1592	ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1593	ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1594	ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1595	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1596	ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1597	ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1598	ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1599	ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1600	ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1601	ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1602	ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1603	ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1604	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1605	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1606
1607	if (ret) {
1608		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1609			   "firmware2 upload prep failed, ret=%d",ret);
1610		release_firmware(fw_entry);
1611		goto done;
1612	}
1613
1614	/* Now send firmware */
1615
1616	fw_len = fw_entry->size;
1617
1618	if (fw_len % sizeof(u32)) {
1619		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1620			   "size of %s firmware"
1621			   " must be a multiple of %zu bytes",
1622			   fw_files[fwidx],sizeof(u32));
1623		release_firmware(fw_entry);
1624		ret = -EINVAL;
1625		goto done;
1626	}
1627
1628	fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1629	if (fw_ptr == NULL){
1630		release_firmware(fw_entry);
1631		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1632			   "failed to allocate memory for firmware2 upload");
1633		ret = -ENOMEM;
1634		goto done;
1635	}
1636
1637	pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1638
1639	fw_done = 0;
1640	for (fw_done = 0; fw_done < fw_len;) {
1641		bcnt = fw_len - fw_done;
1642		if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1643		memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1644		/* Usbsnoop log shows that we must swap bytes... */
1645		/* Some background info: The data being swapped here is a
1646		   firmware image destined for the mpeg encoder chip that
1647		   lives at the other end of a USB endpoint.  The encoder
1648		   chip always talks in 32 bit chunks and its storage is
1649		   organized into 32 bit words.  However from the file
1650		   system to the encoder chip everything is purely a byte
1651		   stream.  The firmware file's contents are always 32 bit
1652		   swapped from what the encoder expects.  Thus the need
1653		   always exists to swap the bytes regardless of the endian
1654		   type of the host processor and therefore swab32() makes
1655		   the most sense. */
1656		for (icnt = 0; icnt < bcnt/4 ; icnt++)
1657			((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1658
1659		ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1660				    &actual_length, HZ);
1661		ret |= (actual_length != bcnt);
1662		if (ret) break;
1663		fw_done += bcnt;
1664	}
1665
1666	trace_firmware("upload of %s : %i / %i ",
1667		       fw_files[fwidx],fw_done,fw_len);
1668
1669	kfree(fw_ptr);
1670	release_firmware(fw_entry);
1671
1672	if (ret) {
1673		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1674			   "firmware2 upload transfer failure");
1675		goto done;
1676	}
1677
1678	/* Finish upload */
1679
1680	ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1681	ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1682	ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1683
1684	if (ret) {
1685		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1686			   "firmware2 upload post-proc failure");
1687	}
1688
1689 done:
1690	if (hdw->hdw_desc->signal_routing_scheme ==
1691	    PVR2_ROUTING_SCHEME_GOTVIEW) {
1692		/* Ensure that GPIO 11 is set to output for GOTVIEW
1693		   hardware. */
1694		pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1695	}
1696	return ret;
1697}
1698
1699
1700static const char *pvr2_get_state_name(unsigned int st)
1701{
1702	if (st < ARRAY_SIZE(pvr2_state_names)) {
1703		return pvr2_state_names[st];
1704	}
1705	return "???";
1706}
1707
1708static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1709{
1710	/* Even though we really only care about the video decoder chip at
1711	   this point, we'll broadcast stream on/off to all sub-devices
1712	   anyway, just in case somebody else wants to hear the
1713	   command... */
1714	pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1715		   (enablefl ? "on" : "off"));
1716	v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1717	v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1718	if (hdw->decoder_client_id) {
1719		/* We get here if the encoder has been noticed.  Otherwise
1720		   we'll issue a warning to the user (which should
1721		   normally never happen). */
1722		return 0;
1723	}
1724	if (!hdw->flag_decoder_missed) {
1725		pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1726			   "WARNING: No decoder present");
1727		hdw->flag_decoder_missed = !0;
1728		trace_stbit("flag_decoder_missed",
1729			    hdw->flag_decoder_missed);
1730	}
1731	return -EIO;
1732}
1733
1734
1735int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1736{
1737	return hdw->master_state;
1738}
1739
1740
1741static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1742{
1743	if (!hdw->flag_tripped) return 0;
1744	hdw->flag_tripped = 0;
1745	pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1746		   "Clearing driver error statuss");
1747	return !0;
1748}
1749
1750
1751int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1752{
1753	int fl;
1754	LOCK_TAKE(hdw->big_lock); do {
1755		fl = pvr2_hdw_untrip_unlocked(hdw);
1756	} while (0); LOCK_GIVE(hdw->big_lock);
1757	if (fl) pvr2_hdw_state_sched(hdw);
1758	return 0;
1759}
1760
1761
1762
1763
1764int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1765{
1766	return hdw->state_pipeline_req != 0;
1767}
1768
1769
1770int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1771{
1772	int ret,st;
1773	LOCK_TAKE(hdw->big_lock); do {
1774		pvr2_hdw_untrip_unlocked(hdw);
1775		if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1776			hdw->state_pipeline_req = enable_flag != 0;
1777			pvr2_trace(PVR2_TRACE_START_STOP,
1778				   "/*--TRACE_STREAM--*/ %s",
1779				   enable_flag ? "enable" : "disable");
1780		}
1781		pvr2_hdw_state_sched(hdw);
1782	} while (0); LOCK_GIVE(hdw->big_lock);
1783	if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1784	if (enable_flag) {
1785		while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1786			if (st != PVR2_STATE_READY) return -EIO;
1787			if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1788		}
1789	}
1790	return 0;
1791}
1792
1793
1794int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1795{
1796	int fl;
1797	LOCK_TAKE(hdw->big_lock);
1798	if ((fl = (hdw->desired_stream_type != config)) != 0) {
1799		hdw->desired_stream_type = config;
1800		hdw->state_pipeline_config = 0;
1801		trace_stbit("state_pipeline_config",
1802			    hdw->state_pipeline_config);
1803		pvr2_hdw_state_sched(hdw);
1804	}
1805	LOCK_GIVE(hdw->big_lock);
1806	if (fl) return 0;
1807	return pvr2_hdw_wait(hdw,0);
1808}
1809
1810
1811static int get_default_tuner_type(struct pvr2_hdw *hdw)
1812{
1813	int unit_number = hdw->unit_number;
1814	int tp = -1;
1815	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1816		tp = tuner[unit_number];
1817	}
1818	if (tp < 0) return -EINVAL;
1819	hdw->tuner_type = tp;
1820	hdw->tuner_updated = !0;
1821	return 0;
1822}
1823
1824
1825static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1826{
1827	int unit_number = hdw->unit_number;
1828	int tp = 0;
1829	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1830		tp = video_std[unit_number];
1831		if (tp) return tp;
1832	}
1833	return 0;
1834}
1835
1836
1837static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1838{
1839	int unit_number = hdw->unit_number;
1840	int tp = 0;
1841	if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1842		tp = tolerance[unit_number];
1843	}
1844	return tp;
1845}
1846
1847
1848static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1849{
1850	/* Try a harmless request to fetch the eeprom's address over
1851	   endpoint 1.  See what happens.  Only the full FX2 image can
1852	   respond to this.  If this probe fails then likely the FX2
1853	   firmware needs be loaded. */
1854	int result;
1855	LOCK_TAKE(hdw->ctl_lock); do {
1856		hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1857		result = pvr2_send_request_e

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