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/drivers/char/mwave/3780i.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 740 lines | 486 code | 175 blank | 79 comment | 22 complexity | f2ac118f18e40cf1328562fc001dd08e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. *
  3. * 3780i.c -- helper routines for the 3780i DSP
  4. *
  5. *
  6. * Written By: Mike Sullivan IBM Corporation
  7. *
  8. * Copyright (C) 1999 IBM Corporation
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * NO WARRANTY
  21. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25. * solely responsible for determining the appropriateness of using and
  26. * distributing the Program and assumes all risks associated with its
  27. * exercise of rights under this Agreement, including but not limited to
  28. * the risks and costs of program errors, damage to or loss of data,
  29. * programs or equipment, and unavailability or interruption of operations.
  30. *
  31. * DISCLAIMER OF LIABILITY
  32. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39. *
  40. * You should have received a copy of the GNU General Public License
  41. * along with this program; if not, write to the Free Software
  42. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  43. *
  44. *
  45. * 10/23/2000 - Alpha Release
  46. * First release to the public
  47. */
  48. #include <linux/kernel.h>
  49. #include <linux/unistd.h>
  50. #include <linux/delay.h>
  51. #include <linux/ioport.h>
  52. #include <linux/init.h>
  53. #include <linux/bitops.h>
  54. #include <linux/sched.h> /* cond_resched() */
  55. #include <asm/io.h>
  56. #include <asm/uaccess.h>
  57. #include <asm/system.h>
  58. #include <asm/irq.h>
  59. #include "smapi.h"
  60. #include "mwavedd.h"
  61. #include "3780i.h"
  62. static DEFINE_SPINLOCK(dsp_lock);
  63. static void PaceMsaAccess(unsigned short usDspBaseIO)
  64. {
  65. cond_resched();
  66. udelay(100);
  67. cond_resched();
  68. }
  69. unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
  70. unsigned long ulMsaAddr)
  71. {
  72. unsigned long flags;
  73. unsigned short val;
  74. PRINTK_3(TRACE_3780I,
  75. "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
  76. usDspBaseIO, ulMsaAddr);
  77. spin_lock_irqsave(&dsp_lock, flags);
  78. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
  79. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
  80. val = InWordDsp(DSP_MsaDataDSISHigh);
  81. spin_unlock_irqrestore(&dsp_lock, flags);
  82. PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
  83. return val;
  84. }
  85. void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
  86. unsigned long ulMsaAddr, unsigned short usValue)
  87. {
  88. unsigned long flags;
  89. PRINTK_4(TRACE_3780I,
  90. "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
  91. usDspBaseIO, ulMsaAddr, usValue);
  92. spin_lock_irqsave(&dsp_lock, flags);
  93. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
  94. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
  95. OutWordDsp(DSP_MsaDataDSISHigh, usValue);
  96. spin_unlock_irqrestore(&dsp_lock, flags);
  97. }
  98. static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
  99. unsigned char ucValue)
  100. {
  101. DSP_ISA_SLAVE_CONTROL rSlaveControl;
  102. DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
  103. PRINTK_4(TRACE_3780I,
  104. "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
  105. usDspBaseIO, uIndex, ucValue);
  106. MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
  107. PRINTK_2(TRACE_3780I,
  108. "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
  109. MKBYTE(rSlaveControl));
  110. rSlaveControl_Save = rSlaveControl;
  111. rSlaveControl.ConfigMode = TRUE;
  112. PRINTK_2(TRACE_3780I,
  113. "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
  114. MKBYTE(rSlaveControl));
  115. OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
  116. OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
  117. OutByteDsp(DSP_ConfigData, ucValue);
  118. OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
  119. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
  120. }
  121. #if 0
  122. unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
  123. unsigned uIndex)
  124. {
  125. DSP_ISA_SLAVE_CONTROL rSlaveControl;
  126. DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
  127. unsigned char ucValue;
  128. PRINTK_3(TRACE_3780I,
  129. "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
  130. usDspBaseIO, uIndex);
  131. MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
  132. rSlaveControl_Save = rSlaveControl;
  133. rSlaveControl.ConfigMode = TRUE;
  134. OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
  135. OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
  136. ucValue = InByteDsp(DSP_ConfigData);
  137. OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
  138. PRINTK_2(TRACE_3780I,
  139. "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
  140. return ucValue;
  141. }
  142. #endif /* 0 */
  143. int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
  144. unsigned short *pIrqMap,
  145. unsigned short *pDmaMap)
  146. {
  147. unsigned long flags;
  148. unsigned short usDspBaseIO = pSettings->usDspBaseIO;
  149. int i;
  150. DSP_UART_CFG_1 rUartCfg1;
  151. DSP_UART_CFG_2 rUartCfg2;
  152. DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
  153. DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
  154. DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
  155. DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
  156. DSP_ISA_PROT_CFG rIsaProtCfg;
  157. DSP_POWER_MGMT_CFG rPowerMgmtCfg;
  158. DSP_HBUS_TIMER_CFG rHBusTimerCfg;
  159. DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
  160. DSP_CHIP_RESET rChipReset;
  161. DSP_CLOCK_CONTROL_1 rClockControl1;
  162. DSP_CLOCK_CONTROL_2 rClockControl2;
  163. DSP_ISA_SLAVE_CONTROL rSlaveControl;
  164. DSP_HBRIDGE_CONTROL rHBridgeControl;
  165. unsigned short ChipID = 0;
  166. unsigned short tval;
  167. PRINTK_2(TRACE_3780I,
  168. "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
  169. pSettings->bDSPEnabled);
  170. if (!pSettings->bDSPEnabled) {
  171. PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
  172. return -EIO;
  173. }
  174. PRINTK_2(TRACE_3780I,
  175. "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
  176. pSettings->bModemEnabled);
  177. if (pSettings->bModemEnabled) {
  178. rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
  179. rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
  180. rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
  181. rUartCfg1.Irq =
  182. (unsigned char) pIrqMap[pSettings->usUartIrq];
  183. switch (pSettings->usUartBaseIO) {
  184. case 0x03F8:
  185. rUartCfg1.BaseIO = 0;
  186. break;
  187. case 0x02F8:
  188. rUartCfg1.BaseIO = 1;
  189. break;
  190. case 0x03E8:
  191. rUartCfg1.BaseIO = 2;
  192. break;
  193. case 0x02E8:
  194. rUartCfg1.BaseIO = 3;
  195. break;
  196. }
  197. rUartCfg2.Enable = TRUE;
  198. }
  199. rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
  200. rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
  201. rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
  202. rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
  203. rHBridgeCfg1.AccessMode = 1;
  204. rHBridgeCfg2.Enable = TRUE;
  205. rBusmasterCfg2.Reserved = 0;
  206. rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
  207. rBusmasterCfg1.NumTransfers =
  208. (unsigned char) pSettings->usNumTransfers;
  209. rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
  210. rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
  211. rBusmasterCfg2.IsaMemCmdWidth =
  212. (unsigned char) pSettings->usIsaMemCmdWidth;
  213. rIsaProtCfg.Reserved = 0;
  214. rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
  215. rPowerMgmtCfg.Reserved = 0;
  216. rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
  217. rHBusTimerCfg.LoadValue =
  218. (unsigned char) pSettings->usHBusTimerLoadValue;
  219. rLBusTimeoutDisable.Reserved = 0;
  220. rLBusTimeoutDisable.DisableTimeout =
  221. pSettings->bDisableLBusTimeout;
  222. MKWORD(rChipReset) = ~pSettings->usChipletEnable;
  223. rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
  224. rClockControl1.N_Divisor = pSettings->usN_Divisor;
  225. rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
  226. rClockControl2.Reserved = 0;
  227. rClockControl2.PllBypass = pSettings->bPllBypass;
  228. /* Issue a soft reset to the chip */
  229. /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
  230. * soft-reset active for 10ms.
  231. */
  232. rSlaveControl.ClockControl = 0;
  233. rSlaveControl.SoftReset = TRUE;
  234. rSlaveControl.ConfigMode = FALSE;
  235. rSlaveControl.Reserved = 0;
  236. PRINTK_4(TRACE_3780I,
  237. "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
  238. usDspBaseIO, DSP_IsaSlaveControl,
  239. usDspBaseIO + DSP_IsaSlaveControl);
  240. PRINTK_2(TRACE_3780I,
  241. "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
  242. MKWORD(rSlaveControl));
  243. spin_lock_irqsave(&dsp_lock, flags);
  244. OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
  245. MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
  246. PRINTK_2(TRACE_3780I,
  247. "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
  248. for (i = 0; i < 11; i++)
  249. udelay(2000);
  250. rSlaveControl.SoftReset = FALSE;
  251. OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
  252. MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
  253. PRINTK_2(TRACE_3780I,
  254. "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
  255. /* Program our general configuration registers */
  256. WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
  257. WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
  258. WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
  259. WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
  260. WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
  261. WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
  262. WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
  263. if (pSettings->bModemEnabled) {
  264. WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
  265. WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
  266. }
  267. rHBridgeControl.EnableDspInt = FALSE;
  268. rHBridgeControl.MemAutoInc = TRUE;
  269. rHBridgeControl.IoAutoInc = FALSE;
  270. rHBridgeControl.DiagnosticMode = FALSE;
  271. PRINTK_3(TRACE_3780I,
  272. "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
  273. DSP_HBridgeControl, MKWORD(rHBridgeControl));
  274. OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
  275. spin_unlock_irqrestore(&dsp_lock, flags);
  276. WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
  277. WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
  278. WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
  279. WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
  280. ChipID = ReadMsaCfg(DSP_ChipID);
  281. PRINTK_2(TRACE_3780I,
  282. "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n",
  283. ChipID);
  284. return 0;
  285. }
  286. int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
  287. {
  288. unsigned long flags;
  289. unsigned short usDspBaseIO = pSettings->usDspBaseIO;
  290. DSP_ISA_SLAVE_CONTROL rSlaveControl;
  291. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
  292. rSlaveControl.ClockControl = 0;
  293. rSlaveControl.SoftReset = TRUE;
  294. rSlaveControl.ConfigMode = FALSE;
  295. rSlaveControl.Reserved = 0;
  296. spin_lock_irqsave(&dsp_lock, flags);
  297. OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
  298. udelay(5);
  299. rSlaveControl.ClockControl = 1;
  300. OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
  301. spin_unlock_irqrestore(&dsp_lock, flags);
  302. udelay(5);
  303. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
  304. return 0;
  305. }
  306. int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
  307. {
  308. unsigned long flags;
  309. unsigned short usDspBaseIO = pSettings->usDspBaseIO;
  310. DSP_BOOT_DOMAIN rBootDomain;
  311. DSP_HBRIDGE_CONTROL rHBridgeControl;
  312. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
  313. spin_lock_irqsave(&dsp_lock, flags);
  314. /* Mask DSP to PC interrupt */
  315. MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
  316. PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
  317. MKWORD(rHBridgeControl));
  318. rHBridgeControl.EnableDspInt = FALSE;
  319. OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
  320. spin_unlock_irqrestore(&dsp_lock, flags);
  321. /* Reset the core via the boot domain register */
  322. rBootDomain.ResetCore = TRUE;
  323. rBootDomain.Halt = TRUE;
  324. rBootDomain.NMI = TRUE;
  325. rBootDomain.Reserved = 0;
  326. PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
  327. MKWORD(rBootDomain));
  328. WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
  329. /* Reset all the chiplets and then reactivate them */
  330. WriteMsaCfg(DSP_ChipReset, 0xFFFF);
  331. udelay(5);
  332. WriteMsaCfg(DSP_ChipReset,
  333. (unsigned short) (~pSettings->usChipletEnable));
  334. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
  335. return 0;
  336. }
  337. int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
  338. {
  339. unsigned long flags;
  340. unsigned short usDspBaseIO = pSettings->usDspBaseIO;
  341. DSP_BOOT_DOMAIN rBootDomain;
  342. DSP_HBRIDGE_CONTROL rHBridgeControl;
  343. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
  344. /* Transition the core to a running state */
  345. rBootDomain.ResetCore = TRUE;
  346. rBootDomain.Halt = FALSE;
  347. rBootDomain.NMI = TRUE;
  348. rBootDomain.Reserved = 0;
  349. WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
  350. udelay(5);
  351. rBootDomain.ResetCore = FALSE;
  352. WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
  353. udelay(5);
  354. rBootDomain.NMI = FALSE;
  355. WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
  356. udelay(5);
  357. /* Enable DSP to PC interrupt */
  358. spin_lock_irqsave(&dsp_lock, flags);
  359. MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
  360. rHBridgeControl.EnableDspInt = TRUE;
  361. PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
  362. MKWORD(rHBridgeControl));
  363. OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
  364. spin_unlock_irqrestore(&dsp_lock, flags);
  365. PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n");
  366. return 0;
  367. }
  368. int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
  369. unsigned uCount, unsigned long ulDSPAddr)
  370. {
  371. unsigned long flags;
  372. unsigned short __user *pusBuffer = pvBuffer;
  373. unsigned short val;
  374. PRINTK_5(TRACE_3780I,
  375. "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
  376. usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
  377. /* Set the initial MSA address. No adjustments need to be made to data store addresses */
  378. spin_lock_irqsave(&dsp_lock, flags);
  379. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
  380. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
  381. spin_unlock_irqrestore(&dsp_lock, flags);
  382. /* Transfer the memory block */
  383. while (uCount-- != 0) {
  384. spin_lock_irqsave(&dsp_lock, flags);
  385. val = InWordDsp(DSP_MsaDataDSISHigh);
  386. spin_unlock_irqrestore(&dsp_lock, flags);
  387. if(put_user(val, pusBuffer++))
  388. return -EFAULT;
  389. PRINTK_3(TRACE_3780I,
  390. "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
  391. uCount, val);
  392. PaceMsaAccess(usDspBaseIO);
  393. }
  394. PRINTK_1(TRACE_3780I,
  395. "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n");
  396. return 0;
  397. }
  398. int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
  399. void __user *pvBuffer, unsigned uCount,
  400. unsigned long ulDSPAddr)
  401. {
  402. unsigned long flags;
  403. unsigned short __user *pusBuffer = pvBuffer;
  404. unsigned short val;
  405. PRINTK_5(TRACE_3780I,
  406. "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
  407. usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
  408. /* Set the initial MSA address. No adjustments need to be made to data store addresses */
  409. spin_lock_irqsave(&dsp_lock, flags);
  410. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
  411. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
  412. spin_unlock_irqrestore(&dsp_lock, flags);
  413. /* Transfer the memory block */
  414. while (uCount-- != 0) {
  415. spin_lock_irqsave(&dsp_lock, flags);
  416. val = InWordDsp(DSP_ReadAndClear);
  417. spin_unlock_irqrestore(&dsp_lock, flags);
  418. if(put_user(val, pusBuffer++))
  419. return -EFAULT;
  420. PRINTK_3(TRACE_3780I,
  421. "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
  422. uCount, val);
  423. PaceMsaAccess(usDspBaseIO);
  424. }
  425. PRINTK_1(TRACE_3780I,
  426. "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n");
  427. return 0;
  428. }
  429. int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
  430. unsigned uCount, unsigned long ulDSPAddr)
  431. {
  432. unsigned long flags;
  433. unsigned short __user *pusBuffer = pvBuffer;
  434. PRINTK_5(TRACE_3780I,
  435. "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
  436. usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
  437. /* Set the initial MSA address. No adjustments need to be made to data store addresses */
  438. spin_lock_irqsave(&dsp_lock, flags);
  439. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
  440. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
  441. spin_unlock_irqrestore(&dsp_lock, flags);
  442. /* Transfer the memory block */
  443. while (uCount-- != 0) {
  444. unsigned short val;
  445. if(get_user(val, pusBuffer++))
  446. return -EFAULT;
  447. spin_lock_irqsave(&dsp_lock, flags);
  448. OutWordDsp(DSP_MsaDataDSISHigh, val);
  449. spin_unlock_irqrestore(&dsp_lock, flags);
  450. PRINTK_3(TRACE_3780I,
  451. "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
  452. uCount, val);
  453. PaceMsaAccess(usDspBaseIO);
  454. }
  455. PRINTK_1(TRACE_3780I,
  456. "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n");
  457. return 0;
  458. }
  459. int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
  460. unsigned uCount, unsigned long ulDSPAddr)
  461. {
  462. unsigned long flags;
  463. unsigned short __user *pusBuffer = pvBuffer;
  464. PRINTK_5(TRACE_3780I,
  465. "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
  466. usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
  467. /*
  468. * Set the initial MSA address. To convert from an instruction store
  469. * address to an MSA address
  470. * shift the address two bits to the left and set bit 22
  471. */
  472. ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
  473. spin_lock_irqsave(&dsp_lock, flags);
  474. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
  475. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
  476. spin_unlock_irqrestore(&dsp_lock, flags);
  477. /* Transfer the memory block */
  478. while (uCount-- != 0) {
  479. unsigned short val_lo, val_hi;
  480. spin_lock_irqsave(&dsp_lock, flags);
  481. val_lo = InWordDsp(DSP_MsaDataISLow);
  482. val_hi = InWordDsp(DSP_MsaDataDSISHigh);
  483. spin_unlock_irqrestore(&dsp_lock, flags);
  484. if(put_user(val_lo, pusBuffer++))
  485. return -EFAULT;
  486. if(put_user(val_hi, pusBuffer++))
  487. return -EFAULT;
  488. PRINTK_4(TRACE_3780I,
  489. "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
  490. uCount, val_lo, val_hi);
  491. PaceMsaAccess(usDspBaseIO);
  492. }
  493. PRINTK_1(TRACE_3780I,
  494. "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n");
  495. return 0;
  496. }
  497. int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
  498. unsigned uCount, unsigned long ulDSPAddr)
  499. {
  500. unsigned long flags;
  501. unsigned short __user *pusBuffer = pvBuffer;
  502. PRINTK_5(TRACE_3780I,
  503. "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
  504. usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
  505. /*
  506. * Set the initial MSA address. To convert from an instruction store
  507. * address to an MSA address
  508. * shift the address two bits to the left and set bit 22
  509. */
  510. ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
  511. spin_lock_irqsave(&dsp_lock, flags);
  512. OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
  513. OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
  514. spin_unlock_irqrestore(&dsp_lock, flags);
  515. /* Transfer the memory block */
  516. while (uCount-- != 0) {
  517. unsigned short val_lo, val_hi;
  518. if(get_user(val_lo, pusBuffer++))
  519. return -EFAULT;
  520. if(get_user(val_hi, pusBuffer++))
  521. return -EFAULT;
  522. spin_lock_irqsave(&dsp_lock, flags);
  523. OutWordDsp(DSP_MsaDataISLow, val_lo);
  524. OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
  525. spin_unlock_irqrestore(&dsp_lock, flags);
  526. PRINTK_4(TRACE_3780I,
  527. "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
  528. uCount, val_lo, val_hi);
  529. PaceMsaAccess(usDspBaseIO);
  530. }
  531. PRINTK_1(TRACE_3780I,
  532. "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n");
  533. return 0;
  534. }
  535. int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
  536. unsigned short *pusIPCSource)
  537. {
  538. unsigned long flags;
  539. DSP_HBRIDGE_CONTROL rHBridgeControl;
  540. unsigned short temp;
  541. PRINTK_3(TRACE_3780I,
  542. "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
  543. usDspBaseIO, pusIPCSource);
  544. /*
  545. * Disable DSP to PC interrupts, read the interrupt register,
  546. * clear the pending IPC bits, and reenable DSP to PC interrupts
  547. */
  548. spin_lock_irqsave(&dsp_lock, flags);
  549. MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
  550. rHBridgeControl.EnableDspInt = FALSE;
  551. OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
  552. *pusIPCSource = InWordDsp(DSP_Interrupt);
  553. temp = (unsigned short) ~(*pusIPCSource);
  554. PRINTK_3(TRACE_3780I,
  555. "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
  556. *pusIPCSource, temp);
  557. OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
  558. rHBridgeControl.EnableDspInt = TRUE;
  559. OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
  560. spin_unlock_irqrestore(&dsp_lock, flags);
  561. PRINTK_2(TRACE_3780I,
  562. "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
  563. *pusIPCSource);
  564. return 0;
  565. }