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/drivers/staging/lirc/lirc_sir.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 1279 lines | 911 code | 175 blank | 193 comment | 116 complexity | 9b34b3c9cc42ffcc3791b4a0c772cc5e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
  3. *
  4. * lirc_sir - Device driver for use with SIR (serial infra red)
  5. * mode of IrDA on many notebooks.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. *
  22. * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
  23. * added timeout and relaxed pulse detection, removed gap bug
  24. *
  25. * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
  26. * added support for Tekram Irmate 210 (sending does not work yet,
  27. * kind of disappointing that nobody was able to implement that
  28. * before),
  29. * major clean-up
  30. *
  31. * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
  32. * added support for StrongARM SA1100 embedded microprocessor
  33. * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
  34. */
  35. #include <linux/module.h>
  36. #include <linux/sched.h>
  37. #include <linux/errno.h>
  38. #include <linux/signal.h>
  39. #include <linux/fs.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/ioport.h>
  42. #include <linux/kernel.h>
  43. #include <linux/serial_reg.h>
  44. #include <linux/time.h>
  45. #include <linux/string.h>
  46. #include <linux/types.h>
  47. #include <linux/wait.h>
  48. #include <linux/mm.h>
  49. #include <linux/delay.h>
  50. #include <linux/poll.h>
  51. #include <asm/system.h>
  52. #include <linux/io.h>
  53. #include <asm/irq.h>
  54. #include <linux/fcntl.h>
  55. #ifdef LIRC_ON_SA1100
  56. #include <asm/hardware.h>
  57. #ifdef CONFIG_SA1100_COLLIE
  58. #include <asm/arch/tc35143.h>
  59. #include <asm/ucb1200.h>
  60. #endif
  61. #endif
  62. #include <linux/timer.h>
  63. #include <media/lirc.h>
  64. #include <media/lirc_dev.h>
  65. /* SECTION: Definitions */
  66. /*** Tekram dongle ***/
  67. #ifdef LIRC_SIR_TEKRAM
  68. /* stolen from kernel source */
  69. /* definitions for Tekram dongle */
  70. #define TEKRAM_115200 0x00
  71. #define TEKRAM_57600 0x01
  72. #define TEKRAM_38400 0x02
  73. #define TEKRAM_19200 0x03
  74. #define TEKRAM_9600 0x04
  75. #define TEKRAM_2400 0x08
  76. #define TEKRAM_PW 0x10 /* Pulse select bit */
  77. /* 10bit * 1s/115200bit in milliseconds = 87ms*/
  78. #define TIME_CONST (10000000ul/115200ul)
  79. #endif
  80. #ifdef LIRC_SIR_ACTISYS_ACT200L
  81. static void init_act200(void);
  82. #elif defined(LIRC_SIR_ACTISYS_ACT220L)
  83. static void init_act220(void);
  84. #endif
  85. /*** SA1100 ***/
  86. #ifdef LIRC_ON_SA1100
  87. struct sa1100_ser2_registers {
  88. /* HSSP control register */
  89. unsigned char hscr0;
  90. /* UART registers */
  91. unsigned char utcr0;
  92. unsigned char utcr1;
  93. unsigned char utcr2;
  94. unsigned char utcr3;
  95. unsigned char utcr4;
  96. unsigned char utdr;
  97. unsigned char utsr0;
  98. unsigned char utsr1;
  99. } sr;
  100. static int irq = IRQ_Ser2ICP;
  101. #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
  102. /* pulse/space ratio of 50/50 */
  103. static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
  104. /* 1000000/freq-pulse_width */
  105. static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
  106. static unsigned int freq = 38000; /* modulation frequency */
  107. static unsigned int duty_cycle = 50; /* duty cycle of 50% */
  108. #endif
  109. #define RBUF_LEN 1024
  110. #define WBUF_LEN 1024
  111. #define LIRC_DRIVER_NAME "lirc_sir"
  112. #define PULSE '['
  113. #ifndef LIRC_SIR_TEKRAM
  114. /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
  115. #define TIME_CONST (9000000ul/115200ul)
  116. #endif
  117. /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
  118. #define SIR_TIMEOUT (HZ*5/100)
  119. #ifndef LIRC_ON_SA1100
  120. #ifndef LIRC_IRQ
  121. #define LIRC_IRQ 4
  122. #endif
  123. #ifndef LIRC_PORT
  124. /* for external dongles, default to com1 */
  125. #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
  126. defined(LIRC_SIR_ACTISYS_ACT220L) || \
  127. defined(LIRC_SIR_TEKRAM)
  128. #define LIRC_PORT 0x3f8
  129. #else
  130. /* onboard sir ports are typically com3 */
  131. #define LIRC_PORT 0x3e8
  132. #endif
  133. #endif
  134. static int io = LIRC_PORT;
  135. static int irq = LIRC_IRQ;
  136. static int threshold = 3;
  137. #endif
  138. static DEFINE_SPINLOCK(timer_lock);
  139. static struct timer_list timerlist;
  140. /* time of last signal change detected */
  141. static struct timeval last_tv = {0, 0};
  142. /* time of last UART data ready interrupt */
  143. static struct timeval last_intr_tv = {0, 0};
  144. static int last_value;
  145. static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
  146. static DEFINE_SPINLOCK(hardware_lock);
  147. static int rx_buf[RBUF_LEN];
  148. static unsigned int rx_tail, rx_head;
  149. static int debug;
  150. #define dprintk(fmt, args...) \
  151. do { \
  152. if (debug) \
  153. printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \
  154. fmt, ## args); \
  155. } while (0)
  156. /* SECTION: Prototypes */
  157. /* Communication with user-space */
  158. static unsigned int lirc_poll(struct file *file, poll_table *wait);
  159. static ssize_t lirc_read(struct file *file, char *buf, size_t count,
  160. loff_t *ppos);
  161. static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
  162. loff_t *pos);
  163. static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
  164. static void add_read_queue(int flag, unsigned long val);
  165. static int init_chrdev(void);
  166. static void drop_chrdev(void);
  167. /* Hardware */
  168. static irqreturn_t sir_interrupt(int irq, void *dev_id);
  169. static void send_space(unsigned long len);
  170. static void send_pulse(unsigned long len);
  171. static int init_hardware(void);
  172. static void drop_hardware(void);
  173. /* Initialisation */
  174. static int init_port(void);
  175. static void drop_port(void);
  176. #ifdef LIRC_ON_SA1100
  177. static void on(void)
  178. {
  179. PPSR |= PPC_TXD2;
  180. }
  181. static void off(void)
  182. {
  183. PPSR &= ~PPC_TXD2;
  184. }
  185. #else
  186. static inline unsigned int sinp(int offset)
  187. {
  188. return inb(io + offset);
  189. }
  190. static inline void soutp(int offset, int value)
  191. {
  192. outb(value, io + offset);
  193. }
  194. #endif
  195. #ifndef MAX_UDELAY_MS
  196. #define MAX_UDELAY_US 5000
  197. #else
  198. #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
  199. #endif
  200. static void safe_udelay(unsigned long usecs)
  201. {
  202. while (usecs > MAX_UDELAY_US) {
  203. udelay(MAX_UDELAY_US);
  204. usecs -= MAX_UDELAY_US;
  205. }
  206. udelay(usecs);
  207. }
  208. /* SECTION: Communication with user-space */
  209. static unsigned int lirc_poll(struct file *file, poll_table *wait)
  210. {
  211. poll_wait(file, &lirc_read_queue, wait);
  212. if (rx_head != rx_tail)
  213. return POLLIN | POLLRDNORM;
  214. return 0;
  215. }
  216. static ssize_t lirc_read(struct file *file, char *buf, size_t count,
  217. loff_t *ppos)
  218. {
  219. int n = 0;
  220. int retval = 0;
  221. DECLARE_WAITQUEUE(wait, current);
  222. if (count % sizeof(int))
  223. return -EINVAL;
  224. add_wait_queue(&lirc_read_queue, &wait);
  225. set_current_state(TASK_INTERRUPTIBLE);
  226. while (n < count) {
  227. if (rx_head != rx_tail) {
  228. if (copy_to_user((void *) buf + n,
  229. (void *) (rx_buf + rx_head),
  230. sizeof(int))) {
  231. retval = -EFAULT;
  232. break;
  233. }
  234. rx_head = (rx_head + 1) & (RBUF_LEN - 1);
  235. n += sizeof(int);
  236. } else {
  237. if (file->f_flags & O_NONBLOCK) {
  238. retval = -EAGAIN;
  239. break;
  240. }
  241. if (signal_pending(current)) {
  242. retval = -ERESTARTSYS;
  243. break;
  244. }
  245. schedule();
  246. set_current_state(TASK_INTERRUPTIBLE);
  247. }
  248. }
  249. remove_wait_queue(&lirc_read_queue, &wait);
  250. set_current_state(TASK_RUNNING);
  251. return n ? n : retval;
  252. }
  253. static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
  254. loff_t *pos)
  255. {
  256. unsigned long flags;
  257. int i, count;
  258. int *tx_buf;
  259. count = n / sizeof(int);
  260. if (n % sizeof(int) || count % 2 == 0)
  261. return -EINVAL;
  262. tx_buf = memdup_user(buf, n);
  263. if (IS_ERR(tx_buf))
  264. return PTR_ERR(tx_buf);
  265. i = 0;
  266. #ifdef LIRC_ON_SA1100
  267. /* disable receiver */
  268. Ser2UTCR3 = 0;
  269. #endif
  270. local_irq_save(flags);
  271. while (1) {
  272. if (i >= count)
  273. break;
  274. if (tx_buf[i])
  275. send_pulse(tx_buf[i]);
  276. i++;
  277. if (i >= count)
  278. break;
  279. if (tx_buf[i])
  280. send_space(tx_buf[i]);
  281. i++;
  282. }
  283. local_irq_restore(flags);
  284. #ifdef LIRC_ON_SA1100
  285. off();
  286. udelay(1000); /* wait 1ms for IR diode to recover */
  287. Ser2UTCR3 = 0;
  288. /* clear status register to prevent unwanted interrupts */
  289. Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
  290. /* enable receiver */
  291. Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
  292. #endif
  293. kfree(tx_buf);
  294. return count;
  295. }
  296. static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  297. {
  298. int retval = 0;
  299. __u32 value = 0;
  300. #ifdef LIRC_ON_SA1100
  301. if (cmd == LIRC_GET_FEATURES)
  302. value = LIRC_CAN_SEND_PULSE |
  303. LIRC_CAN_SET_SEND_DUTY_CYCLE |
  304. LIRC_CAN_SET_SEND_CARRIER |
  305. LIRC_CAN_REC_MODE2;
  306. else if (cmd == LIRC_GET_SEND_MODE)
  307. value = LIRC_MODE_PULSE;
  308. else if (cmd == LIRC_GET_REC_MODE)
  309. value = LIRC_MODE_MODE2;
  310. #else
  311. if (cmd == LIRC_GET_FEATURES)
  312. value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
  313. else if (cmd == LIRC_GET_SEND_MODE)
  314. value = LIRC_MODE_PULSE;
  315. else if (cmd == LIRC_GET_REC_MODE)
  316. value = LIRC_MODE_MODE2;
  317. #endif
  318. switch (cmd) {
  319. case LIRC_GET_FEATURES:
  320. case LIRC_GET_SEND_MODE:
  321. case LIRC_GET_REC_MODE:
  322. retval = put_user(value, (__u32 *) arg);
  323. break;
  324. case LIRC_SET_SEND_MODE:
  325. case LIRC_SET_REC_MODE:
  326. retval = get_user(value, (__u32 *) arg);
  327. break;
  328. #ifdef LIRC_ON_SA1100
  329. case LIRC_SET_SEND_DUTY_CYCLE:
  330. retval = get_user(value, (__u32 *) arg);
  331. if (retval)
  332. return retval;
  333. if (value <= 0 || value > 100)
  334. return -EINVAL;
  335. /* (value/100)*(1000000/freq) */
  336. duty_cycle = value;
  337. pulse_width = (unsigned long) duty_cycle*10000/freq;
  338. space_width = (unsigned long) 1000000L/freq-pulse_width;
  339. if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
  340. pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
  341. if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
  342. space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
  343. break;
  344. case LIRC_SET_SEND_CARRIER:
  345. retval = get_user(value, (__u32 *) arg);
  346. if (retval)
  347. return retval;
  348. if (value > 500000 || value < 20000)
  349. return -EINVAL;
  350. freq = value;
  351. pulse_width = (unsigned long) duty_cycle*10000/freq;
  352. space_width = (unsigned long) 1000000L/freq-pulse_width;
  353. if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
  354. pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
  355. if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
  356. space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
  357. break;
  358. #endif
  359. default:
  360. retval = -ENOIOCTLCMD;
  361. }
  362. if (retval)
  363. return retval;
  364. if (cmd == LIRC_SET_REC_MODE) {
  365. if (value != LIRC_MODE_MODE2)
  366. retval = -ENOSYS;
  367. } else if (cmd == LIRC_SET_SEND_MODE) {
  368. if (value != LIRC_MODE_PULSE)
  369. retval = -ENOSYS;
  370. }
  371. return retval;
  372. }
  373. static void add_read_queue(int flag, unsigned long val)
  374. {
  375. unsigned int new_rx_tail;
  376. int newval;
  377. dprintk("add flag %d with val %lu\n", flag, val);
  378. newval = val & PULSE_MASK;
  379. /*
  380. * statistically, pulses are ~TIME_CONST/2 too long. we could
  381. * maybe make this more exact, but this is good enough
  382. */
  383. if (flag) {
  384. /* pulse */
  385. if (newval > TIME_CONST/2)
  386. newval -= TIME_CONST/2;
  387. else /* should not ever happen */
  388. newval = 1;
  389. newval |= PULSE_BIT;
  390. } else {
  391. newval += TIME_CONST/2;
  392. }
  393. new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
  394. if (new_rx_tail == rx_head) {
  395. dprintk("Buffer overrun.\n");
  396. return;
  397. }
  398. rx_buf[rx_tail] = newval;
  399. rx_tail = new_rx_tail;
  400. wake_up_interruptible(&lirc_read_queue);
  401. }
  402. static const struct file_operations lirc_fops = {
  403. .owner = THIS_MODULE,
  404. .read = lirc_read,
  405. .write = lirc_write,
  406. .poll = lirc_poll,
  407. .unlocked_ioctl = lirc_ioctl,
  408. #ifdef CONFIG_COMPAT
  409. .compat_ioctl = lirc_ioctl,
  410. #endif
  411. .open = lirc_dev_fop_open,
  412. .release = lirc_dev_fop_close,
  413. .llseek = no_llseek,
  414. };
  415. static int set_use_inc(void *data)
  416. {
  417. return 0;
  418. }
  419. static void set_use_dec(void *data)
  420. {
  421. }
  422. static struct lirc_driver driver = {
  423. .name = LIRC_DRIVER_NAME,
  424. .minor = -1,
  425. .code_length = 1,
  426. .sample_rate = 0,
  427. .data = NULL,
  428. .add_to_buf = NULL,
  429. .set_use_inc = set_use_inc,
  430. .set_use_dec = set_use_dec,
  431. .fops = &lirc_fops,
  432. .dev = NULL,
  433. .owner = THIS_MODULE,
  434. };
  435. static int init_chrdev(void)
  436. {
  437. driver.minor = lirc_register_driver(&driver);
  438. if (driver.minor < 0) {
  439. printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n");
  440. return -EIO;
  441. }
  442. return 0;
  443. }
  444. static void drop_chrdev(void)
  445. {
  446. lirc_unregister_driver(driver.minor);
  447. }
  448. /* SECTION: Hardware */
  449. static long delta(struct timeval *tv1, struct timeval *tv2)
  450. {
  451. unsigned long deltv;
  452. deltv = tv2->tv_sec - tv1->tv_sec;
  453. if (deltv > 15)
  454. deltv = 0xFFFFFF;
  455. else
  456. deltv = deltv*1000000 +
  457. tv2->tv_usec -
  458. tv1->tv_usec;
  459. return deltv;
  460. }
  461. static void sir_timeout(unsigned long data)
  462. {
  463. /*
  464. * if last received signal was a pulse, but receiving stopped
  465. * within the 9 bit frame, we need to finish this pulse and
  466. * simulate a signal change to from pulse to space. Otherwise
  467. * upper layers will receive two sequences next time.
  468. */
  469. unsigned long flags;
  470. unsigned long pulse_end;
  471. /* avoid interference with interrupt */
  472. spin_lock_irqsave(&timer_lock, flags);
  473. if (last_value) {
  474. #ifndef LIRC_ON_SA1100
  475. /* clear unread bits in UART and restart */
  476. outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
  477. #endif
  478. /* determine 'virtual' pulse end: */
  479. pulse_end = delta(&last_tv, &last_intr_tv);
  480. dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
  481. add_read_queue(last_value, pulse_end);
  482. last_value = 0;
  483. last_tv = last_intr_tv;
  484. }
  485. spin_unlock_irqrestore(&timer_lock, flags);
  486. }
  487. static irqreturn_t sir_interrupt(int irq, void *dev_id)
  488. {
  489. unsigned char data;
  490. struct timeval curr_tv;
  491. static unsigned long deltv;
  492. #ifdef LIRC_ON_SA1100
  493. int status;
  494. static int n;
  495. status = Ser2UTSR0;
  496. /*
  497. * Deal with any receive errors first. The bytes in error may be
  498. * the only bytes in the receive FIFO, so we do this first.
  499. */
  500. while (status & UTSR0_EIF) {
  501. int bstat;
  502. if (debug) {
  503. dprintk("EIF\n");
  504. bstat = Ser2UTSR1;
  505. if (bstat & UTSR1_FRE)
  506. dprintk("frame error\n");
  507. if (bstat & UTSR1_ROR)
  508. dprintk("receive fifo overrun\n");
  509. if (bstat & UTSR1_PRE)
  510. dprintk("parity error\n");
  511. }
  512. bstat = Ser2UTDR;
  513. n++;
  514. status = Ser2UTSR0;
  515. }
  516. if (status & (UTSR0_RFS | UTSR0_RID)) {
  517. do_gettimeofday(&curr_tv);
  518. deltv = delta(&last_tv, &curr_tv);
  519. do {
  520. data = Ser2UTDR;
  521. dprintk("%d data: %u\n", n, (unsigned int) data);
  522. n++;
  523. } while (status & UTSR0_RID && /* do not empty fifo in order to
  524. * get UTSR0_RID in any case */
  525. Ser2UTSR1 & UTSR1_RNE); /* data ready */
  526. if (status&UTSR0_RID) {
  527. add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
  528. add_read_queue(1, n * TIME_CONST); /*pulse*/
  529. n = 0;
  530. last_tv = curr_tv;
  531. }
  532. }
  533. if (status & UTSR0_TFS)
  534. printk(KERN_ERR "transmit fifo not full, shouldn't happen\n");
  535. /* We must clear certain bits. */
  536. status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
  537. if (status)
  538. Ser2UTSR0 = status;
  539. #else
  540. unsigned long deltintrtv;
  541. unsigned long flags;
  542. int iir, lsr;
  543. while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
  544. switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
  545. case UART_IIR_MSI:
  546. (void) inb(io + UART_MSR);
  547. break;
  548. case UART_IIR_RLSI:
  549. (void) inb(io + UART_LSR);
  550. break;
  551. case UART_IIR_THRI:
  552. #if 0
  553. if (lsr & UART_LSR_THRE) /* FIFO is empty */
  554. outb(data, io + UART_TX)
  555. #endif
  556. break;
  557. case UART_IIR_RDI:
  558. /* avoid interference with timer */
  559. spin_lock_irqsave(&timer_lock, flags);
  560. do {
  561. del_timer(&timerlist);
  562. data = inb(io + UART_RX);
  563. do_gettimeofday(&curr_tv);
  564. deltv = delta(&last_tv, &curr_tv);
  565. deltintrtv = delta(&last_intr_tv, &curr_tv);
  566. dprintk("t %lu, d %d\n", deltintrtv, (int)data);
  567. /*
  568. * if nothing came in last X cycles,
  569. * it was gap
  570. */
  571. if (deltintrtv > TIME_CONST * threshold) {
  572. if (last_value) {
  573. dprintk("GAP\n");
  574. /* simulate signal change */
  575. add_read_queue(last_value,
  576. deltv -
  577. deltintrtv);
  578. last_value = 0;
  579. last_tv.tv_sec =
  580. last_intr_tv.tv_sec;
  581. last_tv.tv_usec =
  582. last_intr_tv.tv_usec;
  583. deltv = deltintrtv;
  584. }
  585. }
  586. data = 1;
  587. if (data ^ last_value) {
  588. /*
  589. * deltintrtv > 2*TIME_CONST, remember?
  590. * the other case is timeout
  591. */
  592. add_read_queue(last_value,
  593. deltv-TIME_CONST);
  594. last_value = data;
  595. last_tv = curr_tv;
  596. if (last_tv.tv_usec >= TIME_CONST) {
  597. last_tv.tv_usec -= TIME_CONST;
  598. } else {
  599. last_tv.tv_sec--;
  600. last_tv.tv_usec += 1000000 -
  601. TIME_CONST;
  602. }
  603. }
  604. last_intr_tv = curr_tv;
  605. if (data) {
  606. /*
  607. * start timer for end of
  608. * sequence detection
  609. */
  610. timerlist.expires = jiffies +
  611. SIR_TIMEOUT;
  612. add_timer(&timerlist);
  613. }
  614. lsr = inb(io + UART_LSR);
  615. } while (lsr & UART_LSR_DR); /* data ready */
  616. spin_unlock_irqrestore(&timer_lock, flags);
  617. break;
  618. default:
  619. break;
  620. }
  621. }
  622. #endif
  623. return IRQ_RETVAL(IRQ_HANDLED);
  624. }
  625. #ifdef LIRC_ON_SA1100
  626. static void send_pulse(unsigned long length)
  627. {
  628. unsigned long k, delay;
  629. int flag;
  630. if (length == 0)
  631. return;
  632. /*
  633. * this won't give us the carrier frequency we really want
  634. * due to integer arithmetic, but we can accept this inaccuracy
  635. */
  636. for (k = flag = 0; k < length; k += delay, flag = !flag) {
  637. if (flag) {
  638. off();
  639. delay = space_width;
  640. } else {
  641. on();
  642. delay = pulse_width;
  643. }
  644. safe_udelay(delay);
  645. }
  646. off();
  647. }
  648. static void send_space(unsigned long length)
  649. {
  650. if (length == 0)
  651. return;
  652. off();
  653. safe_udelay(length);
  654. }
  655. #else
  656. static void send_space(unsigned long len)
  657. {
  658. safe_udelay(len);
  659. }
  660. static void send_pulse(unsigned long len)
  661. {
  662. long bytes_out = len / TIME_CONST;
  663. if (bytes_out == 0)
  664. bytes_out++;
  665. while (bytes_out--) {
  666. outb(PULSE, io + UART_TX);
  667. /* FIXME treba seriozne cakanie z char/serial.c */
  668. while (!(inb(io + UART_LSR) & UART_LSR_THRE))
  669. ;
  670. }
  671. }
  672. #endif
  673. #ifdef CONFIG_SA1100_COLLIE
  674. static int sa1100_irda_set_power_collie(int state)
  675. {
  676. if (state) {
  677. /*
  678. * 0 - off
  679. * 1 - short range, lowest power
  680. * 2 - medium range, medium power
  681. * 3 - maximum range, high power
  682. */
  683. ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
  684. TC35143_IODIR_OUTPUT);
  685. ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
  686. udelay(100);
  687. } else {
  688. /* OFF */
  689. ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
  690. TC35143_IODIR_OUTPUT);
  691. ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
  692. }
  693. return 0;
  694. }
  695. #endif
  696. static int init_hardware(void)
  697. {
  698. unsigned long flags;
  699. spin_lock_irqsave(&hardware_lock, flags);
  700. /* reset UART */
  701. #ifdef LIRC_ON_SA1100
  702. #ifdef CONFIG_SA1100_BITSY
  703. if (machine_is_bitsy()) {
  704. printk(KERN_INFO "Power on IR module\n");
  705. set_bitsy_egpio(EGPIO_BITSY_IR_ON);
  706. }
  707. #endif
  708. #ifdef CONFIG_SA1100_COLLIE
  709. sa1100_irda_set_power_collie(3); /* power on */
  710. #endif
  711. sr.hscr0 = Ser2HSCR0;
  712. sr.utcr0 = Ser2UTCR0;
  713. sr.utcr1 = Ser2UTCR1;
  714. sr.utcr2 = Ser2UTCR2;
  715. sr.utcr3 = Ser2UTCR3;
  716. sr.utcr4 = Ser2UTCR4;
  717. sr.utdr = Ser2UTDR;
  718. sr.utsr0 = Ser2UTSR0;
  719. sr.utsr1 = Ser2UTSR1;
  720. /* configure GPIO */
  721. /* output */
  722. PPDR |= PPC_TXD2;
  723. PSDR |= PPC_TXD2;
  724. /* set output to 0 */
  725. off();
  726. /* Enable HP-SIR modulation, and ensure that the port is disabled. */
  727. Ser2UTCR3 = 0;
  728. Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
  729. /* clear status register to prevent unwanted interrupts */
  730. Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
  731. /* 7N1 */
  732. Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
  733. /* 115200 */
  734. Ser2UTCR1 = 0;
  735. Ser2UTCR2 = 1;
  736. /* use HPSIR, 1.6 usec pulses */
  737. Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
  738. /* enable receiver, receive fifo interrupt */
  739. Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
  740. /* clear status register to prevent unwanted interrupts */
  741. Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
  742. #elif defined(LIRC_SIR_TEKRAM)
  743. /* disable FIFO */
  744. soutp(UART_FCR,
  745. UART_FCR_CLEAR_RCVR|
  746. UART_FCR_CLEAR_XMIT|
  747. UART_FCR_TRIGGER_1);
  748. /* Set DLAB 0. */
  749. soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
  750. /* First of all, disable all interrupts */
  751. soutp(UART_IER, sinp(UART_IER) &
  752. (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
  753. /* Set DLAB 1. */
  754. soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
  755. /* Set divisor to 12 => 9600 Baud */
  756. soutp(UART_DLM, 0);
  757. soutp(UART_DLL, 12);
  758. /* Set DLAB 0. */
  759. soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
  760. /* power supply */
  761. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  762. safe_udelay(50*1000);
  763. /* -DTR low -> reset PIC */
  764. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
  765. udelay(1*1000);
  766. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  767. udelay(100);
  768. /* -RTS low -> send control byte */
  769. soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
  770. udelay(7);
  771. soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
  772. /* one byte takes ~1042 usec to transmit at 9600,8N1 */
  773. udelay(1500);
  774. /* back to normal operation */
  775. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  776. udelay(50);
  777. udelay(1500);
  778. /* read previous control byte */
  779. printk(KERN_INFO LIRC_DRIVER_NAME
  780. ": 0x%02x\n", sinp(UART_RX));
  781. /* Set DLAB 1. */
  782. soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
  783. /* Set divisor to 1 => 115200 Baud */
  784. soutp(UART_DLM, 0);
  785. soutp(UART_DLL, 1);
  786. /* Set DLAB 0, 8 Bit */
  787. soutp(UART_LCR, UART_LCR_WLEN8);
  788. /* enable interrupts */
  789. soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
  790. #else
  791. outb(0, io + UART_MCR);
  792. outb(0, io + UART_IER);
  793. /* init UART */
  794. /* set DLAB, speed = 115200 */
  795. outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
  796. outb(1, io + UART_DLL); outb(0, io + UART_DLM);
  797. /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
  798. outb(UART_LCR_WLEN7, io + UART_LCR);
  799. /* FIFO operation */
  800. outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
  801. /* interrupts */
  802. /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
  803. outb(UART_IER_RDI, io + UART_IER);
  804. /* turn on UART */
  805. outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
  806. #ifdef LIRC_SIR_ACTISYS_ACT200L
  807. init_act200();
  808. #elif defined(LIRC_SIR_ACTISYS_ACT220L)
  809. init_act220();
  810. #endif
  811. #endif
  812. spin_unlock_irqrestore(&hardware_lock, flags);
  813. return 0;
  814. }
  815. static void drop_hardware(void)
  816. {
  817. unsigned long flags;
  818. spin_lock_irqsave(&hardware_lock, flags);
  819. #ifdef LIRC_ON_SA1100
  820. Ser2UTCR3 = 0;
  821. Ser2UTCR0 = sr.utcr0;
  822. Ser2UTCR1 = sr.utcr1;
  823. Ser2UTCR2 = sr.utcr2;
  824. Ser2UTCR4 = sr.utcr4;
  825. Ser2UTCR3 = sr.utcr3;
  826. Ser2HSCR0 = sr.hscr0;
  827. #ifdef CONFIG_SA1100_BITSY
  828. if (machine_is_bitsy())
  829. clr_bitsy_egpio(EGPIO_BITSY_IR_ON);
  830. #endif
  831. #ifdef CONFIG_SA1100_COLLIE
  832. sa1100_irda_set_power_collie(0); /* power off */
  833. #endif
  834. #else
  835. /* turn off interrupts */
  836. outb(0, io + UART_IER);
  837. #endif
  838. spin_unlock_irqrestore(&hardware_lock, flags);
  839. }
  840. /* SECTION: Initialisation */
  841. static int init_port(void)
  842. {
  843. int retval;
  844. /* get I/O port access and IRQ line */
  845. #ifndef LIRC_ON_SA1100
  846. if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
  847. printk(KERN_ERR LIRC_DRIVER_NAME
  848. ": i/o port 0x%.4x already in use.\n", io);
  849. return -EBUSY;
  850. }
  851. #endif
  852. retval = request_irq(irq, sir_interrupt, IRQF_DISABLED,
  853. LIRC_DRIVER_NAME, NULL);
  854. if (retval < 0) {
  855. # ifndef LIRC_ON_SA1100
  856. release_region(io, 8);
  857. # endif
  858. printk(KERN_ERR LIRC_DRIVER_NAME
  859. ": IRQ %d already in use.\n",
  860. irq);
  861. return retval;
  862. }
  863. #ifndef LIRC_ON_SA1100
  864. printk(KERN_INFO LIRC_DRIVER_NAME
  865. ": I/O port 0x%.4x, IRQ %d.\n",
  866. io, irq);
  867. #endif
  868. init_timer(&timerlist);
  869. timerlist.function = sir_timeout;
  870. timerlist.data = 0xabadcafe;
  871. return 0;
  872. }
  873. static void drop_port(void)
  874. {
  875. free_irq(irq, NULL);
  876. del_timer_sync(&timerlist);
  877. #ifndef LIRC_ON_SA1100
  878. release_region(io, 8);
  879. #endif
  880. }
  881. #ifdef LIRC_SIR_ACTISYS_ACT200L
  882. /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
  883. /* some code borrowed from Linux IRDA driver */
  884. /* Register 0: Control register #1 */
  885. #define ACT200L_REG0 0x00
  886. #define ACT200L_TXEN 0x01 /* Enable transmitter */
  887. #define ACT200L_RXEN 0x02 /* Enable receiver */
  888. #define ACT200L_ECHO 0x08 /* Echo control chars */
  889. /* Register 1: Control register #2 */
  890. #define ACT200L_REG1 0x10
  891. #define ACT200L_LODB 0x01 /* Load new baud rate count value */
  892. #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */
  893. /* Register 3: Transmit mode register #2 */
  894. #define ACT200L_REG3 0x30
  895. #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
  896. #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */
  897. #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */
  898. /* Register 4: Output Power register */
  899. #define ACT200L_REG4 0x40
  900. #define ACT200L_OP0 0x01 /* Enable LED1C output */
  901. #define ACT200L_OP1 0x02 /* Enable LED2C output */
  902. #define ACT200L_BLKR 0x04
  903. /* Register 5: Receive Mode register */
  904. #define ACT200L_REG5 0x50
  905. #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */
  906. /*.. other various IRDA bit modes, and TV remote modes..*/
  907. /* Register 6: Receive Sensitivity register #1 */
  908. #define ACT200L_REG6 0x60
  909. #define ACT200L_RS0 0x01 /* receive threshold bit 0 */
  910. #define ACT200L_RS1 0x02 /* receive threshold bit 1 */
  911. /* Register 7: Receive Sensitivity register #2 */
  912. #define ACT200L_REG7 0x70
  913. #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */
  914. /* Register 8,9: Baud Rate Divider register #1,#2 */
  915. #define ACT200L_REG8 0x80
  916. #define ACT200L_REG9 0x90
  917. #define ACT200L_2400 0x5f
  918. #define ACT200L_9600 0x17
  919. #define ACT200L_19200 0x0b
  920. #define ACT200L_38400 0x05
  921. #define ACT200L_57600 0x03
  922. #define ACT200L_115200 0x01
  923. /* Register 13: Control register #3 */
  924. #define ACT200L_REG13 0xd0
  925. #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */
  926. /* Register 15: Status register */
  927. #define ACT200L_REG15 0xf0
  928. /* Register 21: Control register #4 */
  929. #define ACT200L_REG21 0x50
  930. #define ACT200L_EXCK 0x02 /* Disable clock output driver */
  931. #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */
  932. static void init_act200(void)
  933. {
  934. int i;
  935. __u8 control[] = {
  936. ACT200L_REG15,
  937. ACT200L_REG13 | ACT200L_SHDW,
  938. ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
  939. ACT200L_REG13,
  940. ACT200L_REG7 | ACT200L_ENPOS,
  941. ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1,
  942. ACT200L_REG5 | ACT200L_RWIDL,
  943. ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR,
  944. ACT200L_REG3 | ACT200L_B0,
  945. ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN,
  946. ACT200L_REG8 | (ACT200L_115200 & 0x0f),
  947. ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
  948. ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
  949. };
  950. /* Set DLAB 1. */
  951. soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
  952. /* Set divisor to 12 => 9600 Baud */
  953. soutp(UART_DLM, 0);
  954. soutp(UART_DLL, 12);
  955. /* Set DLAB 0. */
  956. soutp(UART_LCR, UART_LCR_WLEN8);
  957. /* Set divisor to 12 => 9600 Baud */
  958. /* power supply */
  959. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  960. for (i = 0; i < 50; i++)
  961. safe_udelay(1000);
  962. /* Reset the dongle : set RTS low for 25 ms */
  963. soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
  964. for (i = 0; i < 25; i++)
  965. udelay(1000);
  966. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  967. udelay(100);
  968. /* Clear DTR and set RTS to enter command mode */
  969. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
  970. udelay(7);
  971. /* send out the control register settings for 115K 7N1 SIR operation */
  972. for (i = 0; i < sizeof(control); i++) {
  973. soutp(UART_TX, control[i]);
  974. /* one byte takes ~1042 usec to transmit at 9600,8N1 */
  975. udelay(1500);
  976. }
  977. /* back to normal operation */
  978. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  979. udelay(50);
  980. udelay(1500);
  981. soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
  982. /* Set DLAB 1. */
  983. soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
  984. /* Set divisor to 1 => 115200 Baud */
  985. soutp(UART_DLM, 0);
  986. soutp(UART_DLL, 1);
  987. /* Set DLAB 0. */
  988. soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
  989. /* Set DLAB 0, 7 Bit */
  990. soutp(UART_LCR, UART_LCR_WLEN7);
  991. /* enable interrupts */
  992. soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
  993. }
  994. #endif
  995. #ifdef LIRC_SIR_ACTISYS_ACT220L
  996. /*
  997. * Derived from linux IrDA driver (net/irda/actisys.c)
  998. * Drop me a mail for any kind of comment: maxx@spaceboyz.net
  999. */
  1000. void init_act220(void)
  1001. {
  1002. int i;
  1003. /* DLAB 1 */
  1004. soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
  1005. /* 9600 baud */
  1006. soutp(UART_DLM, 0);
  1007. soutp(UART_DLL, 12);
  1008. /* DLAB 0 */
  1009. soutp(UART_LCR, UART_LCR_WLEN7);
  1010. /* reset the dongle, set DTR low for 10us */
  1011. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
  1012. udelay(10);
  1013. /* back to normal (still 9600) */
  1014. soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
  1015. /*
  1016. * send RTS pulses until we reach 115200
  1017. * i hope this is really the same for act220l/act220l+
  1018. */
  1019. for (i = 0; i < 3; i++) {
  1020. udelay(10);
  1021. /* set RTS low for 10 us */
  1022. soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
  1023. udelay(10);
  1024. /* set RTS high for 10 us */
  1025. soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
  1026. }
  1027. /* back to normal operation */
  1028. udelay(1500); /* better safe than sorry ;) */
  1029. /* Set DLAB 1. */
  1030. soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
  1031. /* Set divisor to 1 => 115200 Baud */
  1032. soutp(UART_DLM, 0);
  1033. soutp(UART_DLL, 1);
  1034. /* Set DLAB 0, 7 Bit */
  1035. /* The dongle doesn't seem to have any problems with operation at 7N1 */
  1036. soutp(UART_LCR, UART_LCR_WLEN7);
  1037. /* enable interrupts */
  1038. soutp(UART_IER, UART_IER_RDI);
  1039. }
  1040. #endif
  1041. static int init_lirc_sir(void)
  1042. {
  1043. int retval;
  1044. init_waitqueue_head(&lirc_read_queue);
  1045. retval = init_port();
  1046. if (retval < 0)
  1047. return retval;
  1048. init_hardware();
  1049. printk(KERN_INFO LIRC_DRIVER_NAME
  1050. ": Installed.\n");
  1051. return 0;
  1052. }
  1053. static int __init lirc_sir_init(void)
  1054. {
  1055. int retval;
  1056. retval = init_chrdev();
  1057. if (retval < 0)
  1058. return retval;
  1059. retval = init_lirc_sir();
  1060. if (retval) {
  1061. drop_chrdev();
  1062. return retval;
  1063. }
  1064. return 0;
  1065. }
  1066. static void __exit lirc_sir_exit(void)
  1067. {
  1068. drop_hardware();
  1069. drop_chrdev();
  1070. drop_port();
  1071. printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n");
  1072. }
  1073. module_init(lirc_sir_init);
  1074. module_exit(lirc_sir_exit);
  1075. #ifdef LIRC_SIR_TEKRAM
  1076. MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
  1077. MODULE_AUTHOR("Christoph Bartelmus");
  1078. #elif defined(LIRC_ON_SA1100)
  1079. MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
  1080. MODULE_AUTHOR("Christoph Bartelmus");
  1081. #elif defined(LIRC_SIR_ACTISYS_ACT200L)
  1082. MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
  1083. MODULE_AUTHOR("Karl Bongers");
  1084. #elif defined(LIRC_SIR_ACTISYS_ACT220L)
  1085. MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
  1086. MODULE_AUTHOR("Jan Roemisch");
  1087. #else
  1088. MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
  1089. MODULE_AUTHOR("Milan Pikula");
  1090. #endif
  1091. MODULE_LICENSE("GPL");
  1092. #ifdef LIRC_ON_SA1100
  1093. module_param(irq, int, S_IRUGO);
  1094. MODULE_PARM_DESC(irq, "Interrupt (16)");
  1095. #else
  1096. module_param(io, int, S_IRUGO);
  1097. MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
  1098. module_param(irq, int, S_IRUGO);
  1099. MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
  1100. module_param(threshold, int, S_IRUGO);
  1101. MODULE_PARM_DESC(threshold, "space detection threshold (3)");
  1102. #endif
  1103. module_param(debug, bool, S_IRUGO | S_IWUSR);
  1104. MODULE_PARM_DESC(debug, "Enable debugging messages");