/drivers/staging/comedi/drivers/adv_pci1710.c

https://bitbucket.org/wisechild/galaxy-nexus · C · 1663 lines · 1297 code · 198 blank · 168 comment · 214 complexity · 89e11d93bacbf1bb80d511b219b6b1f6 MD5 · raw file 

    

  1. /*
    2. 

  2.  * comedi/drivers/adv_pci1710.c
    3. 

  3.  *
    4. 

  4.  * Author: Michal Dobes <dobes@tesnet.cz>
    5. 

  5.  *
    6. 

  6.  * Thanks to ZhenGang Shang <ZhenGang.Shang@Advantech.com.cn>
    7. 

  7.  * for testing and informations.
    8. 

  8.  *
    9. 

  9.  *  hardware driver for Advantech cards:
    10. 

  10.  *   card:   PCI-1710, PCI-1710HG, PCI-1711, PCI-1713, PCI-1720, PCI-1731
    11. 

  11.  *   driver: pci1710,  pci1710hg,  pci1711,  pci1713,  pci1720,  pci1731
    12. 

  12.  *
    13. 

  13.  * Options:
    14. 

  14.  *  [0] - PCI bus number - if bus number and slot number are 0,
    15. 

  15.  *                         then driver search for first unused card
    16. 

  16.  *  [1] - PCI slot number
    17. 

  17.  *
    18. 

  18. */
    19. 

  19. /*
    20. 

  20. Driver: adv_pci1710
    21. 

  21. Description: Advantech PCI-1710, PCI-1710HG, PCI-1711, PCI-1713,
    22. 

  22. 	     Advantech PCI-1720, PCI-1731
    23. 

  23. Author: Michal Dobes <dobes@tesnet.cz>
    24. 

  24. Devices: [Advantech] PCI-1710 (adv_pci1710), PCI-1710HG (pci1710hg),
    25. 

  25.   PCI-1711 (adv_pci1710), PCI-1713, PCI-1720,
    26. 

  26.   PCI-1731
    27. 

  27. Status: works
    28. 

    29. 

  29. This driver supports AI, AO, DI and DO subdevices.
    30. 

  30. AI subdevice supports cmd and insn interface,
    31. 

  31. other subdevices support only insn interface.
    32. 

    33. 

  33. The PCI-1710 and PCI-1710HG have the same PCI device ID, so the
    34. 

  34. driver cannot distinguish between them, as would be normal for a
    35. 

  35. PCI driver.
    36. 

    37. 

  37. Configuration options:
    38. 

  38.   [0] - PCI bus of device (optional)
    39. 

  39.   [1] - PCI slot of device (optional)
    40. 

  40. 	If bus/slot is not specified, the first available PCI
    41. 

  41. 	device will be used.
    42. 

  42. */
    43. 

  43. 

  44. #include <linux/interrupt.h>
    45. 

  45. 

  46. #include "../comedidev.h"
    47. 

  47. 

  48. #include "comedi_pci.h"
    49. 

  49. 

  50. #include "8253.h"
    51. 

  51. #include "amcc_s5933.h"
    52. 

  52. 

  53. #define PCI171x_PARANOIDCHECK	/* if defined, then is used code which control
    54. 

  54. 				 * correct channel number on every 12 bit
    55. 

  55. 				 * sample */
    56. 

  56. 

  57. #undef PCI171X_EXTDEBUG
    58. 

  58. 

  59. #define DRV_NAME "adv_pci1710"
    60. 

  60. 

  61. #undef DPRINTK
    62. 

  62. #ifdef PCI171X_EXTDEBUG
    63. 

  63. #define DPRINTK(fmt, args...) printk(fmt, ## args)
    64. 

  64. #else
    65. 

  65. #define DPRINTK(fmt, args...)
    66. 

  66. #endif
    67. 

  67. 

  68. #define PCI_VENDOR_ID_ADVANTECH		0x13fe
    69. 

  69. 

  70. /* hardware types of the cards */
    71. 

  71. #define TYPE_PCI171X	0
    72. 

  72. #define TYPE_PCI1713	2
    73. 

  73. #define TYPE_PCI1720	3
    74. 

  74. 

  75. #define IORANGE_171x	32
    76. 

  76. #define IORANGE_1720	16
    77. 

  77. 

  78. #define PCI171x_AD_DATA	 0	/* R:   A/D data */
    79. 

  79. #define PCI171x_SOFTTRG	 0	/* W:   soft trigger for A/D */
    80. 

  80. #define PCI171x_RANGE	 2	/* W:   A/D gain/range register */
    81. 

  81. #define PCI171x_MUX	 4	/* W:   A/D multiplexor control */
    82. 

  82. #define PCI171x_STATUS	 6	/* R:   status register */
    83. 

  83. #define PCI171x_CONTROL	 6	/* W:   control register */
    84. 

  84. #define PCI171x_CLRINT	 8	/* W:   clear interrupts request */
    85. 

  85. #define PCI171x_CLRFIFO	 9	/* W:   clear FIFO */
    86. 

  86. #define PCI171x_DA1	10	/* W:   D/A register */
    87. 

  87. #define PCI171x_DA2	12	/* W:   D/A register */
    88. 

  88. #define PCI171x_DAREF	14	/* W:   D/A reference control */
    89. 

  89. #define PCI171x_DI	16	/* R:   digi inputs */
    90. 

  90. #define PCI171x_DO	16	/* R:   digi inputs */
    91. 

  91. #define PCI171x_CNT0	24	/* R/W: 8254 counter 0 */
    92. 

  92. #define PCI171x_CNT1	26	/* R/W: 8254 counter 1 */
    93. 

  93. #define PCI171x_CNT2	28	/* R/W: 8254 counter 2 */
    94. 

  94. #define PCI171x_CNTCTRL	30	/* W:   8254 counter control */
    95. 

  95. 

  96. /* upper bits from status register (PCI171x_STATUS) (lower is same with control
    97. 

  97.  * reg) */
    98. 

  98. #define	Status_FE	0x0100	/* 1=FIFO is empty */
    99. 

  99. #define Status_FH	0x0200	/* 1=FIFO is half full */
    100. 

  100. #define Status_FF	0x0400	/* 1=FIFO is full, fatal error */
    101. 

  101. #define Status_IRQ	0x0800	/* 1=IRQ occurred */
    102. 

  102. /* bits from control register (PCI171x_CONTROL) */
    103. 

  103. #define Control_CNT0	0x0040	/* 1=CNT0 have external source,
    104. 

  104. 				 * 0=have internal 100kHz source */
    105. 

  105. #define Control_ONEFH	0x0020	/* 1=IRQ on FIFO is half full, 0=every sample */
    106. 

  106. #define Control_IRQEN	0x0010	/* 1=enable IRQ */
    107. 

  107. #define Control_GATE	0x0008	/* 1=enable external trigger GATE (8254?) */
    108. 

  108. #define Control_EXT	0x0004	/* 1=external trigger source */
    109. 

  109. #define Control_PACER	0x0002	/* 1=enable internal 8254 trigger source */
    110. 

  110. #define Control_SW	0x0001	/* 1=enable software trigger source */
    111. 

  111. /* bits from counter control register (PCI171x_CNTCTRL) */
    112. 

  112. #define Counter_BCD     0x0001	/* 0 = binary counter, 1 = BCD counter */
    113. 

  113. #define Counter_M0      0x0002	/* M0-M2 select modes 0-5 */
    114. 

  114. #define Counter_M1      0x0004	/* 000 = mode 0, 010 = mode 2 ... */
    115. 

  115. #define Counter_M2      0x0008
    116. 

  116. #define Counter_RW0     0x0010	/* RW0/RW1 select read/write mode */
    117. 

  117. #define Counter_RW1     0x0020
    118. 

  118. #define Counter_SC0     0x0040	/* Select Counter. Only 00 or 11 may */
    119. 

  119. #define Counter_SC1     0x0080	/* be used, 00 for CNT0,
    120. 

  120. 				 * 11 for read-back command */
    121. 

  121. 

  122. #define PCI1720_DA0	 0	/* W:   D/A register 0 */
    123. 

  123. #define PCI1720_DA1	 2	/* W:   D/A register 1 */
    124. 

  124. #define PCI1720_DA2	 4	/* W:   D/A register 2 */
    125. 

  125. #define PCI1720_DA3	 6	/* W:   D/A register 3 */
    126. 

  126. #define PCI1720_RANGE	 8	/* R/W: D/A range register */
    127. 

  127. #define PCI1720_SYNCOUT	 9	/* W:   D/A synchronized output register */
    128. 

  128. #define PCI1720_SYNCONT	15	/* R/W: D/A synchronized control */
    129. 

  129. 

  130. /* D/A synchronized control (PCI1720_SYNCONT) */
    131. 

  131. #define Syncont_SC0	 1	/* set synchronous output mode */
    132. 

  132. 

  133. static const struct comedi_lrange range_pci1710_3 = { 9, {
    134. 

  134. 							  BIP_RANGE(5),
    135. 

  135. 							  BIP_RANGE(2.5),
    136. 

  136. 							  BIP_RANGE(1.25),
    137. 

  137. 							  BIP_RANGE(0.625),
    138. 

  138. 							  BIP_RANGE(10),
    139. 

  139. 							  UNI_RANGE(10),
    140. 

  140. 							  UNI_RANGE(5),
    141. 

  141. 							  UNI_RANGE(2.5),
    142. 

  142. 							  UNI_RANGE(1.25)
    143. 

  143. 							  }
    144. 

  144. };
    145. 

  145. 

  146. static const char range_codes_pci1710_3[] = { 0x00, 0x01, 0x02, 0x03, 0x04,
    147. 

  147. 					      0x10, 0x11, 0x12, 0x13 };
    148. 

  148. 

  149. static const struct comedi_lrange range_pci1710hg = { 12, {
    150. 

  150. 							   BIP_RANGE(5),
    151. 

  151. 							   BIP_RANGE(0.5),
    152. 

  152. 							   BIP_RANGE(0.05),
    153. 

  153. 							   BIP_RANGE(0.005),
    154. 

  154. 							   BIP_RANGE(10),
    155. 

  155. 							   BIP_RANGE(1),
    156. 

  156. 							   BIP_RANGE(0.1),
    157. 

  157. 							   BIP_RANGE(0.01),
    158. 

  158. 							   UNI_RANGE(10),
    159. 

  159. 							   UNI_RANGE(1),
    160. 

  160. 							   UNI_RANGE(0.1),
    161. 

  161. 							   UNI_RANGE(0.01)
    162. 

  162. 							   }
    163. 

  163. };
    164. 

  164. 

  165. static const char range_codes_pci1710hg[] = { 0x00, 0x01, 0x02, 0x03, 0x04,
    166. 

  166. 					      0x05, 0x06, 0x07, 0x10, 0x11,
    167. 

  167. 					      0x12, 0x13 };
    168. 

  168. 

  169. static const struct comedi_lrange range_pci17x1 = { 5, {
    170. 

  170. 							BIP_RANGE(10),
    171. 

  171. 							BIP_RANGE(5),
    172. 

  172. 							BIP_RANGE(2.5),
    173. 

  173. 							BIP_RANGE(1.25),
    174. 

  174. 							BIP_RANGE(0.625)
    175. 

  175. 							}
    176. 

  176. };
    177. 

  177. 

  178. static const char range_codes_pci17x1[] = { 0x00, 0x01, 0x02, 0x03, 0x04 };
    179. 

  179. 

  180. static const struct comedi_lrange range_pci1720 = { 4, {
    181. 

  181. 							UNI_RANGE(5),
    182. 

  182. 							UNI_RANGE(10),
    183. 

  183. 							BIP_RANGE(5),
    184. 

  184. 							BIP_RANGE(10)
    185. 

  185. 							}
    186. 

  186. };
    187. 

  187. 

  188. static const struct comedi_lrange range_pci171x_da = { 2, {
    189. 

  189. 							   UNI_RANGE(5),
    190. 

  190. 							   UNI_RANGE(10),
    191. 

  191. 							   }
    192. 

  192. };
    193. 

  193. 

  194. static int pci1710_attach(struct comedi_device *dev,
    195. 

  195. 			  struct comedi_devconfig *it);
    196. 

  196. static int pci1710_detach(struct comedi_device *dev);
    197. 

  197. 

  198. struct boardtype {
    199. 

  199. 	const char *name;	/*  board name */
    200. 

  200. 	int device_id;
    201. 

  201. 	int iorange;		/*  I/O range len */
    202. 

  202. 	char have_irq;		/*  1=card support IRQ */
    203. 

  203. 	char cardtype;		/*  0=1710& co. 2=1713, ... */
    204. 

  204. 	int n_aichan;		/*  num of A/D chans */
    205. 

  205. 	int n_aichand;		/*  num of A/D chans in diff mode */
    206. 

  206. 	int n_aochan;		/*  num of D/A chans */
    207. 

  207. 	int n_dichan;		/*  num of DI chans */
    208. 

  208. 	int n_dochan;		/*  num of DO chans */
    209. 

  209. 	int n_counter;		/*  num of counters */
    210. 

  210. 	int ai_maxdata;		/*  resolution of A/D */
    211. 

  211. 	int ao_maxdata;		/*  resolution of D/A */
    212. 

  212. 	const struct comedi_lrange *rangelist_ai;	/*  rangelist for A/D */
    213. 

  213. 	const char *rangecode_ai;	/*  range codes for programming */
    214. 

  214. 	const struct comedi_lrange *rangelist_ao;	/*  rangelist for D/A */
    215. 

  215. 	unsigned int ai_ns_min;	/*  max sample speed of card v ns */
    216. 

  216. 	unsigned int fifo_half_size;	/*  size of FIFO/2 */
    217. 

  217. };
    218. 

  218. 

  219. static DEFINE_PCI_DEVICE_TABLE(pci1710_pci_table) = {
    220. 

  220. 	{ PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1710) },
    221. 

  221. 	{ PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1711) },
    222. 

  222. 	{ PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1713) },
    223. 

  223. 	{ PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1720) },
    224. 

  224. 	{ PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1731) },
    225. 

  225. 	{ 0 }
    226. 

  226. };
    227. 

  227. 

  228. MODULE_DEVICE_TABLE(pci, pci1710_pci_table);
    229. 

  229. 

  230. static const struct boardtype boardtypes[] = {
    231. 

  231. 	{"pci1710", 0x1710,
    232. 

  232. 	 IORANGE_171x, 1, TYPE_PCI171X,
    233. 

  233. 	 16, 8, 2, 16, 16, 1, 0x0fff, 0x0fff,
    234. 

  234. 	 &range_pci1710_3, range_codes_pci1710_3,
    235. 

  235. 	 &range_pci171x_da,
    236. 

  236. 	 10000, 2048},
    237. 

  237. 	{"pci1710hg", 0x1710,
    238. 

  238. 	 IORANGE_171x, 1, TYPE_PCI171X,
    239. 

  239. 	 16, 8, 2, 16, 16, 1, 0x0fff, 0x0fff,
    240. 

  240. 	 &range_pci1710hg, range_codes_pci1710hg,
    241. 

  241. 	 &range_pci171x_da,
    242. 

  242. 	 10000, 2048},
    243. 

  243. 	{"pci1711", 0x1711,
    244. 

  244. 	 IORANGE_171x, 1, TYPE_PCI171X,
    245. 

  245. 	 16, 0, 2, 16, 16, 1, 0x0fff, 0x0fff,
    246. 

  246. 	 &range_pci17x1, range_codes_pci17x1, &range_pci171x_da,
    247. 

  247. 	 10000, 512},
    248. 

  248. 	{"pci1713", 0x1713,
    249. 

  249. 	 IORANGE_171x, 1, TYPE_PCI1713,
    250. 

  250. 	 32, 16, 0, 0, 0, 0, 0x0fff, 0x0000,
    251. 

  251. 	 &range_pci1710_3, range_codes_pci1710_3, NULL,
    252. 

  252. 	 10000, 2048},
    253. 

  253. 	{"pci1720", 0x1720,
    254. 

  254. 	 IORANGE_1720, 0, TYPE_PCI1720,
    255. 

  255. 	 0, 0, 4, 0, 0, 0, 0x0000, 0x0fff,
    256. 

  256. 	 NULL, NULL, &range_pci1720,
    257. 

  257. 	 0, 0},
    258. 

  258. 	{"pci1731", 0x1731,
    259. 

  259. 	 IORANGE_171x, 1, TYPE_PCI171X,
    260. 

  260. 	 16, 0, 0, 16, 16, 0, 0x0fff, 0x0000,
    261. 

  261. 	 &range_pci17x1, range_codes_pci17x1, NULL,
    262. 

  262. 	 10000, 512},
    263. 

  263. 	/*  dummy entry corresponding to driver name */
    264. 

  264. 	{.name = DRV_NAME},
    265. 

  265. };
    266. 

  266. 

  267. #define n_boardtypes (sizeof(boardtypes)/sizeof(struct boardtype))
    268. 

  268. 

  269. static struct comedi_driver driver_pci1710 = {
    270. 

  270. 	.driver_name = DRV_NAME,
    271. 

  271. 	.module = THIS_MODULE,
    272. 

  272. 	.attach = pci1710_attach,
    273. 

  273. 	.detach = pci1710_detach,
    274. 

  274. 	.num_names = n_boardtypes,
    275. 

  275. 	.board_name = &boardtypes[0].name,
    276. 

  276. 	.offset = sizeof(struct boardtype),
    277. 

  277. };
    278. 

  278. 

  279. struct pci1710_private {
    280. 

  280. 	struct pci_dev *pcidev;	/*  ptr to PCI device */
    281. 

  281. 	char valid;		/*  card is usable */
    282. 

  282. 	char neverending_ai;	/*  we do unlimited AI */
    283. 

  283. 	unsigned int CntrlReg;	/*  Control register */
    284. 

  284. 	unsigned int i8254_osc_base;	/*  frequence of onboard oscilator */
    285. 

  285. 	unsigned int ai_do;	/*  what do AI? 0=nothing, 1 to 4 mode */
    286. 

  286. 	unsigned int ai_act_scan;	/*  how many scans we finished */
    287. 

  287. 	unsigned int ai_act_chan;	/*  actual position in actual scan */
    288. 

  288. 	unsigned int ai_buf_ptr;	/*  data buffer ptr in samples */
    289. 

  289. 	unsigned char ai_eos;	/*  1=EOS wake up */
    290. 

  290. 	unsigned char ai_et;
    291. 

  291. 	unsigned int ai_et_CntrlReg;
    292. 

  292. 	unsigned int ai_et_MuxVal;
    293. 

  293. 	unsigned int ai_et_div1, ai_et_div2;
    294. 

  294. 	unsigned int act_chanlist[32];	/*  list of scaned channel */
    295. 

  295. 	unsigned char act_chanlist_len;	/*  len of scanlist */
    296. 

  296. 	unsigned char act_chanlist_pos;	/*  actual position in MUX list */
    297. 

  297. 	unsigned char da_ranges;	/*  copy of D/A outpit range register */
    298. 

  298. 	unsigned int ai_scans;	/*  len of scanlist */
    299. 

  299. 	unsigned int ai_n_chan;	/*  how many channels is measured */
    300. 

  300. 	unsigned int *ai_chanlist;	/*  actaul chanlist */
    301. 

  301. 	unsigned int ai_flags;	/*  flaglist */
    302. 

  302. 	unsigned int ai_data_len;	/*  len of data buffer */
    303. 

  303. 	short *ai_data;		/*  data buffer */
    304. 

  304. 	unsigned int ai_timer1;	/*  timers */
    305. 

  305. 	unsigned int ai_timer2;
    306. 

  306. 	short ao_data[4];	/*  data output buffer */
    307. 

  307. 	unsigned int cnt0_write_wait;	/* after a write, wait for update of the
    308. 

  308. 					 * internal state */
    309. 

  309. };
    310. 

  310. 

  311. #define devpriv ((struct pci1710_private *)dev->private)
    312. 

  312. #define this_board ((const struct boardtype *)dev->board_ptr)
    313. 

  313. 

  314. /*
    315. 

  315. ==============================================================================
    316. 

  316. */
    317. 

  317. 

  318. static int check_channel_list(struct comedi_device *dev,
    319. 

  319. 			      struct comedi_subdevice *s,
    320. 

  320. 			      unsigned int *chanlist, unsigned int n_chan);
    321. 

  321. static void setup_channel_list(struct comedi_device *dev,
    322. 

  322. 			       struct comedi_subdevice *s,
    323. 

  323. 			       unsigned int *chanlist, unsigned int n_chan,
    324. 

  324. 			       unsigned int seglen);
    325. 

  325. static void start_pacer(struct comedi_device *dev, int mode,
    326. 

  326. 			unsigned int divisor1, unsigned int divisor2);
    327. 

  327. static int pci1710_reset(struct comedi_device *dev);
    328. 

  328. static int pci171x_ai_cancel(struct comedi_device *dev,
    329. 

  329. 			     struct comedi_subdevice *s);
    330. 

  330. 

  331. /*  used for gain list programming */
    332. 

  332. static const unsigned int muxonechan[] = {
    333. 

  333. 	0x0000, 0x0101, 0x0202, 0x0303, 0x0404, 0x0505, 0x0606, 0x0707,
    334. 

  334. 	0x0808, 0x0909, 0x0a0a, 0x0b0b, 0x0c0c, 0x0d0d, 0x0e0e, 0x0f0f,
    335. 

  335. 	0x1010, 0x1111, 0x1212, 0x1313, 0x1414, 0x1515, 0x1616, 0x1717,
    336. 

  336. 	0x1818, 0x1919, 0x1a1a, 0x1b1b, 0x1c1c, 0x1d1d, 0x1e1e, 0x1f1f
    337. 

  337. };
    338. 

  338. 

  339. /*
    340. 

  340. ==============================================================================
    341. 

  341. */
    342. 

  342. static int pci171x_insn_read_ai(struct comedi_device *dev,
    343. 

  343. 				struct comedi_subdevice *s,
    344. 

  344. 				struct comedi_insn *insn, unsigned int *data)
    345. 

  345. {
    346. 

  346. 	int n, timeout;
    347. 

  347. #ifdef PCI171x_PARANOIDCHECK
    348. 

  348. 	unsigned int idata;
    349. 

  349. #endif
    350. 

  350. 

  351. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_insn_read_ai(...)\n");
    352. 

  352. 	devpriv->CntrlReg &= Control_CNT0;
    353. 

  353. 	devpriv->CntrlReg |= Control_SW;	/*  set software trigger */
    354. 

  354. 	outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
    355. 

  355. 	outb(0, dev->iobase + PCI171x_CLRFIFO);
    356. 

  356. 	outb(0, dev->iobase + PCI171x_CLRINT);
    357. 

  357. 

  358. 	setup_channel_list(dev, s, &insn->chanspec, 1, 1);
    359. 

  359. 

  360. 	DPRINTK("adv_pci1710 A ST=%4x IO=%x\n",
    361. 

  361. 		inw(dev->iobase + PCI171x_STATUS),
    362. 

  362. 		dev->iobase + PCI171x_STATUS);
    363. 

  363. 	for (n = 0; n < insn->n; n++) {
    364. 

  364. 		outw(0, dev->iobase + PCI171x_SOFTTRG);	/* start conversion */
    365. 

  365. 		DPRINTK("adv_pci1710 B n=%d ST=%4x\n", n,
    366. 

  366. 			inw(dev->iobase + PCI171x_STATUS));
    367. 

  367. 		/* udelay(1); */
    368. 

  368. 		DPRINTK("adv_pci1710 C n=%d ST=%4x\n", n,
    369. 

  369. 			inw(dev->iobase + PCI171x_STATUS));
    370. 

  370. 		timeout = 100;
    371. 

  371. 		while (timeout--) {
    372. 

  372. 			if (!(inw(dev->iobase + PCI171x_STATUS) & Status_FE))
    373. 

  373. 				goto conv_finish;
    374. 

  374. 			if (!(timeout % 10))
    375. 

  375. 				DPRINTK("adv_pci1710 D n=%d tm=%d ST=%4x\n", n,
    376. 

  376. 					timeout,
    377. 

  377. 					inw(dev->iobase + PCI171x_STATUS));
    378. 

  378. 		}
    379. 

  379. 		comedi_error(dev, "A/D insn timeout");
    380. 

  380. 		outb(0, dev->iobase + PCI171x_CLRFIFO);
    381. 

  381. 		outb(0, dev->iobase + PCI171x_CLRINT);
    382. 

  382. 		data[n] = 0;
    383. 

  383. 		DPRINTK
    384. 

  384. 		    ("adv_pci1710 EDBG: END: pci171x_insn_read_ai(...) n=%d\n",
    385. 

  385. 		     n);
    386. 

  386. 		return -ETIME;
    387. 

  387. 

  388. conv_finish:
    389. 

  389. #ifdef PCI171x_PARANOIDCHECK
    390. 

  390. 		idata = inw(dev->iobase + PCI171x_AD_DATA);
    391. 

  391. 		if (this_board->cardtype != TYPE_PCI1713)
    392. 

  392. 			if ((idata & 0xf000) != devpriv->act_chanlist[0]) {
    393. 

  393. 				comedi_error(dev, "A/D insn data droput!");
    394. 

  394. 				return -ETIME;
    395. 

  395. 			}
    396. 

  396. 		data[n] = idata & 0x0fff;
    397. 

  397. #else
    398. 

  398. 		data[n] = inw(dev->iobase + PCI171x_AD_DATA) & 0x0fff;
    399. 

  399. #endif
    400. 

  400. 

  401. 	}
    402. 

  402. 

  403. 	outb(0, dev->iobase + PCI171x_CLRFIFO);
    404. 

  404. 	outb(0, dev->iobase + PCI171x_CLRINT);
    405. 

  405. 

  406. 	DPRINTK("adv_pci1710 EDBG: END: pci171x_insn_read_ai(...) n=%d\n", n);
    407. 

  407. 	return n;
    408. 

  408. }
    409. 

  409. 

  410. /*
    411. 

  411. ==============================================================================
    412. 

  412. */
    413. 

  413. static int pci171x_insn_write_ao(struct comedi_device *dev,
    414. 

  414. 				 struct comedi_subdevice *s,
    415. 

  415. 				 struct comedi_insn *insn, unsigned int *data)
    416. 

  416. {
    417. 

  417. 	int n, chan, range, ofs;
    418. 

  418. 

  419. 	chan = CR_CHAN(insn->chanspec);
    420. 

  420. 	range = CR_RANGE(insn->chanspec);
    421. 

  421. 	if (chan) {
    422. 

  422. 		devpriv->da_ranges &= 0xfb;
    423. 

  423. 		devpriv->da_ranges |= (range << 2);
    424. 

  424. 		outw(devpriv->da_ranges, dev->iobase + PCI171x_DAREF);
    425. 

  425. 		ofs = PCI171x_DA2;
    426. 

  426. 	} else {
    427. 

  427. 		devpriv->da_ranges &= 0xfe;
    428. 

  428. 		devpriv->da_ranges |= range;
    429. 

  429. 		outw(devpriv->da_ranges, dev->iobase + PCI171x_DAREF);
    430. 

  430. 		ofs = PCI171x_DA1;
    431. 

  431. 	}
    432. 

  432. 

  433. 	for (n = 0; n < insn->n; n++)
    434. 

  434. 		outw(data[n], dev->iobase + ofs);
    435. 

  435. 

  436. 	devpriv->ao_data[chan] = data[n];
    437. 

  437. 

  438. 	return n;
    439. 

  439. 

  440. }
    441. 

  441. 

  442. /*
    443. 

  443. ==============================================================================
    444. 

  444. */
    445. 

  445. static int pci171x_insn_read_ao(struct comedi_device *dev,
    446. 

  446. 				struct comedi_subdevice *s,
    447. 

  447. 				struct comedi_insn *insn, unsigned int *data)
    448. 

  448. {
    449. 

  449. 	int n, chan;
    450. 

  450. 

  451. 	chan = CR_CHAN(insn->chanspec);
    452. 

  452. 	for (n = 0; n < insn->n; n++)
    453. 

  453. 		data[n] = devpriv->ao_data[chan];
    454. 

  454. 

  455. 	return n;
    456. 

  456. }
    457. 

  457. 

  458. /*
    459. 

  459. ==============================================================================
    460. 

  460. */
    461. 

  461. static int pci171x_insn_bits_di(struct comedi_device *dev,
    462. 

  462. 				struct comedi_subdevice *s,
    463. 

  463. 				struct comedi_insn *insn, unsigned int *data)
    464. 

  464. {
    465. 

  465. 	data[1] = inw(dev->iobase + PCI171x_DI);
    466. 

  466. 

  467. 	return 2;
    468. 

  468. }
    469. 

  469. 

  470. /*
    471. 

  471. ==============================================================================
    472. 

  472. */
    473. 

  473. static int pci171x_insn_bits_do(struct comedi_device *dev,
    474. 

  474. 				struct comedi_subdevice *s,
    475. 

  475. 				struct comedi_insn *insn, unsigned int *data)
    476. 

  476. {
    477. 

  477. 	if (data[0]) {
    478. 

  478. 		s->state &= ~data[0];
    479. 

  479. 		s->state |= (data[0] & data[1]);
    480. 

  480. 		outw(s->state, dev->iobase + PCI171x_DO);
    481. 

  481. 	}
    482. 

  482. 	data[1] = s->state;
    483. 

  483. 

  484. 	return 2;
    485. 

  485. }
    486. 

  486. 

  487. /*
    488. 

  488. ==============================================================================
    489. 

  489. */
    490. 

  490. static int pci171x_insn_counter_read(struct comedi_device *dev,
    491. 

  491. 				     struct comedi_subdevice *s,
    492. 

  492. 				     struct comedi_insn *insn,
    493. 

  493. 				     unsigned int *data)
    494. 

  494. {
    495. 

  495. 	unsigned int msb, lsb, ccntrl;
    496. 

  496. 	int i;
    497. 

  497. 

  498. 	ccntrl = 0xD2;		/* count only */
    499. 

  499. 	for (i = 0; i < insn->n; i++) {
    500. 

  500. 		outw(ccntrl, dev->iobase + PCI171x_CNTCTRL);
    501. 

  501. 

  502. 		lsb = inw(dev->iobase + PCI171x_CNT0) & 0xFF;
    503. 

  503. 		msb = inw(dev->iobase + PCI171x_CNT0) & 0xFF;
    504. 

  504. 

  505. 		data[0] = lsb | (msb << 8);
    506. 

  506. 	}
    507. 

  507. 

  508. 	return insn->n;
    509. 

  509. }
    510. 

  510. 

  511. /*
    512. 

  512. ==============================================================================
    513. 

  513. */
    514. 

  514. static int pci171x_insn_counter_write(struct comedi_device *dev,
    515. 

  515. 				      struct comedi_subdevice *s,
    516. 

  516. 				      struct comedi_insn *insn,
    517. 

  517. 				      unsigned int *data)
    518. 

  518. {
    519. 

  519. 	uint msb, lsb, ccntrl, status;
    520. 

  520. 

  521. 	lsb = data[0] & 0x00FF;
    522. 

  522. 	msb = (data[0] & 0xFF00) >> 8;
    523. 

  523. 

  524. 	/* write lsb, then msb */
    525. 

  525. 	outw(lsb, dev->iobase + PCI171x_CNT0);
    526. 

  526. 	outw(msb, dev->iobase + PCI171x_CNT0);
    527. 

  527. 

  528. 	if (devpriv->cnt0_write_wait) {
    529. 

  529. 		/* wait for the new count to be loaded */
    530. 

  530. 		ccntrl = 0xE2;
    531. 

  531. 		do {
    532. 

  532. 			outw(ccntrl, dev->iobase + PCI171x_CNTCTRL);
    533. 

  533. 			status = inw(dev->iobase + PCI171x_CNT0) & 0xFF;
    534. 

  534. 		} while (status & 0x40);
    535. 

  535. 	}
    536. 

  536. 

  537. 	return insn->n;
    538. 

  538. }
    539. 

  539. 

  540. /*
    541. 

  541. ==============================================================================
    542. 

  542. */
    543. 

  543. static int pci171x_insn_counter_config(struct comedi_device *dev,
    544. 

  544. 				       struct comedi_subdevice *s,
    545. 

  545. 				       struct comedi_insn *insn,
    546. 

  546. 				       unsigned int *data)
    547. 

  547. {
    548. 

  548. #ifdef unused
    549. 

  549. 	/* This doesn't work like a normal Comedi counter config */
    550. 

  550. 	uint ccntrl = 0;
    551. 

  551. 

  552. 	devpriv->cnt0_write_wait = data[0] & 0x20;
    553. 

  553. 

  554. 	/* internal or external clock? */
    555. 

  555. 	if (!(data[0] & 0x10)) {	/* internal */
    556. 

  556. 		devpriv->CntrlReg &= ~Control_CNT0;
    557. 

  557. 	} else {
    558. 

  558. 		devpriv->CntrlReg |= Control_CNT0;
    559. 

  559. 	}
    560. 

  560. 	outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
    561. 

  561. 

  562. 	if (data[0] & 0x01)
    563. 

  563. 		ccntrl |= Counter_M0;
    564. 

  564. 	if (data[0] & 0x02)
    565. 

  565. 		ccntrl |= Counter_M1;
    566. 

  566. 	if (data[0] & 0x04)
    567. 

  567. 		ccntrl |= Counter_M2;
    568. 

  568. 	if (data[0] & 0x08)
    569. 

  569. 		ccntrl |= Counter_BCD;
    570. 

  570. 	ccntrl |= Counter_RW0;	/* set read/write mode */
    571. 

  571. 	ccntrl |= Counter_RW1;
    572. 

  572. 	outw(ccntrl, dev->iobase + PCI171x_CNTCTRL);
    573. 

  573. #endif
    574. 

  574. 

  575. 	return 1;
    576. 

  576. }
    577. 

  577. 

  578. /*
    579. 

  579. ==============================================================================
    580. 

  580. */
    581. 

  581. static int pci1720_insn_write_ao(struct comedi_device *dev,
    582. 

  582. 				 struct comedi_subdevice *s,
    583. 

  583. 				 struct comedi_insn *insn, unsigned int *data)
    584. 

  584. {
    585. 

  585. 	int n, rangereg, chan;
    586. 

  586. 

  587. 	chan = CR_CHAN(insn->chanspec);
    588. 

  588. 	rangereg = devpriv->da_ranges & (~(0x03 << (chan << 1)));
    589. 

  589. 	rangereg |= (CR_RANGE(insn->chanspec) << (chan << 1));
    590. 

  590. 	if (rangereg != devpriv->da_ranges) {
    591. 

  591. 		outb(rangereg, dev->iobase + PCI1720_RANGE);
    592. 

  592. 		devpriv->da_ranges = rangereg;
    593. 

  593. 	}
    594. 

  594. 

  595. 	for (n = 0; n < insn->n; n++) {
    596. 

  596. 		outw(data[n], dev->iobase + PCI1720_DA0 + (chan << 1));
    597. 

  597. 		outb(0, dev->iobase + PCI1720_SYNCOUT);	/*  update outputs */
    598. 

  598. 	}
    599. 

  599. 

  600. 	devpriv->ao_data[chan] = data[n];
    601. 

  601. 

  602. 	return n;
    603. 

  603. }
    604. 

  604. 

  605. /*
    606. 

  606. ==============================================================================
    607. 

  607. */
    608. 

  608. static void interrupt_pci1710_every_sample(void *d)
    609. 

  609. {
    610. 

  610. 	struct comedi_device *dev = d;
    611. 

  611. 	struct comedi_subdevice *s = dev->subdevices + 0;
    612. 

  612. 	int m;
    613. 

  613. #ifdef PCI171x_PARANOIDCHECK
    614. 

  614. 	short sampl;
    615. 

  615. #endif
    616. 

  616. 

  617. 	DPRINTK("adv_pci1710 EDBG: BGN: interrupt_pci1710_every_sample(...)\n");
    618. 

  618. 	m = inw(dev->iobase + PCI171x_STATUS);
    619. 

  619. 	if (m & Status_FE) {
    620. 

  620. 		printk("comedi%d: A/D FIFO empty (%4x)\n", dev->minor, m);
    621. 

  621. 		pci171x_ai_cancel(dev, s);
    622. 

  622. 		s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
    623. 

  623. 		comedi_event(dev, s);
    624. 

  624. 		return;
    625. 

  625. 	}
    626. 

  626. 	if (m & Status_FF) {
    627. 

  627. 		printk
    628. 

  628. 		    ("comedi%d: A/D FIFO Full status (Fatal Error!) (%4x)\n",
    629. 

  629. 		     dev->minor, m);
    630. 

  630. 		pci171x_ai_cancel(dev, s);
    631. 

  631. 		s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
    632. 

  632. 		comedi_event(dev, s);
    633. 

  633. 		return;
    634. 

  634. 	}
    635. 

  635. 

  636. 	outb(0, dev->iobase + PCI171x_CLRINT);	/*  clear our INT request */
    637. 

  637. 

  638. 	DPRINTK("FOR ");
    639. 

  639. 	for (; !(inw(dev->iobase + PCI171x_STATUS) & Status_FE);) {
    640. 

  640. #ifdef PCI171x_PARANOIDCHECK
    641. 

  641. 		sampl = inw(dev->iobase + PCI171x_AD_DATA);
    642. 

  642. 		DPRINTK("%04x:", sampl);
    643. 

  643. 		if (this_board->cardtype != TYPE_PCI1713)
    644. 

  644. 			if ((sampl & 0xf000) !=
    645. 

  645. 			    devpriv->act_chanlist[s->async->cur_chan]) {
    646. 

  646. 				printk
    647. 

  647. 				    ("comedi: A/D data dropout: received data from channel %d, expected %d!\n",
    648. 

  648. 				     (sampl & 0xf000) >> 12,
    649. 

  649. 				     (devpriv->
    650. 

  650. 				      act_chanlist[s->
    651. 

  651. 						   async->cur_chan] & 0xf000) >>
    652. 

  652. 				     12);
    653. 

  653. 				pci171x_ai_cancel(dev, s);
    654. 

  654. 				s->async->events |=
    655. 

  655. 				    COMEDI_CB_EOA | COMEDI_CB_ERROR;
    656. 

  656. 				comedi_event(dev, s);
    657. 

  657. 				return;
    658. 

  658. 			}
    659. 

  659. 		DPRINTK("%8d %2d %8d~", s->async->buf_int_ptr,
    660. 

  660. 			s->async->cur_chan, s->async->buf_int_count);
    661. 

  661. 		comedi_buf_put(s->async, sampl & 0x0fff);
    662. 

  662. #else
    663. 

  663. 		comedi_buf_put(s->async,
    664. 

  664. 			       inw(dev->iobase + PCI171x_AD_DATA) & 0x0fff);
    665. 

  665. #endif
    666. 

  666. 		++s->async->cur_chan;
    667. 

  667. 

  668. 		if (s->async->cur_chan >= devpriv->ai_n_chan)
    669. 

  669. 			s->async->cur_chan = 0;
    670. 

  670. 

  671. 

  672. 		if (s->async->cur_chan == 0) {	/*  one scan done */
    673. 

  673. 			devpriv->ai_act_scan++;
    674. 

  674. 			DPRINTK
    675. 

  675. 			    ("adv_pci1710 EDBG: EOS1 bic %d bip %d buc %d bup %d\n",
    676. 

  676. 			     s->async->buf_int_count, s->async->buf_int_ptr,
    677. 

  677. 			     s->async->buf_user_count, s->async->buf_user_ptr);
    678. 

  678. 			DPRINTK("adv_pci1710 EDBG: EOS2\n");
    679. 

  679. 			if ((!devpriv->neverending_ai) && (devpriv->ai_act_scan >= devpriv->ai_scans)) {	/*  all data sampled */
    680. 

  680. 				pci171x_ai_cancel(dev, s);
    681. 

  681. 				s->async->events |= COMEDI_CB_EOA;
    682. 

  682. 				comedi_event(dev, s);
    683. 

  683. 				return;
    684. 

  684. 			}
    685. 

  685. 		}
    686. 

  686. 	}
    687. 

  687. 

  688. 	outb(0, dev->iobase + PCI171x_CLRINT);	/*  clear our INT request */
    689. 

  689. 	DPRINTK("adv_pci1710 EDBG: END: interrupt_pci1710_every_sample(...)\n");
    690. 

  690. 

  691. 	comedi_event(dev, s);
    692. 

  692. }
    693. 

  693. 

  694. /*
    695. 

  695. ==============================================================================
    696. 

  696. */
    697. 

  697. static int move_block_from_fifo(struct comedi_device *dev,
    698. 

  698. 				struct comedi_subdevice *s, int n, int turn)
    699. 

  699. {
    700. 

  700. 	int i, j;
    701. 

  701. #ifdef PCI171x_PARANOIDCHECK
    702. 

  702. 	int sampl;
    703. 

  703. #endif
    704. 

  704. 	DPRINTK("adv_pci1710 EDBG: BGN: move_block_from_fifo(...,%d,%d)\n", n,
    705. 

  705. 		turn);
    706. 

  706. 	j = s->async->cur_chan;
    707. 

  707. 	for (i = 0; i < n; i++) {
    708. 

  708. #ifdef PCI171x_PARANOIDCHECK
    709. 

  709. 		sampl = inw(dev->iobase + PCI171x_AD_DATA);
    710. 

  710. 		if (this_board->cardtype != TYPE_PCI1713)
    711. 

  711. 			if ((sampl & 0xf000) != devpriv->act_chanlist[j]) {
    712. 

  712. 				printk
    713. 

  713. 				    ("comedi%d: A/D  FIFO data dropout: received data from channel %d, expected %d! (%d/%d/%d/%d/%d/%4x)\n",
    714. 

  714. 				     dev->minor, (sampl & 0xf000) >> 12,
    715. 

  715. 				     (devpriv->act_chanlist[j] & 0xf000) >> 12,
    716. 

  716. 				     i, j, devpriv->ai_act_scan, n, turn,
    717. 

  717. 				     sampl);
    718. 

  718. 				pci171x_ai_cancel(dev, s);
    719. 

  719. 				s->async->events |=
    720. 

  720. 				    COMEDI_CB_EOA | COMEDI_CB_ERROR;
    721. 

  721. 				comedi_event(dev, s);
    722. 

  722. 				return 1;
    723. 

  723. 			}
    724. 

  724. 		comedi_buf_put(s->async, sampl & 0x0fff);
    725. 

  725. #else
    726. 

  726. 		comedi_buf_put(s->async,
    727. 

  727. 			       inw(dev->iobase + PCI171x_AD_DATA) & 0x0fff);
    728. 

  728. #endif
    729. 

  729. 		j++;
    730. 

  730. 		if (j >= devpriv->ai_n_chan) {
    731. 

  731. 			j = 0;
    732. 

  732. 			devpriv->ai_act_scan++;
    733. 

  733. 		}
    734. 

  734. 	}
    735. 

  735. 	s->async->cur_chan = j;
    736. 

  736. 	DPRINTK("adv_pci1710 EDBG: END: move_block_from_fifo(...)\n");
    737. 

  737. 	return 0;
    738. 

  738. }
    739. 

  739. 

  740. /*
    741. 

  741. ==============================================================================
    742. 

  742. */
    743. 

  743. static void interrupt_pci1710_half_fifo(void *d)
    744. 

  744. {
    745. 

  745. 	struct comedi_device *dev = d;
    746. 

  746. 	struct comedi_subdevice *s = dev->subdevices + 0;
    747. 

  747. 	int m, samplesinbuf;
    748. 

  748. 

  749. 	DPRINTK("adv_pci1710 EDBG: BGN: interrupt_pci1710_half_fifo(...)\n");
    750. 

  750. 	m = inw(dev->iobase + PCI171x_STATUS);
    751. 

  751. 	if (!(m & Status_FH)) {
    752. 

  752. 		printk("comedi%d: A/D FIFO not half full! (%4x)\n",
    753. 

  753. 		       dev->minor, m);
    754. 

  754. 		pci171x_ai_cancel(dev, s);
    755. 

  755. 		s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
    756. 

  756. 		comedi_event(dev, s);
    757. 

  757. 		return;
    758. 

  758. 	}
    759. 

  759. 	if (m & Status_FF) {
    760. 

  760. 		printk
    761. 

  761. 		    ("comedi%d: A/D FIFO Full status (Fatal Error!) (%4x)\n",
    762. 

  762. 		     dev->minor, m);
    763. 

  763. 		pci171x_ai_cancel(dev, s);
    764. 

  764. 		s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
    765. 

  765. 		comedi_event(dev, s);
    766. 

  766. 		return;
    767. 

  767. 	}
    768. 

  768. 

  769. 	samplesinbuf = this_board->fifo_half_size;
    770. 

  770. 	if (samplesinbuf * sizeof(short) >= devpriv->ai_data_len) {
    771. 

  771. 		m = devpriv->ai_data_len / sizeof(short);
    772. 

  772. 		if (move_block_from_fifo(dev, s, m, 0))
    773. 

  773. 			return;
    774. 

  774. 		samplesinbuf -= m;
    775. 

  775. 	}
    776. 

  776. 

  777. 	if (samplesinbuf) {
    778. 

  778. 		if (move_block_from_fifo(dev, s, samplesinbuf, 1))
    779. 

  779. 			return;
    780. 

  780. 	}
    781. 

  781. 

  782. 	if (!devpriv->neverending_ai)
    783. 

  783. 		if (devpriv->ai_act_scan >= devpriv->ai_scans) { /* all data
    784. 

  784. 								    sampled */
    785. 

  785. 			pci171x_ai_cancel(dev, s);
    786. 

  786. 			s->async->events |= COMEDI_CB_EOA;
    787. 

  787. 			comedi_event(dev, s);
    788. 

  788. 			return;
    789. 

  789. 		}
    790. 

  790. 	outb(0, dev->iobase + PCI171x_CLRINT);	/*  clear our INT request */
    791. 

  791. 	DPRINTK("adv_pci1710 EDBG: END: interrupt_pci1710_half_fifo(...)\n");
    792. 

  792. 

  793. 	comedi_event(dev, s);
    794. 

  794. }
    795. 

  795. 

  796. /*
    797. 

  797. ==============================================================================
    798. 

  798. */
    799. 

  799. static irqreturn_t interrupt_service_pci1710(int irq, void *d)
    800. 

  800. {
    801. 

  801. 	struct comedi_device *dev = d;
    802. 

  802. 

  803. 	DPRINTK("adv_pci1710 EDBG: BGN: interrupt_service_pci1710(%d,...)\n",
    804. 

  804. 		irq);
    805. 

  805. 	if (!dev->attached)	/*  is device attached? */
    806. 

  806. 		return IRQ_NONE;	/*  no, exit */
    807. 

  807. 

  808. 	if (!(inw(dev->iobase + PCI171x_STATUS) & Status_IRQ))	/*  is this interrupt from our board? */
    809. 

  809. 		return IRQ_NONE;	/*  no, exit */
    810. 

  810. 

  811. 	DPRINTK("adv_pci1710 EDBG: interrupt_service_pci1710() ST: %4x\n",
    812. 

  812. 		inw(dev->iobase + PCI171x_STATUS));
    813. 

  813. 

  814. 	if (devpriv->ai_et) {	/*  Switch from initial TRIG_EXT to TRIG_xxx. */
    815. 

  815. 		devpriv->ai_et = 0;
    816. 

  816. 		devpriv->CntrlReg &= Control_CNT0;
    817. 

  817. 		devpriv->CntrlReg |= Control_SW;	/*  set software trigger */
    818. 

  818. 		outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
    819. 

  819. 		devpriv->CntrlReg = devpriv->ai_et_CntrlReg;
    820. 

  820. 		outb(0, dev->iobase + PCI171x_CLRFIFO);
    821. 

  821. 		outb(0, dev->iobase + PCI171x_CLRINT);
    822. 

  822. 		outw(devpriv->ai_et_MuxVal, dev->iobase + PCI171x_MUX);
    823. 

  823. 		outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
    824. 

  824. 		/*  start pacer */
    825. 

  825. 		start_pacer(dev, 1, devpriv->ai_et_div1, devpriv->ai_et_div2);
    826. 

  826. 		return IRQ_HANDLED;
    827. 

  827. 	}
    828. 

  828. 	if (devpriv->ai_eos) {	/*  We use FIFO half full INT or not? */
    829. 

  829. 		interrupt_pci1710_every_sample(d);
    830. 

  830. 	} else {
    831. 

  831. 		interrupt_pci1710_half_fifo(d);
    832. 

  832. 	}
    833. 

  833. 	DPRINTK("adv_pci1710 EDBG: END: interrupt_service_pci1710(...)\n");
    834. 

  834. 	return IRQ_HANDLED;
    835. 

  835. }
    836. 

  836. 

  837. /*
    838. 

  838. ==============================================================================
    839. 

  839. */
    840. 

  840. static int pci171x_ai_docmd_and_mode(int mode, struct comedi_device *dev,
    841. 

  841. 				     struct comedi_subdevice *s)
    842. 

  842. {
    843. 

  843. 	unsigned int divisor1 = 0, divisor2 = 0;
    844. 

  844. 	unsigned int seglen;
    845. 

  845. 

  846. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_ai_docmd_and_mode(%d,...)\n",
    847. 

  847. 		mode);
    848. 

  848. 	start_pacer(dev, -1, 0, 0);	/*  stop pacer */
    849. 

  849. 

  850. 	seglen = check_channel_list(dev, s, devpriv->ai_chanlist,
    851. 

  851. 				    devpriv->ai_n_chan);
    852. 

  852. 	if (seglen < 1)
    853. 

  853. 		return -EINVAL;
    854. 

  854. 	setup_channel_list(dev, s, devpriv->ai_chanlist,
    855. 

  855. 			   devpriv->ai_n_chan, seglen);
    856. 

  856. 

  857. 	outb(0, dev->iobase + PCI171x_CLRFIFO);
    858. 

  858. 	outb(0, dev->iobase + PCI171x_CLRINT);
    859. 

  859. 

  860. 	devpriv->ai_do = mode;
    861. 

  861. 

  862. 	devpriv->ai_act_scan = 0;
    863. 

  863. 	s->async->cur_chan = 0;
    864. 

  864. 	devpriv->ai_buf_ptr = 0;
    865. 

  865. 	devpriv->neverending_ai = 0;
    866. 

  866. 

  867. 	devpriv->CntrlReg &= Control_CNT0;
    868. 

  868. 	if ((devpriv->ai_flags & TRIG_WAKE_EOS)) {	/*  don't we want wake up every scan?            devpriv->ai_eos=1; */
    869. 

  869. 		devpriv->ai_eos = 1;
    870. 

  870. 	} else {
    871. 

  871. 		devpriv->CntrlReg |= Control_ONEFH;
    872. 

  872. 		devpriv->ai_eos = 0;
    873. 

  873. 	}
    874. 

  874. 

  875. 	if ((devpriv->ai_scans == 0) || (devpriv->ai_scans == -1))
    876. 

  876. 		devpriv->neverending_ai = 1;
    877. 

  877. 	/* well, user want neverending */
    878. 

  878. 	else
    879. 

  879. 		devpriv->neverending_ai = 0;
    880. 

  880. 

  881. 	switch (mode) {
    882. 

  882. 	case 1:
    883. 

  883. 	case 2:
    884. 

  884. 		if (devpriv->ai_timer1 < this_board->ai_ns_min)
    885. 

  885. 			devpriv->ai_timer1 = this_board->ai_ns_min;
    886. 

  886. 		devpriv->CntrlReg |= Control_PACER | Control_IRQEN;
    887. 

  887. 		if (mode == 2) {
    888. 

  888. 			devpriv->ai_et_CntrlReg = devpriv->CntrlReg;
    889. 

  889. 			devpriv->CntrlReg &=
    890. 

  890. 			    ~(Control_PACER | Control_ONEFH | Control_GATE);
    891. 

  891. 			devpriv->CntrlReg |= Control_EXT;
    892. 

  892. 			devpriv->ai_et = 1;
    893. 

  893. 		} else {
    894. 

  894. 			devpriv->ai_et = 0;
    895. 

  895. 		}
    896. 

  896. 		i8253_cascade_ns_to_timer(devpriv->i8254_osc_base, &divisor1,
    897. 

  897. 					  &divisor2, &devpriv->ai_timer1,
    898. 

  898. 					  devpriv->ai_flags & TRIG_ROUND_MASK);
    899. 

  899. 		DPRINTK
    900. 

  900. 		    ("adv_pci1710 EDBG: OSC base=%u div1=%u div2=%u timer=%u\n",
    901. 

  901. 		     devpriv->i8254_osc_base, divisor1, divisor2,
    902. 

  902. 		     devpriv->ai_timer1);
    903. 

  903. 		outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
    904. 

  904. 		if (mode != 2) {
    905. 

  905. 			/*  start pacer */
    906. 

  906. 			start_pacer(dev, mode, divisor1, divisor2);
    907. 

  907. 		} else {
    908. 

  908. 			devpriv->ai_et_div1 = divisor1;
    909. 

  909. 			devpriv->ai_et_div2 = divisor2;
    910. 

  910. 		}
    911. 

  911. 		break;
    912. 

  912. 	case 3:
    913. 

  913. 		devpriv->CntrlReg |= Control_EXT | Control_IRQEN;
    914. 

  914. 		outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
    915. 

  915. 		break;
    916. 

  916. 	}
    917. 

  917. 

  918. 	DPRINTK("adv_pci1710 EDBG: END: pci171x_ai_docmd_and_mode(...)\n");
    919. 

  919. 	return 0;
    920. 

  920. }
    921. 

  921. 

  922. #ifdef PCI171X_EXTDEBUG
    923. 

  923. /*
    924. 

  924. ==============================================================================
    925. 

  925. */
    926. 

  926. static void pci171x_cmdtest_out(int e, struct comedi_cmd *cmd)
    927. 

  927. {
    928. 

  928. 	printk("adv_pci1710 e=%d startsrc=%x scansrc=%x convsrc=%x\n", e,
    929. 

  929. 	       cmd->start_src, cmd->scan_begin_src, cmd->convert_src);
    930. 

  930. 	printk("adv_pci1710 e=%d startarg=%d scanarg=%d convarg=%d\n", e,
    931. 

  931. 	       cmd->start_arg, cmd->scan_begin_arg, cmd->convert_arg);
    932. 

  932. 	printk("adv_pci1710 e=%d stopsrc=%x scanend=%x\n", e, cmd->stop_src,
    933. 

  933. 	       cmd->scan_end_src);
    934. 

  934. 	printk("adv_pci1710 e=%d stoparg=%d scanendarg=%d chanlistlen=%d\n",
    935. 

  935. 	       e, cmd->stop_arg, cmd->scan_end_arg, cmd->chanlist_len);
    936. 

  936. }
    937. 

  937. #endif
    938. 

  938. 

  939. /*
    940. 

  940. ==============================================================================
    941. 

  941. */
    942. 

  942. static int pci171x_ai_cmdtest(struct comedi_device *dev,
    943. 

  943. 			      struct comedi_subdevice *s,
    944. 

  944. 			      struct comedi_cmd *cmd)
    945. 

  945. {
    946. 

  946. 	int err = 0;
    947. 

  947. 	int tmp;
    948. 

  948. 	unsigned int divisor1 = 0, divisor2 = 0;
    949. 

  949. 

  950. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_ai_cmdtest(...)\n");
    951. 

  951. #ifdef PCI171X_EXTDEBUG
    952. 

  952. 	pci171x_cmdtest_out(-1, cmd);
    953. 

  953. #endif
    954. 

  954. 	/* step 1: make sure trigger sources are trivially valid */
    955. 

  955. 

  956. 	tmp = cmd->start_src;
    957. 

  957. 	cmd->start_src &= TRIG_NOW | TRIG_EXT;
    958. 

  958. 	if (!cmd->start_src || tmp != cmd->start_src)
    959. 

  959. 		err++;
    960. 

  960. 

  961. 	tmp = cmd->scan_begin_src;
    962. 

  962. 	cmd->scan_begin_src &= TRIG_FOLLOW;
    963. 

  963. 	if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
    964. 

  964. 		err++;
    965. 

  965. 

  966. 	tmp = cmd->convert_src;
    967. 

  967. 	cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
    968. 

  968. 	if (!cmd->convert_src || tmp != cmd->convert_src)
    969. 

  969. 		err++;
    970. 

  970. 

  971. 	tmp = cmd->scan_end_src;
    972. 

  972. 	cmd->scan_end_src &= TRIG_COUNT;
    973. 

  973. 	if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
    974. 

  974. 		err++;
    975. 

  975. 

  976. 	tmp = cmd->stop_src;
    977. 

  977. 	cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
    978. 

  978. 	if (!cmd->stop_src || tmp != cmd->stop_src)
    979. 

  979. 		err++;
    980. 

  980. 

  981. 	if (err) {
    982. 

  982. #ifdef PCI171X_EXTDEBUG
    983. 

  983. 		pci171x_cmdtest_out(1, cmd);
    984. 

  984. #endif
    985. 

  985. 		DPRINTK
    986. 

  986. 		    ("adv_pci1710 EDBG: BGN: pci171x_ai_cmdtest(...) err=%d ret=1\n",
    987. 

  987. 		     err);
    988. 

  988. 		return 1;
    989. 

  989. 	}
    990. 

  990. 

  991. 	/* step 2: make sure trigger sources are unique and mutually compatible */
    992. 

  992. 

  993. 	if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) {
    994. 

  994. 		cmd->start_src = TRIG_NOW;
    995. 

  995. 		err++;
    996. 

  996. 	}
    997. 

  997. 

  998. 	if (cmd->scan_begin_src != TRIG_FOLLOW) {
    999. 

  999. 		cmd->scan_begin_src = TRIG_FOLLOW;
    1000. 

  1000. 		err++;
    1001. 

  1001. 	}
    1002. 

  1002. 

  1003. 	if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
    1004. 

  1004. 		err++;
    1005. 

  1005. 

  1006. 	if (cmd->scan_end_src != TRIG_COUNT) {
    1007. 

  1007. 		cmd->scan_end_src = TRIG_COUNT;
    1008. 

  1008. 		err++;
    1009. 

  1009. 	}
    1010. 

  1010. 

  1011. 	if (cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_COUNT)
    1012. 

  1012. 		err++;
    1013. 

  1013. 

  1014. 	if (err) {
    1015. 

  1015. #ifdef PCI171X_EXTDEBUG
    1016. 

  1016. 		pci171x_cmdtest_out(2, cmd);
    1017. 

  1017. #endif
    1018. 

  1018. 		DPRINTK
    1019. 

  1019. 		    ("adv_pci1710 EDBG: BGN: pci171x_ai_cmdtest(...) err=%d ret=2\n",
    1020. 

  1020. 		     err);
    1021. 

  1021. 		return 2;
    1022. 

  1022. 	}
    1023. 

  1023. 

  1024. 	/* step 3: make sure arguments are trivially compatible */
    1025. 

  1025. 

  1026. 	if (cmd->start_arg != 0) {
    1027. 

  1027. 		cmd->start_arg = 0;
    1028. 

  1028. 		err++;
    1029. 

  1029. 	}
    1030. 

  1030. 

  1031. 	if (cmd->scan_begin_arg != 0) {
    1032. 

  1032. 		cmd->scan_begin_arg = 0;
    1033. 

  1033. 		err++;
    1034. 

  1034. 	}
    1035. 

  1035. 

  1036. 	if (cmd->convert_src == TRIG_TIMER) {
    1037. 

  1037. 		if (cmd->convert_arg < this_board->ai_ns_min) {
    1038. 

  1038. 			cmd->convert_arg = this_board->ai_ns_min;
    1039. 

  1039. 			err++;
    1040. 

  1040. 		}
    1041. 

  1041. 	} else {		/* TRIG_FOLLOW */
    1042. 

  1042. 		if (cmd->convert_arg != 0) {
    1043. 

  1043. 			cmd->convert_arg = 0;
    1044. 

  1044. 			err++;
    1045. 

  1045. 		}
    1046. 

  1046. 	}
    1047. 

  1047. 

  1048. 	if (cmd->scan_end_arg != cmd->chanlist_len) {
    1049. 

  1049. 		cmd->scan_end_arg = cmd->chanlist_len;
    1050. 

  1050. 		err++;
    1051. 

  1051. 	}
    1052. 

  1052. 	if (cmd->stop_src == TRIG_COUNT) {
    1053. 

  1053. 		if (!cmd->stop_arg) {
    1054. 

  1054. 			cmd->stop_arg = 1;
    1055. 

  1055. 			err++;
    1056. 

  1056. 		}
    1057. 

  1057. 	} else {		/* TRIG_NONE */
    1058. 

  1058. 		if (cmd->stop_arg != 0) {
    1059. 

  1059. 			cmd->stop_arg = 0;
    1060. 

  1060. 			err++;
    1061. 

  1061. 		}
    1062. 

  1062. 	}
    1063. 

  1063. 

  1064. 	if (err) {
    1065. 

  1065. #ifdef PCI171X_EXTDEBUG
    1066. 

  1066. 		pci171x_cmdtest_out(3, cmd);
    1067. 

  1067. #endif
    1068. 

  1068. 		DPRINTK
    1069. 

  1069. 		    ("adv_pci1710 EDBG: BGN: pci171x_ai_cmdtest(...) err=%d ret=3\n",
    1070. 

  1070. 		     err);
    1071. 

  1071. 		return 3;
    1072. 

  1072. 	}
    1073. 

  1073. 

  1074. 	/* step 4: fix up any arguments */
    1075. 

  1075. 

  1076. 	if (cmd->convert_src == TRIG_TIMER) {
    1077. 

  1077. 		tmp = cmd->convert_arg;
    1078. 

  1078. 		i8253_cascade_ns_to_timer(devpriv->i8254_osc_base, &divisor1,
    1079. 

  1079. 					  &divisor2, &cmd->convert_arg,
    1080. 

  1080. 					  cmd->flags & TRIG_ROUND_MASK);
    1081. 

  1081. 		if (cmd->convert_arg < this_board->ai_ns_min)
    1082. 

  1082. 			cmd->convert_arg = this_board->ai_ns_min;
    1083. 

  1083. 		if (tmp != cmd->convert_arg)
    1084. 

  1084. 			err++;
    1085. 

  1085. 	}
    1086. 

  1086. 

  1087. 	if (err) {
    1088. 

  1088. 		DPRINTK
    1089. 

  1089. 		    ("adv_pci1710 EDBG: BGN: pci171x_ai_cmdtest(...) err=%d ret=4\n",
    1090. 

  1090. 		     err);
    1091. 

  1091. 		return 4;
    1092. 

  1092. 	}
    1093. 

  1093. 

  1094. 	/* step 5: complain about special chanlist considerations */
    1095. 

  1095. 

  1096. 	if (cmd->chanlist) {
    1097. 

  1097. 		if (!check_channel_list(dev, s, cmd->chanlist,
    1098. 

  1098. 					cmd->chanlist_len))
    1099. 

  1099. 			return 5;	/*  incorrect channels list */
    1100. 

  1100. 	}
    1101. 

  1101. 

  1102. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_ai_cmdtest(...) ret=0\n");
    1103. 

  1103. 	return 0;
    1104. 

  1104. }
    1105. 

  1105. 

  1106. /*
    1107. 

  1107. ==============================================================================
    1108. 

  1108. */
    1109. 

  1109. static int pci171x_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
    1110. 

  1110. {
    1111. 

  1111. 	struct comedi_cmd *cmd = &s->async->cmd;
    1112. 

  1112. 

  1113. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_ai_cmd(...)\n");
    1114. 

  1114. 	devpriv->ai_n_chan = cmd->chanlist_len;
    1115. 

  1115. 	devpriv->ai_chanlist = cmd->chanlist;
    1116. 

  1116. 	devpriv->ai_flags = cmd->flags;
    1117. 

  1117. 	devpriv->ai_data_len = s->async->prealloc_bufsz;
    1118. 

  1118. 	devpriv->ai_data = s->async->prealloc_buf;
    1119. 

  1119. 	devpriv->ai_timer1 = 0;
    1120. 

  1120. 	devpriv->ai_timer2 = 0;
    1121. 

  1121. 

  1122. 	if (cmd->stop_src == TRIG_COUNT)
    1123. 

  1123. 		devpriv->ai_scans = cmd->stop_arg;
    1124. 

  1124. 	else
    1125. 

  1125. 		devpriv->ai_scans = 0;
    1126. 

  1126. 

  1127. 

  1128. 	if (cmd->scan_begin_src == TRIG_FOLLOW) {	/*  mode 1, 2, 3 */
    1129. 

  1129. 		if (cmd->convert_src == TRIG_TIMER) {	/*  mode 1 and 2 */
    1130. 

  1130. 			devpriv->ai_timer1 = cmd->convert_arg;
    1131. 

  1131. 			return pci171x_ai_docmd_and_mode(cmd->start_src ==
    1132. 

  1132. 							 TRIG_EXT ? 2 : 1, dev,
    1133. 

  1133. 							 s);
    1134. 

  1134. 		}
    1135. 

  1135. 		if (cmd->convert_src == TRIG_EXT) {	/*  mode 3 */
    1136. 

  1136. 			return pci171x_ai_docmd_and_mode(3, dev, s);
    1137. 

  1137. 		}
    1138. 

  1138. 	}
    1139. 

  1139. 

  1140. 	return -1;
    1141. 

  1141. }
    1142. 

  1142. 

  1143. /*
    1144. 

  1144. ==============================================================================
    1145. 

  1145.  Check if channel list from user is builded correctly
    1146. 

  1146.  If it's ok, then program scan/gain logic.
    1147. 

  1147.  This works for all cards.
    1148. 

  1148. */
    1149. 

  1149. static int check_channel_list(struct comedi_device *dev,
    1150. 

  1150. 			      struct comedi_subdevice *s,
    1151. 

  1151. 			      unsigned int *chanlist, unsigned int n_chan)
    1152. 

  1152. {
    1153. 

  1153. 	unsigned int chansegment[32];
    1154. 

  1154. 	unsigned int i, nowmustbechan, seglen, segpos;
    1155. 

  1155. 

  1156. 	DPRINTK("adv_pci1710 EDBG:  check_channel_list(...,%d)\n", n_chan);
    1157. 

  1157. 	/* correct channel and range number check itself comedi/range.c */
    1158. 

  1158. 	if (n_chan < 1) {
    1159. 

  1159. 		comedi_error(dev, "range/channel list is empty!");
    1160. 

  1160. 		return 0;
    1161. 

  1161. 	}
    1162. 

  1162. 

  1163. 	if (n_chan > 1) {
    1164. 

  1164. 		chansegment[0] = chanlist[0];	/*  first channel is every time ok */
    1165. 

  1165. 		for (i = 1, seglen = 1; i < n_chan; i++, seglen++) {	/*  build part of chanlist */
    1166. 

  1166. 			/*  printk("%d. %d %d\n",i,CR_CHAN(chanlist[i]),CR_RANGE(chanlist[i])); */
    1167. 

  1167. 			if (chanlist[0] == chanlist[i])
    1168. 

  1168. 				break;	/*  we detect loop, this must by finish */
    1169. 

  1169. 			if (CR_CHAN(chanlist[i]) & 1)	/*  odd channel cann't by differencial */
    1170. 

  1170. 				if (CR_AREF(chanlist[i]) == AREF_DIFF) {
    1171. 

  1171. 					comedi_error(dev,
    1172. 

  1172. 						     "Odd channel can't be differential input!\n");
    1173. 

  1173. 					return 0;
    1174. 

  1174. 				}
    1175. 

  1175. 			nowmustbechan =
    1176. 

  1176. 			    (CR_CHAN(chansegment[i - 1]) + 1) % s->n_chan;
    1177. 

  1177. 			if (CR_AREF(chansegment[i - 1]) == AREF_DIFF)
    1178. 

  1178. 				nowmustbechan = (nowmustbechan + 1) % s->n_chan;
    1179. 

  1179. 			if (nowmustbechan != CR_CHAN(chanlist[i])) {	/*  channel list isn't continuous :-( */
    1180. 

  1180. 				printk
    1181. 

  1181. 				    ("channel list must be continuous! chanlist[%i]=%d but must be %d or %d!\n",
    1182. 

  1182. 				     i, CR_CHAN(chanlist[i]), nowmustbechan,
    1183. 

  1183. 				     CR_CHAN(chanlist[0]));
    1184. 

  1184. 				return 0;
    1185. 

  1185. 			}
    1186. 

  1186. 			chansegment[i] = chanlist[i];	/*  well, this is next correct channel in list */
    1187. 

  1187. 		}
    1188. 

  1188. 

  1189. 		for (i = 0, segpos = 0; i < n_chan; i++) {	/*  check whole chanlist */
    1190. 

  1190. 			/* printk("%d %d=%d %d\n",CR_CHAN(chansegment[i%seglen]),CR_RANGE(chansegment[i%seglen]),CR_CHAN(chanlist[i]),CR_RANGE(chanlist[i])); */
    1191. 

  1191. 			if (chanlist[i] != chansegment[i % seglen]) {
    1192. 

  1192. 				printk
    1193. 

  1193. 				    ("bad channel, reference or range number! chanlist[%i]=%d,%d,%d and not %d,%d,%d!\n",
    1194. 

  1194. 				     i, CR_CHAN(chansegment[i]),
    1195. 

  1195. 				     CR_RANGE(chansegment[i]),
    1196. 

  1196. 				     CR_AREF(chansegment[i]),
    1197. 

  1197. 				     CR_CHAN(chanlist[i % seglen]),
    1198. 

  1198. 				     CR_RANGE(chanlist[i % seglen]),
    1199. 

  1199. 				     CR_AREF(chansegment[i % seglen]));
    1200. 

  1200. 				return 0;	/*  chan/gain list is strange */
    1201. 

  1201. 			}
    1202. 

  1202. 		}
    1203. 

  1203. 	} else {
    1204. 

  1204. 		seglen = 1;
    1205. 

  1205. 	}
    1206. 

  1206. 	return seglen;
    1207. 

  1207. }
    1208. 

  1208. 

  1209. static void setup_channel_list(struct comedi_device *dev,
    1210. 

  1210. 			       struct comedi_subdevice *s,
    1211. 

  1211. 			       unsigned int *chanlist, unsigned int n_chan,
    1212. 

  1212. 			       unsigned int seglen)
    1213. 

  1213. {
    1214. 

  1214. 	unsigned int i, range, chanprog;
    1215. 

  1215. 

  1216. 	DPRINTK("adv_pci1710 EDBG:  setup_channel_list(...,%d,%d)\n", n_chan,
    1217. 

  1217. 		seglen);
    1218. 

  1218. 	devpriv->act_chanlist_len = seglen;
    1219. 

  1219. 	devpriv->act_chanlist_pos = 0;
    1220. 

  1220. 

  1221. 	DPRINTK("SegLen: %d\n", seglen);
    1222. 

  1222. 	for (i = 0; i < seglen; i++) {	/*  store range list to card */
    1223. 

  1223. 		chanprog = muxonechan[CR_CHAN(chanlist[i])];
    1224. 

  1224. 		outw(chanprog, dev->iobase + PCI171x_MUX);	/* select channel */
    1225. 

  1225. 		range = this_board->rangecode_ai[CR_RANGE(chanlist[i])];
    1226. 

  1226. 		if (CR_AREF(chanlist[i]) == AREF_DIFF)
    1227. 

  1227. 			range |= 0x0020;
    1228. 

  1228. 		outw(range, dev->iobase + PCI171x_RANGE);	/* select gain */
    1229. 

  1229. #ifdef PCI171x_PARANOIDCHECK
    1230. 

  1230. 		devpriv->act_chanlist[i] =
    1231. 

  1231. 		    (CR_CHAN(chanlist[i]) << 12) & 0xf000;
    1232. 

  1232. #endif
    1233. 

  1233. 		DPRINTK("GS: %2d. [%4x]=%4x %4x\n", i, chanprog, range,
    1234. 

  1234. 			devpriv->act_chanlist[i]);
    1235. 

  1235. 	}
    1236. 

  1236. #ifdef PCI171x_PARANOIDCHECK
    1237. 

  1237. 	for ( ; i < n_chan; i++) { /* store remainder of channel list */
    1238. 

  1238. 		devpriv->act_chanlist[i] =
    1239. 

  1239. 		    (CR_CHAN(chanlist[i]) << 12) & 0xf000;
    1240. 

  1240. 	}
    1241. 

  1241. #endif
    1242. 

  1242. 

  1243. 	devpriv->ai_et_MuxVal =
    1244. 

  1244. 	    CR_CHAN(chanlist[0]) | (CR_CHAN(chanlist[seglen - 1]) << 8);
    1245. 

  1245. 	outw(devpriv->ai_et_MuxVal, dev->iobase + PCI171x_MUX);	/* select channel interval to scan */
    1246. 

  1246. 	DPRINTK("MUX: %4x L%4x.H%4x\n",
    1247. 

  1247. 		CR_CHAN(chanlist[0]) | (CR_CHAN(chanlist[seglen - 1]) << 8),
    1248. 

  1248. 		CR_CHAN(chanlist[0]), CR_CHAN(chanlist[seglen - 1]));
    1249. 

  1249. }
    1250. 

  1250. 

  1251. /*
    1252. 

  1252. ==============================================================================
    1253. 

  1253. */
    1254. 

  1254. static void start_pacer(struct comedi_device *dev, int mode,
    1255. 

  1255. 			unsigned int divisor1, unsigned int divisor2)
    1256. 

  1256. {
    1257. 

  1257. 	DPRINTK("adv_pci1710 EDBG: BGN: start_pacer(%d,%u,%u)\n", mode,
    1258. 

  1258. 		divisor1, divisor2);
    1259. 

  1259. 	outw(0xb4, dev->iobase + PCI171x_CNTCTRL);
    1260. 

  1260. 	outw(0x74, dev->iobase + PCI171x_CNTCTRL);
    1261. 

  1261. 

  1262. 	if (mode == 1) {
    1263. 

  1263. 		outw(divisor2 & 0xff, dev->iobase + PCI171x_CNT2);
    1264. 

  1264. 		outw((divisor2 >> 8) & 0xff, dev->iobase + PCI171x_CNT2);
    1265. 

  1265. 		outw(divisor1 & 0xff, dev->iobase + PCI171x_CNT1);
    1266. 

  1266. 		outw((divisor1 >> 8) & 0xff, dev->iobase + PCI171x_CNT1);
    1267. 

  1267. 	}
    1268. 

  1268. 	DPRINTK("adv_pci1710 EDBG: END: start_pacer(...)\n");
    1269. 

  1269. }
    1270. 

  1270. 

  1271. /*
    1272. 

  1272. ==============================================================================
    1273. 

  1273. */
    1274. 

  1274. static int pci171x_ai_cancel(struct comedi_device *dev,
    1275. 

  1275. 			     struct comedi_subdevice *s)
    1276. 

  1276. {
    1277. 

  1277. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_ai_cancel(...)\n");
    1278. 

  1278. 

  1279. 	switch (this_board->cardtype) {
    1280. 

  1280. 	default:
    1281. 

  1281. 		devpriv->CntrlReg &= Control_CNT0;
    1282. 

  1282. 		devpriv->CntrlReg |= Control_SW;
    1283. 

  1283. 

  1284. 		outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);	/*  reset any operations */
    1285. 

  1285. 		start_pacer(dev, -1, 0, 0);
    1286. 

  1286. 		outb(0, dev->iobase + PCI171x_CLRFIFO);
    1287. 

  1287. 		outb(0, dev->iobase + PCI171x_CLRINT);
    1288. 

  1288. 		break;
    1289. 

  1289. 	}
    1290. 

  1290. 

  1291. 	devpriv->ai_do = 0;
    1292. 

  1292. 	devpriv->ai_act_scan = 0;
    1293. 

  1293. 	s->async->cur_chan = 0;
    1294. 

  1294. 	devpriv->ai_buf_ptr = 0;
    1295. 

  1295. 	devpriv->neverending_ai = 0;
    1296. 

  1296. 

  1297. 	DPRINTK("adv_pci1710 EDBG: END: pci171x_ai_cancel(...)\n");
    1298. 

  1298. 	return 0;
    1299. 

  1299. }
    1300. 

  1300. 

  1301. /*
    1302. 

  1302. ==============================================================================
    1303. 

  1303. */
    1304. 

  1304. static int pci171x_reset(struct comedi_device *dev)
    1305. 

  1305. {
    1306. 

  1306. 	DPRINTK("adv_pci1710 EDBG: BGN: pci171x_reset(...)\n");
    1307. 

  1307. 	outw(0x30, dev->iobase + PCI171x_CNTCTRL);
    1308. 

  1308. 	devpriv->CntrlReg = Control_SW | Control_CNT0;	/*  Software trigger, CNT0=external */
    1309. 

  1309. 	outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);	/*  reset any operations */
    1310. 

  1310. 	outb(0, dev->iobase + PCI171x_CLRFIFO);	/*  clear FIFO */
    1311. 

  1311. 	outb(0, dev->iobase + PCI171x_CLRINT);	/*  clear INT request */
    1312. 

  1312. 	start_pacer(dev, -1, 0, 0);	/*  stop 8254 */
    1313. 

  1313. 	devpriv->da_ranges = 0;
    1314. 

  1314. 	if (this_board->n_aochan) {
    1315. 

  1315. 		outb(devpriv->da_ranges, dev->iobase + PCI171x_DAREF);	/*  set DACs to 0..5V */
    1316. 

  1316. 		outw(0, dev->iobase + PCI171x_DA1);	/*  set DA outputs to 0V */
    1317. 

  1317. 		devpriv->ao_data[0] = 0x0000;
    1318. 

  1318. 		if (this_board->n_aochan > 1) {
    1319. 

  1319. 			outw(0, dev->iobase + PCI171x_DA2);
    1320. 

  1320. 			devpriv->ao_data[1] = 0x0000;
    1321. 

  1321. 		}
    1322. 

  1322. 	}
    1323. 

  1323. 	outw(0, dev->iobase + PCI171x_DO);	/*  digital outputs to 0 */
    1324. 

  1324. 	outb(0, dev->iobase + PCI171x_CLRFIFO);	/*  clear FIFO */
    1325. 

  1325. 	outb(0, dev->iobase + PCI171x_CLRINT);	/*  clear INT request */
    1326. 

  1326. 

  1327. 	DPRINTK("adv_pci1710 EDBG: END: pci171x_reset(...)\n");
    1328. 

  1328. 	return 0;
    1329. 

  1329. }
    1330. 

  1330. 

  1331. /*
    1332. 

  1332. ==============================================================================
    1333. 

  1333. */
    1334. 

  1334. static int pci1720_reset(struct comedi_device *dev)
    1335. 

  1335. {
    1336. 

  1336. 	DPRINTK("adv_pci1710 EDBG: BGN: pci1720_reset(...)\n");
    1337. 

  1337. 	outb(Syncont_SC0, dev->iobase + PCI1720_SYNCONT);	/*  set synchronous output mode */
    1338. 

  1338. 	devpriv->da_ranges = 0xAA;
    1339. 

  1339. 	outb(devpriv->da_ranges, dev->iobase + PCI1720_RANGE);	/*  set all ranges to +/-5V */
    1340. 

  1340. 	outw(0x0800, dev->iobase + PCI1720_DA0);	/*  set outputs to 0V */
    1341. 

  1341. 	outw(0x0800, dev->iobase + PCI1720_DA1);
    1342. 

  1342. 	outw(0x0800, dev->iobase + PCI1720_DA2);
    1343. 

  1343. 	outw(0x0800, dev->iobase + PCI1720_DA3);
    1344. 

  1344. 	outb(0, dev->iobase + PCI1720_SYNCOUT);	/*  update outputs */
    1345. 

  1345. 	devpriv->ao_data[0] = 0x0800;
    1346. 

  1346. 	devpriv->ao_data[1] = 0x0800;
    1347. 

  1347. 	devpriv->ao_data[2] = 0x0800;
    1348. 

  1348. 	devpriv->ao_data[3] = 0x0800;
    1349. 

  1349. 	DPRINTK("adv_pci1710 EDBG: END: pci1720_reset(...)\n");
    1350. 

  1350. 	return 0;
    1351. 

  1351. }
    1352. 

  1352. 

  1353. /*
    1354. 

  1354. ==============================================================================
    1355. 

  1355. */
    1356. 

  1356. static int pci1710_reset(struct comedi_device *dev)
    1357. 

  1357. {
    1358. 

  1358. 	DPRINTK("adv_pci1710 EDBG: BGN: pci1710_reset(...)\n");
    1359. 

  1359. 	switch (this_board->cardtype) {
    1360. 

  1360. 	case TYPE_PCI1720:
    1361. 

  1361. 		return pci1720_reset(dev);
    1362. 

  1362. 	default:
    1363. 

  1363. 		return pci171x_reset(dev);
    1364. 

  1364. 	}
    1365. 

  1365. 	DPRINTK("adv_pci1710 EDBG: END: pci1710_reset(...)\n");
    1366. 

  1366. }
    1367. 

  1367. 

  1368. /*
    1369. 

  1369. ==============================================================================
    1370. 

  1370. */
    1371. 

  1371. static int pci1710_attach(struct comedi_device *dev,
    1372. 

  1372. 			  struct comedi_devconfig *it)
    1373. 

  1373. {
    1374. 

  1374. 	struct comedi_subdevice *s;
    1375. 

  1375. 	int ret, subdev, n_subdevices;
    1376. 

  1376. 	unsigned int irq;
    1377. 

  1377. 	unsigned long iobase;
    1378. 

  1378. 	struct pci_dev *pcidev;
    1379. 

  1379. 	int opt_bus, opt_slot;
    1380. 

  1380. 	const char *errstr;
    1381. 

  1381. 	unsigned char pci_bus, pci_slot, pci_func;
    1382. 

  1382. 	int i;
    1383. 

  1383. 	int board_index;
    1384. 

  1384. 

  1385. 	printk("comedi%d: adv_pci1710: ", dev->minor);
    1386. 

  1386. 

  1387. 	opt_bus = it->options[0];
    1388. 

  1388. 	opt_slot = it->options[1];
    1389. 

  1389. 

  1390. 	ret = alloc_private(dev, sizeof(struct pci1710_private));
    1391. 

  1391. 	if (ret < 0) {
    1392. 

  1392. 		printk(" - Allocation failed!\n");
    1393. 

  1393. 		return -ENOMEM;
    1394. 

  1394. 	}
    1395. 

  1395. 

  1396. 	/* Look for matching PCI device */
    1397. 

  1397. 	errstr = "not found!";
    1398. 

  1398. 	pcidev = NULL;
    1399. 

  1399. 	board_index = this_board - boardtypes;
    1400. 

  1400. 	while (NULL != (pcidev = pci_get_device(PCI_VENDOR_ID_ADVANTECH,
    1401. 

  1401. 						PCI_ANY_ID, pcidev))) {
    1402. 

  1402. 		if (strcmp(this_board->name, DRV_NAME) == 0) {
    1403. 

  1403. 			for (i = 0; i < n_boardtypes; ++i) {
    1404. 

  1404. 				if (pcidev->device == boardtypes[i].device_id) {
    1405. 

  1405. 					board_index = i;
    1406. 

  1406. 					break;
    1407. 

  1407. 				}
    1408. 

  1408. 			}
    1409. 

  1409. 			if (i == n_boardtypes)
    1410. 

  1410. 				continue;
    1411. 

  1411. 		} else {
    1412. 

  1412. 			if (pcidev->device != boardtypes[board_index].device_id)
    1413. 

  1413. 				continue;
    1414. 

  1414. 		}
    1415. 

  1415. 

  1416. 		/* Found matching vendor/device. */
    1417. 

  1417. 		if (opt_bus || opt_slot) {
    1418. 

  1418. 			/* Check bus/slot. */
    1419. 

  1419. 			if (opt_bus != pcidev->bus->number
    1420. 

  1420. 			    || opt_slot != PCI_SLOT(pcidev->devfn))
    1421. 

  1421. 				continue;	/* no match */
    1422. 

  1422. 		}
    1423. 

  1423. 		/*
    1424. 

  1424. 		 * Look for device that isn't in use.
    1425. 

  1425. 		 * Enable PCI device and request regions.
    1426. 

  1426. 		 */
    1427. 

  1427. 		if (comedi_pci_enable(pcidev, DRV_NAME)) {
    1428. 

  1428. 			errstr =
    1429. 

  1429. 			    "failed to enable PCI device and request regions!";
    1430. 

  1430. 			continue;
    1431. 

  1431. 		}
    1432. 

  1432. 		/*  fixup board_ptr in case we were using the dummy entry with the driver name */
    1433. 

  1433. 		dev->board_ptr = &boardtypes[board_index];
    1434. 

  1434. 		break;
    1435. 

  1435. 	}
    1436. 

  1436. 

  1437. 	if (!pcidev) {
    1438. 

  1438. 		if (opt_bus || opt_slot) {
    1439. 

  1439. 			printk(" - Card at b:s %d:%d %s\n",
    1440. 

  1440. 			       opt_bus, opt_slot, errstr);
    1441. 

  1441. 		} else {
    1442. 

  1442. 			printk(" - Card %s\n", errstr);
    1443. 

  1443. 		}
    1444. 

  1444. 		return -EIO;
    1445. 

  1445. 	}
    1446. 

  1446. 

  1447. 	pci_bus = pcidev->bus->number;
    1448. 

  1448. 	pci_slot = PCI_SLOT(pcidev->devfn);
    1449. 

  1449. 	pci_func = PCI_FUNC(pcidev->devfn);
    1450. 

  1450. 	irq = pcidev->irq;
    1451. 

  1451. 	iobase = pci_resource_start(pcidev, 2);
    1452. 

  1452. 

  1453. 	printk(", b:s:f=%d:%d:%d, io=0x%4lx", pci_bus, pci_slot, pci_func,
    1454. 

  1454. 	       iobase);
    1455. 

  1455. 

  1456. 	dev->iobase = iobase;
    1457. 

  1457. 

  1458. 	dev->board_name = this_board->name;
    1459. 

  1459. 	devpriv->pcidev = pcidev;
    1460. 

  1460. 

  1461. 	n_subdevices = 0;
    1462. 

  1462. 	if (this_board->n_aichan)
    1463. 

  1463. 		n_subdevices++;
    1464. 

  1464. 	if (this_board->n_aochan)
    1465. 

  1465. 		n_subdevices++;
    1466. 

  1466. 	if (this_board->n_dichan)
    1467. 

  1467. 		n_subdevices++;
    1468. 

  1468. 	if (this_board->n_dochan)
    1469. 

  1469. 		n_subdevices++;
    1470. 

  1470. 	if (this_board->n_counter)
    1471. 

  1471. 		n_subdevices++;
    1472. 

  1472. 

  1473. 	ret = alloc_subdevices(dev, n_subdevices);
    1474. 

  1474. 	if (ret < 0) {
    1475. 

  1475. 		printk(" - Allocation failed!\n");
    1476. 

  1476. 		return ret;
    1477. 

  1477. 	}
    1478. 

  1478. 

  1479. 	pci1710_reset(dev);
    1480. 

  1480. 

  1481. 	if (this_board->have_irq) {
    1482. 

  1482. 		if (irq) {
    1483. 

  1483. 			if (request_irq(irq, interrupt_service_pci1710,
    1484. 

  1484. 					IRQF_SHARED, "Advantech PCI-1710",
    1485. 

  1485. 					dev)) {
    1486. 

  1486. 				printk
    1487. 

  1487. 				    (", unable to allocate IRQ %d, DISABLING IT",
    1488. 

  1488. 				     irq);
    1489. 

  1489. 				irq = 0;	/* Can't use IRQ */
    1490. 

  1490. 			} else {
    1491. 

  1491. 				printk(", irq=%u", irq);
    1492. 

  1492. 			}
    1493. 

  1493. 		} else {
    1494. 

  1494. 			printk(", IRQ disabled");
    1495. 

  1495. 		}
    1496. 

  1496. 	} else {
    1497. 

  1497. 		irq = 0;
    1498. 

  1498. 	}
    1499. 

  1499. 

  1500. 	dev->irq = irq;
    1501. 

  1501. 

  1502. 	printk(".\n");
    1503. 

  1503. 

  1504. 	subdev = 0;
    1505. 

  1505. 

  1506. 	if (this_board->n_aichan) {
    1507. 

  1507. 		s = dev->subdevices + subdev;
    1508. 

  1508. 		dev->read_subdev = s;
    1509. 

  1509. 		s->type = COMEDI_SUBD_AI;
    1510. 

  1510. 		s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND;
    1511. 

  1511. 		if (this_board->n_aichand)
    1512. 

  1512. 			s->subdev_flags |= SDF_DIFF;
    1513. 

  1513. 		s->n_chan = this_board->n_aichan;
    1514. 

  1514. 		s->maxdata = this_board->ai_maxdata;
    1515. 

  1515. 		s->len_chanlist = this_board->n_aichan;
    1516. 

  1516. 		s->range_table = this_board->rangelist_ai;
    1517. 

  1517. 		s->cancel = pci171x_ai_cancel;
    1518. 

  1518. 		s->insn_read = pci171x_insn_read_ai;
    1519. 

  1519. 		if (irq) {
    1520. 

  1520. 			s->subdev_flags |= SDF_CMD_READ;
    1521. 

  1521. 			s->do_cmdtest = pci171x_ai_cmdtest;
    1522. 

  1522. 			s->do_cmd = pci171x_ai_cmd;
    1523. 

  1523. 		}
    1524. 

  1524. 		devpriv->i8254_osc_base = 100;	/*  100ns=10MHz */
    1525. 

  1525. 		subdev++;
    1526. 

  1526. 	}
    1527. 

  1527. 

  1528. 	if (this_board->n_aochan) {
    1529. 

  1529. 		s = dev->subdevices + subdev;
    1530. 

  1530. 		s->type = COMEDI_SUBD_AO;
    1531. 

  1531. 		s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
    1532. 

  1532. 		s->n_chan = this_board->n_aochan;
    1533. 

  1533. 		s->maxdata = this_board->ao_maxdata;
    1534. 

  1534. 		s->len_chanlist = this_board->n_aochan;
    1535. 

  1535. 		s->range_table = this_board->rangelist_ao;
    1536. 

  1536. 		switch (this_board->cardtype) {
    1537. 

  1537. 		case TYPE_PCI1720:
    1538. 

  1538. 			s->insn_write = pci1720_insn_write_ao;
    1539. 

  1539. 			break;
    1540. 

  1540. 		default:
    1541. 

  1541. 			s->insn_write = pci171x_insn_write_ao;
    1542. 

  1542. 			break;
    1543. 

  1543. 		}
    1544. 

  1544. 		s->insn_read = pci171x_insn_read_ao;
    1545. 

  1545. 		subdev++;
    1546. 

  1546. 	}
    1547. 

  1547. 

  1548. 	if (this_board->n_dichan) {
    1549. 

  1549. 		s = dev->subdevices + subdev;
    1550. 

  1550. 		s->type = COMEDI_SUBD_DI;
    1551. 

  1551. 		s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
    1552. 

  1552. 		s->n_chan = this_board->n_dichan;
    1553. 

  1553. 		s->maxdata = 1;
    1554. 

  1554. 		s->len_chanlist = this_board->n_dichan;
    1555. 

  1555. 		s->range_table = &range_digital;
    1556. 

  1556. 		s->io_bits = 0;	/* all bits input */
    1557. 

  1557. 		s->insn_bits = pci171x_insn_bits_di;
    1558. 

  1558. 		subdev++;
    1559. 

  1559. 	}
    1560. 

  1560. 

  1561. 	if (this_board->n_dochan) {
    1562. 

  1562. 		s = dev->subdevices + subdev;
    1563. 

  1563. 		s->type = COMEDI_SUBD_DO;
    1564. 

  1564. 		s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
    1565. 

  1565. 		s->n_chan = this_board->n_dochan;
    1566. 

  1566. 		s->maxdata = 1;
    1567. 

  1567. 		s->len_chanlist = this_board->n_dochan;
    1568. 

  1568. 		s->range_table = &range_digital;
    1569. 

  1569. 		/* all bits output */
    1570. 

  1570. 		s->io_bits = (1 << this_board->n_dochan) - 1;
    1571. 

  1571. 		s->state = 0;
    1572. 

  1572. 		s->insn_bits = pci171x_insn_bits_do;
    1573. 

  1573. 		subdev++;
    1574. 

  1574. 	}
    1575. 

  1575. 

  1576. 	if (this_board->n_counter) {
    1577. 

  1577. 		s = dev->subdevices + subdev;
    1578. 

  1578. 		s->type = COMEDI_SUBD_COUNTER;
    1579. 

  1579. 		s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
    1580. 

  1580. 		s->n_chan = this_board->n_counter;
    1581. 

  1581. 		s->len_chanlist = this_board->n_counter;
    1582. 

  1582. 		s->maxdata = 0xffff;
    1583. 

  1583. 		s->range_table = &range_unknown;
    1584. 

  1584. 		s->insn_read = pci171x_insn_counter_read;
    1585. 

  1585. 		s->insn_write = pci171x_insn_counter_write;
    1586. 

  1586. 		s->insn_config = pci171x_insn_counter_config;
    1587. 

  1587. 		subdev++;
    1588. 

  1588. 	}
    1589. 

  1589. 

  1590. 	devpriv->valid = 1;
    1591. 

  1591. 

  1592. 	return 0;
    1593. 

  1593. }
    1594. 

  1594. 

  1595. /*
    1596. 

  1596. ==============================================================================
    1597. 

  1597. */
    1598. 

  1598. static int pci1710_detach(struct comedi_device *dev)
    1599. 

  1599. {
    1600. 

  1600. 

  1601. 	if (dev->private) {
    1602. 

  1602. 		if (devpriv->valid)
    1603. 

  1603. 			pci1710_reset(dev);
    1604. 

  1604. 		if (dev->irq)
    1605. 

  1605. 			free_irq(dev->irq, dev);
    1606. 

  1606. 		if (devpriv->pcidev) {
    1607. 

  1607. 			if (dev->iobase)
    1608. 

  1608. 				comedi_pci_disable(devpriv->pcidev);
    1609. 

  1609. 

  1610. 			pci_dev_put(devpriv->pcidev);
    1611. 

  1611. 		}
    1612. 

  1612. 	}
    1613. 

  1613. 

  1614. 	return 0;
    1615. 

  1615. }
    1616. 

  1616. 

  1617. /*
    1618. 

  1618. ==============================================================================
    1619. 

  1619. */
    1620. 

  1620. static int __devinit driver_pci1710_pci_probe(struct pci_dev *dev,
    1621. 

  1621. 					      const struct pci_device_id *ent)
    1622. 

  1622. {
    1623. 

  1623. 	return comedi_pci_auto_config(dev, driver_pci1710.driver_name);
    1624. 

  1624. }
    1625. 

  1625. 

  1626. static void __devexit driver_pci1710_pci_remove(struct pci_dev *dev)
    1627. 

  1627. {
    1628. 

  1628. 	comedi_pci_auto_unconfig(dev);
    1629. 

  1629. }
    1630. 

  1630. 

  1631. static struct pci_driver driver_pci1710_pci_driver = {
    1632. 

  1632. 	.id_table = pci1710_pci_table,
    1633. 

  1633. 	.probe = &driver_pci1710_pci_probe,
    1634. 

  1634. 	.remove = __devexit_p(&driver_pci1710_pci_remove)
    1635. 

  1635. };
    1636. 

  1636. 

  1637. static int __init driver_pci1710_init_module(void)
    1638. 

  1638. {
    1639. 

  1639. 	int retval;
    1640. 

  1640. 

  1641. 	retval = comedi_driver_register(&driver_pci1710);
    1642. 

  1642. 	if (retval < 0)
    1643. 

  1643. 		return retval;
    1644. 

  1644. 

  1645. 	driver_pci1710_pci_driver.name = (char *)driver_pci1710.driver_name;
    1646. 

  1646. 	return pci_register_driver(&driver_pci1710_pci_driver);
    1647. 

  1647. }
    1648. 

  1648. 

  1649. static void __exit driver_pci1710_cleanup_module(void)
    1650. 

  1650. {
    1651. 

  1651. 	pci_unregister_driver(&driver_pci1710_pci_driver);
    1652. 

  1652. 	comedi_driver_unregister(&driver_pci1710);
    1653. 

  1653. }
    1654. 

  1654. 

  1655. module_init(driver_pci1710_init_module);
    1656. 

  1656. module_exit(driver_pci1710_cleanup_module);
    1657. 

  1657. /*
    1658. 

  1658. ==============================================================================
    1659. 

  1659. */
    1660. 

  1660. 

  1661. MODULE_AUTHOR("Comedi http://www.comedi.org");
    1662. 

  1662. MODULE_DESCRIPTION("Comedi low-level driver");
    1663. 

  1663. MODULE_LICENSE("GPL");
    1664.