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/drivers/staging/vme/bridges/vme_tsi148.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 2640 lines | 1852 code | 429 blank | 359 comment | 260 complexity | f2771802109565078f29c72070a82e0f MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/*
   2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
   3 *
   4 * Author: Martyn Welch <martyn.welch@ge.com>
   5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6 *
   7 * Based on work by Tom Armistead and Ajit Prem
   8 * Copyright 2004 Motorola Inc.
   9 *
  10 * This program is free software; you can redistribute  it and/or modify it
  11 * under  the terms of  the GNU General  Public License as published by the
  12 * Free Software Foundation;  either version 2 of the  License, or (at your
  13 * option) any later version.
  14 */
  15
  16#include <linux/module.h>
  17#include <linux/moduleparam.h>
  18#include <linux/mm.h>
  19#include <linux/types.h>
  20#include <linux/errno.h>
  21#include <linux/proc_fs.h>
  22#include <linux/pci.h>
  23#include <linux/poll.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/interrupt.h>
  26#include <linux/spinlock.h>
  27#include <linux/sched.h>
  28#include <linux/slab.h>
  29#include <linux/time.h>
  30#include <linux/io.h>
  31#include <linux/uaccess.h>
  32
  33#include "../vme.h"
  34#include "../vme_bridge.h"
  35#include "vme_tsi148.h"
  36
  37static int __init tsi148_init(void);
  38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
  39static void tsi148_remove(struct pci_dev *);
  40static void __exit tsi148_exit(void);
  41
  42
  43/* Module parameter */
  44static int err_chk;
  45static int geoid;
  46
  47static char driver_name[] = "vme_tsi148";
  48
  49static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = {
  50	{ PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
  51	{ },
  52};
  53
  54static struct pci_driver tsi148_driver = {
  55	.name = driver_name,
  56	.id_table = tsi148_ids,
  57	.probe = tsi148_probe,
  58	.remove = tsi148_remove,
  59};
  60
  61static void reg_join(unsigned int high, unsigned int low,
  62	unsigned long long *variable)
  63{
  64	*variable = (unsigned long long)high << 32;
  65	*variable |= (unsigned long long)low;
  66}
  67
  68static void reg_split(unsigned long long variable, unsigned int *high,
  69	unsigned int *low)
  70{
  71	*low = (unsigned int)variable & 0xFFFFFFFF;
  72	*high = (unsigned int)(variable >> 32);
  73}
  74
  75/*
  76 * Wakes up DMA queue.
  77 */
  78static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
  79	int channel_mask)
  80{
  81	u32 serviced = 0;
  82
  83	if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
  84		wake_up(&bridge->dma_queue[0]);
  85		serviced |= TSI148_LCSR_INTC_DMA0C;
  86	}
  87	if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
  88		wake_up(&bridge->dma_queue[1]);
  89		serviced |= TSI148_LCSR_INTC_DMA1C;
  90	}
  91
  92	return serviced;
  93}
  94
  95/*
  96 * Wake up location monitor queue
  97 */
  98static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
  99{
 100	int i;
 101	u32 serviced = 0;
 102
 103	for (i = 0; i < 4; i++) {
 104		if (stat & TSI148_LCSR_INTS_LMS[i]) {
 105			/* We only enable interrupts if the callback is set */
 106			bridge->lm_callback[i](i);
 107			serviced |= TSI148_LCSR_INTC_LMC[i];
 108		}
 109	}
 110
 111	return serviced;
 112}
 113
 114/*
 115 * Wake up mail box queue.
 116 *
 117 * XXX This functionality is not exposed up though API.
 118 */
 119static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
 120{
 121	int i;
 122	u32 val;
 123	u32 serviced = 0;
 124	struct tsi148_driver *bridge;
 125
 126	bridge = tsi148_bridge->driver_priv;
 127
 128	for (i = 0; i < 4; i++) {
 129		if (stat & TSI148_LCSR_INTS_MBS[i]) {
 130			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);
 131			dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
 132				": 0x%x\n", i, val);
 133			serviced |= TSI148_LCSR_INTC_MBC[i];
 134		}
 135	}
 136
 137	return serviced;
 138}
 139
 140/*
 141 * Display error & status message when PERR (PCI) exception interrupt occurs.
 142 */
 143static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
 144{
 145	struct tsi148_driver *bridge;
 146
 147	bridge = tsi148_bridge->driver_priv;
 148
 149	dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
 150		"attributes: %08x\n",
 151		ioread32be(bridge->base + TSI148_LCSR_EDPAU),
 152		ioread32be(bridge->base + TSI148_LCSR_EDPAL),
 153		ioread32be(bridge->base + TSI148_LCSR_EDPAT));
 154
 155	dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
 156		"completion reg: %08x\n",
 157		ioread32be(bridge->base + TSI148_LCSR_EDPXA),
 158		ioread32be(bridge->base + TSI148_LCSR_EDPXS));
 159
 160	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
 161
 162	return TSI148_LCSR_INTC_PERRC;
 163}
 164
 165/*
 166 * Save address and status when VME error interrupt occurs.
 167 */
 168static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
 169{
 170	unsigned int error_addr_high, error_addr_low;
 171	unsigned long long error_addr;
 172	u32 error_attrib;
 173	struct vme_bus_error *error;
 174	struct tsi148_driver *bridge;
 175
 176	bridge = tsi148_bridge->driver_priv;
 177
 178	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
 179	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
 180	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
 181
 182	reg_join(error_addr_high, error_addr_low, &error_addr);
 183
 184	/* Check for exception register overflow (we have lost error data) */
 185	if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
 186		dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
 187			"Occurred\n");
 188	}
 189
 190	error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
 191	if (error) {
 192		error->address = error_addr;
 193		error->attributes = error_attrib;
 194		list_add_tail(&error->list, &tsi148_bridge->vme_errors);
 195	} else {
 196		dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
 197			"VMEbus Error reporting\n");
 198		dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
 199			"0x%llx, attributes: %08x\n", error_addr, error_attrib);
 200	}
 201
 202	/* Clear Status */
 203	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
 204
 205	return TSI148_LCSR_INTC_VERRC;
 206}
 207
 208/*
 209 * Wake up IACK queue.
 210 */
 211static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
 212{
 213	wake_up(&bridge->iack_queue);
 214
 215	return TSI148_LCSR_INTC_IACKC;
 216}
 217
 218/*
 219 * Calling VME bus interrupt callback if provided.
 220 */
 221static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
 222	u32 stat)
 223{
 224	int vec, i, serviced = 0;
 225	struct tsi148_driver *bridge;
 226
 227	bridge = tsi148_bridge->driver_priv;
 228
 229	for (i = 7; i > 0; i--) {
 230		if (stat & (1 << i)) {
 231			/*
 232			 * Note: Even though the registers are defined as
 233			 * 32-bits in the spec, we only want to issue 8-bit
 234			 * IACK cycles on the bus, read from offset 3.
 235			 */
 236			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
 237
 238			vme_irq_handler(tsi148_bridge, i, vec);
 239
 240			serviced |= (1 << i);
 241		}
 242	}
 243
 244	return serviced;
 245}
 246
 247/*
 248 * Top level interrupt handler.  Clears appropriate interrupt status bits and
 249 * then calls appropriate sub handler(s).
 250 */
 251static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
 252{
 253	u32 stat, enable, serviced = 0;
 254	struct vme_bridge *tsi148_bridge;
 255	struct tsi148_driver *bridge;
 256
 257	tsi148_bridge = ptr;
 258
 259	bridge = tsi148_bridge->driver_priv;
 260
 261	/* Determine which interrupts are unmasked and set */
 262	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 263	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
 264
 265	/* Only look at unmasked interrupts */
 266	stat &= enable;
 267
 268	if (unlikely(!stat))
 269		return IRQ_NONE;
 270
 271	/* Call subhandlers as appropriate */
 272	/* DMA irqs */
 273	if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
 274		serviced |= tsi148_DMA_irqhandler(bridge, stat);
 275
 276	/* Location monitor irqs */
 277	if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
 278			TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
 279		serviced |= tsi148_LM_irqhandler(bridge, stat);
 280
 281	/* Mail box irqs */
 282	if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
 283			TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
 284		serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
 285
 286	/* PCI bus error */
 287	if (stat & TSI148_LCSR_INTS_PERRS)
 288		serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
 289
 290	/* VME bus error */
 291	if (stat & TSI148_LCSR_INTS_VERRS)
 292		serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
 293
 294	/* IACK irq */
 295	if (stat & TSI148_LCSR_INTS_IACKS)
 296		serviced |= tsi148_IACK_irqhandler(bridge);
 297
 298	/* VME bus irqs */
 299	if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
 300			TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
 301			TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
 302			TSI148_LCSR_INTS_IRQ1S))
 303		serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
 304
 305	/* Clear serviced interrupts */
 306	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
 307
 308	return IRQ_HANDLED;
 309}
 310
 311static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
 312{
 313	int result;
 314	unsigned int tmp;
 315	struct pci_dev *pdev;
 316	struct tsi148_driver *bridge;
 317
 318	pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 319
 320	bridge = tsi148_bridge->driver_priv;
 321
 322	/* Initialise list for VME bus errors */
 323	INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
 324
 325	mutex_init(&tsi148_bridge->irq_mtx);
 326
 327	result = request_irq(pdev->irq,
 328			     tsi148_irqhandler,
 329			     IRQF_SHARED,
 330			     driver_name, tsi148_bridge);
 331	if (result) {
 332		dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
 333			"vector %02X\n", pdev->irq);
 334		return result;
 335	}
 336
 337	/* Enable and unmask interrupts */
 338	tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
 339		TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
 340		TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
 341		TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
 342		TSI148_LCSR_INTEO_IACKEO;
 343
 344	/* This leaves the following interrupts masked.
 345	 * TSI148_LCSR_INTEO_VIEEO
 346	 * TSI148_LCSR_INTEO_SYSFLEO
 347	 * TSI148_LCSR_INTEO_ACFLEO
 348	 */
 349
 350	/* Don't enable Location Monitor interrupts here - they will be
 351	 * enabled when the location monitors are properly configured and
 352	 * a callback has been attached.
 353	 * TSI148_LCSR_INTEO_LM0EO
 354	 * TSI148_LCSR_INTEO_LM1EO
 355	 * TSI148_LCSR_INTEO_LM2EO
 356	 * TSI148_LCSR_INTEO_LM3EO
 357	 */
 358
 359	/* Don't enable VME interrupts until we add a handler, else the board
 360	 * will respond to it and we don't want that unless it knows how to
 361	 * properly deal with it.
 362	 * TSI148_LCSR_INTEO_IRQ7EO
 363	 * TSI148_LCSR_INTEO_IRQ6EO
 364	 * TSI148_LCSR_INTEO_IRQ5EO
 365	 * TSI148_LCSR_INTEO_IRQ4EO
 366	 * TSI148_LCSR_INTEO_IRQ3EO
 367	 * TSI148_LCSR_INTEO_IRQ2EO
 368	 * TSI148_LCSR_INTEO_IRQ1EO
 369	 */
 370
 371	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 372	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 373
 374	return 0;
 375}
 376
 377static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
 378	struct pci_dev *pdev)
 379{
 380	struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
 381
 382	/* Turn off interrupts */
 383	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
 384	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
 385
 386	/* Clear all interrupts */
 387	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
 388
 389	/* Detach interrupt handler */
 390	free_irq(pdev->irq, tsi148_bridge);
 391}
 392
 393/*
 394 * Check to see if an IACk has been received, return true (1) or false (0).
 395 */
 396static int tsi148_iack_received(struct tsi148_driver *bridge)
 397{
 398	u32 tmp;
 399
 400	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 401
 402	if (tmp & TSI148_LCSR_VICR_IRQS)
 403		return 0;
 404	else
 405		return 1;
 406}
 407
 408/*
 409 * Configure VME interrupt
 410 */
 411static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
 412	int state, int sync)
 413{
 414	struct pci_dev *pdev;
 415	u32 tmp;
 416	struct tsi148_driver *bridge;
 417
 418	bridge = tsi148_bridge->driver_priv;
 419
 420	/* We need to do the ordering differently for enabling and disabling */
 421	if (state == 0) {
 422		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 423		tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
 424		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 425
 426		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 427		tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
 428		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 429
 430		if (sync != 0) {
 431			pdev = container_of(tsi148_bridge->parent,
 432				struct pci_dev, dev);
 433
 434			synchronize_irq(pdev->irq);
 435		}
 436	} else {
 437		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 438		tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
 439		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 440
 441		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 442		tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
 443		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 444	}
 445}
 446
 447/*
 448 * Generate a VME bus interrupt at the requested level & vector. Wait for
 449 * interrupt to be acked.
 450 */
 451static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
 452	int statid)
 453{
 454	u32 tmp;
 455	struct tsi148_driver *bridge;
 456
 457	bridge = tsi148_bridge->driver_priv;
 458
 459	mutex_lock(&bridge->vme_int);
 460
 461	/* Read VICR register */
 462	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 463
 464	/* Set Status/ID */
 465	tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
 466		(statid & TSI148_LCSR_VICR_STID_M);
 467	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 468
 469	/* Assert VMEbus IRQ */
 470	tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
 471	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 472
 473	/* XXX Consider implementing a timeout? */
 474	wait_event_interruptible(bridge->iack_queue,
 475		tsi148_iack_received(bridge));
 476
 477	mutex_unlock(&bridge->vme_int);
 478
 479	return 0;
 480}
 481
 482/*
 483 * Find the first error in this address range
 484 */
 485static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
 486	vme_address_t aspace, unsigned long long address, size_t count)
 487{
 488	struct list_head *err_pos;
 489	struct vme_bus_error *vme_err, *valid = NULL;
 490	unsigned long long bound;
 491
 492	bound = address + count;
 493
 494	/*
 495	 * XXX We are currently not looking at the address space when parsing
 496	 *     for errors. This is because parsing the Address Modifier Codes
 497	 *     is going to be quite resource intensive to do properly. We
 498	 *     should be OK just looking at the addresses and this is certainly
 499	 *     much better than what we had before.
 500	 */
 501	err_pos = NULL;
 502	/* Iterate through errors */
 503	list_for_each(err_pos, &tsi148_bridge->vme_errors) {
 504		vme_err = list_entry(err_pos, struct vme_bus_error, list);
 505		if ((vme_err->address >= address) &&
 506			(vme_err->address < bound)) {
 507
 508			valid = vme_err;
 509			break;
 510		}
 511	}
 512
 513	return valid;
 514}
 515
 516/*
 517 * Clear errors in the provided address range.
 518 */
 519static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
 520	vme_address_t aspace, unsigned long long address, size_t count)
 521{
 522	struct list_head *err_pos, *temp;
 523	struct vme_bus_error *vme_err;
 524	unsigned long long bound;
 525
 526	bound = address + count;
 527
 528	/*
 529	 * XXX We are currently not looking at the address space when parsing
 530	 *     for errors. This is because parsing the Address Modifier Codes
 531	 *     is going to be quite resource intensive to do properly. We
 532	 *     should be OK just looking at the addresses and this is certainly
 533	 *     much better than what we had before.
 534	 */
 535	err_pos = NULL;
 536	/* Iterate through errors */
 537	list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
 538		vme_err = list_entry(err_pos, struct vme_bus_error, list);
 539
 540		if ((vme_err->address >= address) &&
 541			(vme_err->address < bound)) {
 542
 543			list_del(err_pos);
 544			kfree(vme_err);
 545		}
 546	}
 547}
 548
 549/*
 550 * Initialize a slave window with the requested attributes.
 551 */
 552static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
 553	unsigned long long vme_base, unsigned long long size,
 554	dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 555{
 556	unsigned int i, addr = 0, granularity = 0;
 557	unsigned int temp_ctl = 0;
 558	unsigned int vme_base_low, vme_base_high;
 559	unsigned int vme_bound_low, vme_bound_high;
 560	unsigned int pci_offset_low, pci_offset_high;
 561	unsigned long long vme_bound, pci_offset;
 562	struct vme_bridge *tsi148_bridge;
 563	struct tsi148_driver *bridge;
 564
 565	tsi148_bridge = image->parent;
 566	bridge = tsi148_bridge->driver_priv;
 567
 568	i = image->number;
 569
 570	switch (aspace) {
 571	case VME_A16:
 572		granularity = 0x10;
 573		addr |= TSI148_LCSR_ITAT_AS_A16;
 574		break;
 575	case VME_A24:
 576		granularity = 0x1000;
 577		addr |= TSI148_LCSR_ITAT_AS_A24;
 578		break;
 579	case VME_A32:
 580		granularity = 0x10000;
 581		addr |= TSI148_LCSR_ITAT_AS_A32;
 582		break;
 583	case VME_A64:
 584		granularity = 0x10000;
 585		addr |= TSI148_LCSR_ITAT_AS_A64;
 586		break;
 587	case VME_CRCSR:
 588	case VME_USER1:
 589	case VME_USER2:
 590	case VME_USER3:
 591	case VME_USER4:
 592	default:
 593		dev_err(tsi148_bridge->parent, "Invalid address space\n");
 594		return -EINVAL;
 595		break;
 596	}
 597
 598	/* Convert 64-bit variables to 2x 32-bit variables */
 599	reg_split(vme_base, &vme_base_high, &vme_base_low);
 600
 601	/*
 602	 * Bound address is a valid address for the window, adjust
 603	 * accordingly
 604	 */
 605	vme_bound = vme_base + size - granularity;
 606	reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
 607	pci_offset = (unsigned long long)pci_base - vme_base;
 608	reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
 609
 610	if (vme_base_low & (granularity - 1)) {
 611		dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
 612		return -EINVAL;
 613	}
 614	if (vme_bound_low & (granularity - 1)) {
 615		dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
 616		return -EINVAL;
 617	}
 618	if (pci_offset_low & (granularity - 1)) {
 619		dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
 620			"alignment\n");
 621		return -EINVAL;
 622	}
 623
 624	/*  Disable while we are mucking around */
 625	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 626		TSI148_LCSR_OFFSET_ITAT);
 627	temp_ctl &= ~TSI148_LCSR_ITAT_EN;
 628	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 629		TSI148_LCSR_OFFSET_ITAT);
 630
 631	/* Setup mapping */
 632	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
 633		TSI148_LCSR_OFFSET_ITSAU);
 634	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
 635		TSI148_LCSR_OFFSET_ITSAL);
 636	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
 637		TSI148_LCSR_OFFSET_ITEAU);
 638	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
 639		TSI148_LCSR_OFFSET_ITEAL);
 640	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
 641		TSI148_LCSR_OFFSET_ITOFU);
 642	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
 643		TSI148_LCSR_OFFSET_ITOFL);
 644
 645	/* Setup 2eSST speeds */
 646	temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
 647	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 648	case VME_2eSST160:
 649		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
 650		break;
 651	case VME_2eSST267:
 652		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
 653		break;
 654	case VME_2eSST320:
 655		temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
 656		break;
 657	}
 658
 659	/* Setup cycle types */
 660	temp_ctl &= ~(0x1F << 7);
 661	if (cycle & VME_BLT)
 662		temp_ctl |= TSI148_LCSR_ITAT_BLT;
 663	if (cycle & VME_MBLT)
 664		temp_ctl |= TSI148_LCSR_ITAT_MBLT;
 665	if (cycle & VME_2eVME)
 666		temp_ctl |= TSI148_LCSR_ITAT_2eVME;
 667	if (cycle & VME_2eSST)
 668		temp_ctl |= TSI148_LCSR_ITAT_2eSST;
 669	if (cycle & VME_2eSSTB)
 670		temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
 671
 672	/* Setup address space */
 673	temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
 674	temp_ctl |= addr;
 675
 676	temp_ctl &= ~0xF;
 677	if (cycle & VME_SUPER)
 678		temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
 679	if (cycle & VME_USER)
 680		temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
 681	if (cycle & VME_PROG)
 682		temp_ctl |= TSI148_LCSR_ITAT_PGM;
 683	if (cycle & VME_DATA)
 684		temp_ctl |= TSI148_LCSR_ITAT_DATA;
 685
 686	/* Write ctl reg without enable */
 687	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 688		TSI148_LCSR_OFFSET_ITAT);
 689
 690	if (enabled)
 691		temp_ctl |= TSI148_LCSR_ITAT_EN;
 692
 693	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 694		TSI148_LCSR_OFFSET_ITAT);
 695
 696	return 0;
 697}
 698
 699/*
 700 * Get slave window configuration.
 701 */
 702static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
 703	unsigned long long *vme_base, unsigned long long *size,
 704	dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 705{
 706	unsigned int i, granularity = 0, ctl = 0;
 707	unsigned int vme_base_low, vme_base_high;
 708	unsigned int vme_bound_low, vme_bound_high;
 709	unsigned int pci_offset_low, pci_offset_high;
 710	unsigned long long vme_bound, pci_offset;
 711	struct tsi148_driver *bridge;
 712
 713	bridge = image->parent->driver_priv;
 714
 715	i = image->number;
 716
 717	/* Read registers */
 718	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 719		TSI148_LCSR_OFFSET_ITAT);
 720
 721	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 722		TSI148_LCSR_OFFSET_ITSAU);
 723	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 724		TSI148_LCSR_OFFSET_ITSAL);
 725	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 726		TSI148_LCSR_OFFSET_ITEAU);
 727	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 728		TSI148_LCSR_OFFSET_ITEAL);
 729	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 730		TSI148_LCSR_OFFSET_ITOFU);
 731	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 732		TSI148_LCSR_OFFSET_ITOFL);
 733
 734	/* Convert 64-bit variables to 2x 32-bit variables */
 735	reg_join(vme_base_high, vme_base_low, vme_base);
 736	reg_join(vme_bound_high, vme_bound_low, &vme_bound);
 737	reg_join(pci_offset_high, pci_offset_low, &pci_offset);
 738
 739	*pci_base = (dma_addr_t)vme_base + pci_offset;
 740
 741	*enabled = 0;
 742	*aspace = 0;
 743	*cycle = 0;
 744
 745	if (ctl & TSI148_LCSR_ITAT_EN)
 746		*enabled = 1;
 747
 748	if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
 749		granularity = 0x10;
 750		*aspace |= VME_A16;
 751	}
 752	if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
 753		granularity = 0x1000;
 754		*aspace |= VME_A24;
 755	}
 756	if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
 757		granularity = 0x10000;
 758		*aspace |= VME_A32;
 759	}
 760	if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
 761		granularity = 0x10000;
 762		*aspace |= VME_A64;
 763	}
 764
 765	/* Need granularity before we set the size */
 766	*size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 767
 768
 769	if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
 770		*cycle |= VME_2eSST160;
 771	if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
 772		*cycle |= VME_2eSST267;
 773	if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
 774		*cycle |= VME_2eSST320;
 775
 776	if (ctl & TSI148_LCSR_ITAT_BLT)
 777		*cycle |= VME_BLT;
 778	if (ctl & TSI148_LCSR_ITAT_MBLT)
 779		*cycle |= VME_MBLT;
 780	if (ctl & TSI148_LCSR_ITAT_2eVME)
 781		*cycle |= VME_2eVME;
 782	if (ctl & TSI148_LCSR_ITAT_2eSST)
 783		*cycle |= VME_2eSST;
 784	if (ctl & TSI148_LCSR_ITAT_2eSSTB)
 785		*cycle |= VME_2eSSTB;
 786
 787	if (ctl & TSI148_LCSR_ITAT_SUPR)
 788		*cycle |= VME_SUPER;
 789	if (ctl & TSI148_LCSR_ITAT_NPRIV)
 790		*cycle |= VME_USER;
 791	if (ctl & TSI148_LCSR_ITAT_PGM)
 792		*cycle |= VME_PROG;
 793	if (ctl & TSI148_LCSR_ITAT_DATA)
 794		*cycle |= VME_DATA;
 795
 796	return 0;
 797}
 798
 799/*
 800 * Allocate and map PCI Resource
 801 */
 802static int tsi148_alloc_resource(struct vme_master_resource *image,
 803	unsigned long long size)
 804{
 805	unsigned long long existing_size;
 806	int retval = 0;
 807	struct pci_dev *pdev;
 808	struct vme_bridge *tsi148_bridge;
 809
 810	tsi148_bridge = image->parent;
 811
 812	pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 813
 814	existing_size = (unsigned long long)(image->bus_resource.end -
 815		image->bus_resource.start);
 816
 817	/* If the existing size is OK, return */
 818	if ((size != 0) && (existing_size == (size - 1)))
 819		return 0;
 820
 821	if (existing_size != 0) {
 822		iounmap(image->kern_base);
 823		image->kern_base = NULL;
 824		kfree(image->bus_resource.name);
 825		release_resource(&image->bus_resource);
 826		memset(&image->bus_resource, 0, sizeof(struct resource));
 827	}
 828
 829	/* Exit here if size is zero */
 830	if (size == 0)
 831		return 0;
 832
 833	if (image->bus_resource.name == NULL) {
 834		image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
 835		if (image->bus_resource.name == NULL) {
 836			dev_err(tsi148_bridge->parent, "Unable to allocate "
 837				"memory for resource name\n");
 838			retval = -ENOMEM;
 839			goto err_name;
 840		}
 841	}
 842
 843	sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
 844		image->number);
 845
 846	image->bus_resource.start = 0;
 847	image->bus_resource.end = (unsigned long)size;
 848	image->bus_resource.flags = IORESOURCE_MEM;
 849
 850	retval = pci_bus_alloc_resource(pdev->bus,
 851		&image->bus_resource, size, size, PCIBIOS_MIN_MEM,
 852		0, NULL, NULL);
 853	if (retval) {
 854		dev_err(tsi148_bridge->parent, "Failed to allocate mem "
 855			"resource for window %d size 0x%lx start 0x%lx\n",
 856			image->number, (unsigned long)size,
 857			(unsigned long)image->bus_resource.start);
 858		goto err_resource;
 859	}
 860
 861	image->kern_base = ioremap_nocache(
 862		image->bus_resource.start, size);
 863	if (image->kern_base == NULL) {
 864		dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
 865		retval = -ENOMEM;
 866		goto err_remap;
 867	}
 868
 869	return 0;
 870
 871err_remap:
 872	release_resource(&image->bus_resource);
 873err_resource:
 874	kfree(image->bus_resource.name);
 875	memset(&image->bus_resource, 0, sizeof(struct resource));
 876err_name:
 877	return retval;
 878}
 879
 880/*
 881 * Free and unmap PCI Resource
 882 */
 883static void tsi148_free_resource(struct vme_master_resource *image)
 884{
 885	iounmap(image->kern_base);
 886	image->kern_base = NULL;
 887	release_resource(&image->bus_resource);
 888	kfree(image->bus_resource.name);
 889	memset(&image->bus_resource, 0, sizeof(struct resource));
 890}
 891
 892/*
 893 * Set the attributes of an outbound window.
 894 */
 895static int tsi148_master_set(struct vme_master_resource *image, int enabled,
 896	unsigned long long vme_base, unsigned long long size,
 897	vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 898{
 899	int retval = 0;
 900	unsigned int i;
 901	unsigned int temp_ctl = 0;
 902	unsigned int pci_base_low, pci_base_high;
 903	unsigned int pci_bound_low, pci_bound_high;
 904	unsigned int vme_offset_low, vme_offset_high;
 905	unsigned long long pci_bound, vme_offset, pci_base;
 906	struct vme_bridge *tsi148_bridge;
 907	struct tsi148_driver *bridge;
 908
 909	tsi148_bridge = image->parent;
 910
 911	bridge = tsi148_bridge->driver_priv;
 912
 913	/* Verify input data */
 914	if (vme_base & 0xFFFF) {
 915		dev_err(tsi148_bridge->parent, "Invalid VME Window "
 916			"alignment\n");
 917		retval = -EINVAL;
 918		goto err_window;
 919	}
 920
 921	if ((size == 0) && (enabled != 0)) {
 922		dev_err(tsi148_bridge->parent, "Size must be non-zero for "
 923			"enabled windows\n");
 924		retval = -EINVAL;
 925		goto err_window;
 926	}
 927
 928	spin_lock(&image->lock);
 929
 930	/* Let's allocate the resource here rather than further up the stack as
 931	 * it avoids pushing loads of bus dependent stuff up the stack. If size
 932	 * is zero, any existing resource will be freed.
 933	 */
 934	retval = tsi148_alloc_resource(image, size);
 935	if (retval) {
 936		spin_unlock(&image->lock);
 937		dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
 938			"resource\n");
 939		goto err_res;
 940	}
 941
 942	if (size == 0) {
 943		pci_base = 0;
 944		pci_bound = 0;
 945		vme_offset = 0;
 946	} else {
 947		pci_base = (unsigned long long)image->bus_resource.start;
 948
 949		/*
 950		 * Bound address is a valid address for the window, adjust
 951		 * according to window granularity.
 952		 */
 953		pci_bound = pci_base + (size - 0x10000);
 954		vme_offset = vme_base - pci_base;
 955	}
 956
 957	/* Convert 64-bit variables to 2x 32-bit variables */
 958	reg_split(pci_base, &pci_base_high, &pci_base_low);
 959	reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
 960	reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
 961
 962	if (pci_base_low & 0xFFFF) {
 963		spin_unlock(&image->lock);
 964		dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
 965		retval = -EINVAL;
 966		goto err_gran;
 967	}
 968	if (pci_bound_low & 0xFFFF) {
 969		spin_unlock(&image->lock);
 970		dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
 971		retval = -EINVAL;
 972		goto err_gran;
 973	}
 974	if (vme_offset_low & 0xFFFF) {
 975		spin_unlock(&image->lock);
 976		dev_err(tsi148_bridge->parent, "Invalid VME Offset "
 977			"alignment\n");
 978		retval = -EINVAL;
 979		goto err_gran;
 980	}
 981
 982	i = image->number;
 983
 984	/* Disable while we are mucking around */
 985	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
 986		TSI148_LCSR_OFFSET_OTAT);
 987	temp_ctl &= ~TSI148_LCSR_OTAT_EN;
 988	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
 989		TSI148_LCSR_OFFSET_OTAT);
 990
 991	/* Setup 2eSST speeds */
 992	temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
 993	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 994	case VME_2eSST160:
 995		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
 996		break;
 997	case VME_2eSST267:
 998		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
 999		break;
1000	case VME_2eSST320:
1001		temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1002		break;
1003	}
1004
1005	/* Setup cycle types */
1006	if (cycle & VME_BLT) {
1007		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1008		temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1009	}
1010	if (cycle & VME_MBLT) {
1011		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1012		temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1013	}
1014	if (cycle & VME_2eVME) {
1015		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1016		temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1017	}
1018	if (cycle & VME_2eSST) {
1019		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1020		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1021	}
1022	if (cycle & VME_2eSSTB) {
1023		dev_warn(tsi148_bridge->parent, "Currently not setting "
1024			"Broadcast Select Registers\n");
1025		temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1026		temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1027	}
1028
1029	/* Setup data width */
1030	temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1031	switch (dwidth) {
1032	case VME_D16:
1033		temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1034		break;
1035	case VME_D32:
1036		temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1037		break;
1038	default:
1039		spin_unlock(&image->lock);
1040		dev_err(tsi148_bridge->parent, "Invalid data width\n");
1041		retval = -EINVAL;
1042		goto err_dwidth;
1043	}
1044
1045	/* Setup address space */
1046	temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1047	switch (aspace) {
1048	case VME_A16:
1049		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1050		break;
1051	case VME_A24:
1052		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1053		break;
1054	case VME_A32:
1055		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1056		break;
1057	case VME_A64:
1058		temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1059		break;
1060	case VME_CRCSR:
1061		temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1062		break;
1063	case VME_USER1:
1064		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1065		break;
1066	case VME_USER2:
1067		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1068		break;
1069	case VME_USER3:
1070		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1071		break;
1072	case VME_USER4:
1073		temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1074		break;
1075	default:
1076		spin_unlock(&image->lock);
1077		dev_err(tsi148_bridge->parent, "Invalid address space\n");
1078		retval = -EINVAL;
1079		goto err_aspace;
1080		break;
1081	}
1082
1083	temp_ctl &= ~(3<<4);
1084	if (cycle & VME_SUPER)
1085		temp_ctl |= TSI148_LCSR_OTAT_SUP;
1086	if (cycle & VME_PROG)
1087		temp_ctl |= TSI148_LCSR_OTAT_PGM;
1088
1089	/* Setup mapping */
1090	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1091		TSI148_LCSR_OFFSET_OTSAU);
1092	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1093		TSI148_LCSR_OFFSET_OTSAL);
1094	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1095		TSI148_LCSR_OFFSET_OTEAU);
1096	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1097		TSI148_LCSR_OFFSET_OTEAL);
1098	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1099		TSI148_LCSR_OFFSET_OTOFU);
1100	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1101		TSI148_LCSR_OFFSET_OTOFL);
1102
1103	/* Write ctl reg without enable */
1104	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1105		TSI148_LCSR_OFFSET_OTAT);
1106
1107	if (enabled)
1108		temp_ctl |= TSI148_LCSR_OTAT_EN;
1109
1110	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1111		TSI148_LCSR_OFFSET_OTAT);
1112
1113	spin_unlock(&image->lock);
1114	return 0;
1115
1116err_aspace:
1117err_dwidth:
1118err_gran:
1119	tsi148_free_resource(image);
1120err_res:
1121err_window:
1122	return retval;
1123
1124}
1125
1126/*
1127 * Set the attributes of an outbound window.
1128 *
1129 * XXX Not parsing prefetch information.
1130 */
1131static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1132	unsigned long long *vme_base, unsigned long long *size,
1133	vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1134{
1135	unsigned int i, ctl;
1136	unsigned int pci_base_low, pci_base_high;
1137	unsigned int pci_bound_low, pci_bound_high;
1138	unsigned int vme_offset_low, vme_offset_high;
1139
1140	unsigned long long pci_base, pci_bound, vme_offset;
1141	struct tsi148_driver *bridge;
1142
1143	bridge = image->parent->driver_priv;
1144
1145	i = image->number;
1146
1147	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1148		TSI148_LCSR_OFFSET_OTAT);
1149
1150	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1151		TSI148_LCSR_OFFSET_OTSAU);
1152	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1153		TSI148_LCSR_OFFSET_OTSAL);
1154	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1155		TSI148_LCSR_OFFSET_OTEAU);
1156	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1157		TSI148_LCSR_OFFSET_OTEAL);
1158	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1159		TSI148_LCSR_OFFSET_OTOFU);
1160	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1161		TSI148_LCSR_OFFSET_OTOFL);
1162
1163	/* Convert 64-bit variables to 2x 32-bit variables */
1164	reg_join(pci_base_high, pci_base_low, &pci_base);
1165	reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1166	reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1167
1168	*vme_base = pci_base + vme_offset;
1169	*size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1170
1171	*enabled = 0;
1172	*aspace = 0;
1173	*cycle = 0;
1174	*dwidth = 0;
1175
1176	if (ctl & TSI148_LCSR_OTAT_EN)
1177		*enabled = 1;
1178
1179	/* Setup address space */
1180	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1181		*aspace |= VME_A16;
1182	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1183		*aspace |= VME_A24;
1184	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1185		*aspace |= VME_A32;
1186	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1187		*aspace |= VME_A64;
1188	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1189		*aspace |= VME_CRCSR;
1190	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1191		*aspace |= VME_USER1;
1192	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1193		*aspace |= VME_USER2;
1194	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1195		*aspace |= VME_USER3;
1196	if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1197		*aspace |= VME_USER4;
1198
1199	/* Setup 2eSST speeds */
1200	if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1201		*cycle |= VME_2eSST160;
1202	if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1203		*cycle |= VME_2eSST267;
1204	if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1205		*cycle |= VME_2eSST320;
1206
1207	/* Setup cycle types */
1208	if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1209		*cycle |= VME_SCT;
1210	if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1211		*cycle |= VME_BLT;
1212	if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1213		*cycle |= VME_MBLT;
1214	if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1215		*cycle |= VME_2eVME;
1216	if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1217		*cycle |= VME_2eSST;
1218	if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1219		*cycle |= VME_2eSSTB;
1220
1221	if (ctl & TSI148_LCSR_OTAT_SUP)
1222		*cycle |= VME_SUPER;
1223	else
1224		*cycle |= VME_USER;
1225
1226	if (ctl & TSI148_LCSR_OTAT_PGM)
1227		*cycle |= VME_PROG;
1228	else
1229		*cycle |= VME_DATA;
1230
1231	/* Setup data width */
1232	if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1233		*dwidth = VME_D16;
1234	if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1235		*dwidth = VME_D32;
1236
1237	return 0;
1238}
1239
1240
1241static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1242	unsigned long long *vme_base, unsigned long long *size,
1243	vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1244{
1245	int retval;
1246
1247	spin_lock(&image->lock);
1248
1249	retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1250		cycle, dwidth);
1251
1252	spin_unlock(&image->lock);
1253
1254	return retval;
1255}
1256
1257static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1258	size_t count, loff_t offset)
1259{
1260	int retval, enabled;
1261	unsigned long long vme_base, size;
1262	vme_address_t aspace;
1263	vme_cycle_t cycle;
1264	vme_width_t dwidth;
1265	struct vme_bus_error *vme_err = NULL;
1266	struct vme_bridge *tsi148_bridge;
1267
1268	tsi148_bridge = image->parent;
1269
1270	spin_lock(&image->lock);
1271
1272	memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1273	retval = count;
1274
1275	if (!err_chk)
1276		goto skip_chk;
1277
1278	__tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1279		&dwidth);
1280
1281	vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1282		count);
1283	if (vme_err != NULL) {
1284		dev_err(image->parent->parent, "First VME read error detected "
1285			"an at address 0x%llx\n", vme_err->address);
1286		retval = vme_err->address - (vme_base + offset);
1287		/* Clear down save errors in this address range */
1288		tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1289			count);
1290	}
1291
1292skip_chk:
1293	spin_unlock(&image->lock);
1294
1295	return retval;
1296}
1297
1298
1299static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1300	size_t count, loff_t offset)
1301{
1302	int retval = 0, enabled;
1303	unsigned long long vme_base, size;
1304	vme_address_t aspace;
1305	vme_cycle_t cycle;
1306	vme_width_t dwidth;
1307
1308	struct vme_bus_error *vme_err = NULL;
1309	struct vme_bridge *tsi148_bridge;
1310	struct tsi148_driver *bridge;
1311
1312	tsi148_bridge = image->parent;
1313
1314	bridge = tsi148_bridge->driver_priv;
1315
1316	spin_lock(&image->lock);
1317
1318	memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1319	retval = count;
1320
1321	/*
1322	 * Writes are posted. We need to do a read on the VME bus to flush out
1323	 * all of the writes before we check for errors. We can't guarantee
1324	 * that reading the data we have just written is safe. It is believed
1325	 * that there isn't any read, write re-ordering, so we can read any
1326	 * location in VME space, so lets read the Device ID from the tsi148's
1327	 * own registers as mapped into CR/CSR space.
1328	 *
1329	 * We check for saved errors in the written address range/space.
1330	 */
1331
1332	if (!err_chk)
1333		goto skip_chk;
1334
1335	/*
1336	 * Get window info first, to maximise the time that the buffers may
1337	 * fluch on their own
1338	 */
1339	__tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1340		&dwidth);
1341
1342	ioread16(bridge->flush_image->kern_base + 0x7F000);
1343
1344	vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1345		count);
1346	if (vme_err != NULL) {
1347		dev_warn(tsi148_bridge->parent, "First VME write error detected"
1348			" an at address 0x%llx\n", vme_err->address);
1349		retval = vme_err->address - (vme_base + offset);
1350		/* Clear down save errors in this address range */
1351		tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1352			count);
1353	}
1354
1355skip_chk:
1356	spin_unlock(&image->lock);
1357
1358	return retval;
1359}
1360
1361/*
1362 * Perform an RMW cycle on the VME bus.
1363 *
1364 * Requires a previously configured master window, returns final value.
1365 */
1366static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1367	unsigned int mask, unsigned int compare, unsigned int swap,
1368	loff_t offset)
1369{
1370	unsigned long long pci_addr;
1371	unsigned int pci_addr_high, pci_addr_low;
1372	u32 tmp, result;
1373	int i;
1374	struct tsi148_driver *bridge;
1375
1376	bridge = image->parent->driver_priv;
1377
1378	/* Find the PCI address that maps to the desired VME address */
1379	i = image->number;
1380
1381	/* Locking as we can only do one of these at a time */
1382	mutex_lock(&bridge->vme_rmw);
1383
1384	/* Lock image */
1385	spin_lock(&image->lock);
1386
1387	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1388		TSI148_LCSR_OFFSET_OTSAU);
1389	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1390		TSI148_LCSR_OFFSET_OTSAL);
1391
1392	reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1393	reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1394
1395	/* Configure registers */
1396	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1397	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1398	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1399	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1400	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1401
1402	/* Enable RMW */
1403	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1404	tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1405	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1406
1407	/* Kick process off with a read to the required address. */
1408	result = ioread32be(image->kern_base + offset);
1409
1410	/* Disable RMW */
1411	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1412	tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1413	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1414
1415	spin_unlock(&image->lock);
1416
1417	mutex_unlock(&bridge->vme_rmw);
1418
1419	return result;
1420}
1421
1422static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr,
1423	vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1424{
1425	/* Setup 2eSST speeds */
1426	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1427	case VME_2eSST160:
1428		*attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1429		break;
1430	case VME_2eSST267:
1431		*attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1432		break;
1433	case VME_2eSST320:
1434		*attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1435		break;
1436	}
1437
1438	/* Setup cycle types */
1439	if (cycle & VME_SCT)
1440		*attr |= TSI148_LCSR_DSAT_TM_SCT;
1441
1442	if (cycle & VME_BLT)
1443		*attr |= TSI148_LCSR_DSAT_TM_BLT;
1444
1445	if (cycle & VME_MBLT)
1446		*attr |= TSI148_LCSR_DSAT_TM_MBLT;
1447
1448	if (cycle & VME_2eVME)
1449		*attr |= TSI148_LCSR_DSAT_TM_2eVME;
1450
1451	if (cycle & VME_2eSST)
1452		*attr |= TSI148_LCSR_DSAT_TM_2eSST;
1453
1454	if (cycle & VME_2eSSTB) {
1455		dev_err(dev, "Currently not setting Broadcast Select "
1456			"Registers\n");
1457		*attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1458	}
1459
1460	/* Setup data width */
1461	switch (dwidth) {
1462	case VME_D16:
1463		*attr |= TSI148_LCSR_DSAT_DBW_16;
1464		break;
1465	case VME_D32:
1466		*attr |= TSI148_LCSR_DSAT_DBW_32;
1467		break;
1468	default:
1469		dev_err(dev, "Invalid data width\n");
1470		return -EINVAL;
1471	}
1472
1473	/* Setup address space */
1474	switch (aspace) {
1475	case VME_A16:
1476		*attr |= TSI148_LCSR_DSAT_AMODE_A16;
1477		break;
1478	case VME_A24:
1479		*attr |= TSI148_LCSR_DSAT_AMODE_A24;
1480		break;
1481	case VME_A32:
1482		*attr |= TSI148_LCSR_DSAT_AMODE_A32;
1483		break;
1484	case VME_A64:
1485		*attr |= TSI148_LCSR_DSAT_AMODE_A64;
1486		break;
1487	case VME_CRCSR:
1488		*attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1489		break;
1490	case VME_USER1:
1491		*attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1492		break;
1493	case VME_USER2:
1494		*attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1495		break;
1496	case VME_USER3:
1497		*attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1498		break;
1499	case VME_USER4:
1500		*attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1501		break;
1502	default:
1503		dev_err(dev, "Invalid address space\n");
1504		return -EINVAL;
1505		break;
1506	}
1507
1508	if (cycle & VME_SUPER)
1509		*attr |= TSI148_LCSR_DSAT_SUP;
1510	if (cycle & VME_PROG)
1511		*attr |= TSI148_LCSR_DSAT_PGM;
1512
1513	return 0;
1514}
1515
1516static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
1517	vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1518{
1519	/* Setup 2eSST speeds */
1520	switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1521	case VME_2eSST160:
1522		*attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1523		break;
1524	case VME_2eSST267:
1525		*attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1526		break;
1527	case VME_2eSST320:
1528		*attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1529		break;
1530	}
1531
1532	/* Setup cycle types */
1533	if (cycle & VME_SCT)
1534		*attr |= TSI148_LCSR_DDAT_TM_SCT;
1535
1536	if (cycle & VME_BLT)
1537		*attr |= TSI148_LCSR_DDAT_TM_BLT;
1538
1539	if (cycle & VME_MBLT)
1540		*attr |= TSI148_LCSR_DDAT_TM_MBLT;
1541
1542	if (cycle & VME_2eVME)
1543		*attr |= TSI148_LCSR_DDAT_TM_2eVME;
1544
1545	if (cycle & VME_2eSST)
1546		*attr |= TSI148_LCSR_DDAT_TM_2eSST;
1547
1548	if (cycle & VME_2eSSTB) {
1549		dev_err(dev, "Currently not setting Broadcast Select "
1550			"Registers\n");
1551		*attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1552	}
1553
1554	/* Setup data width */
1555	switch (dwidth) {
1556	case VME_D16:
1557		*attr |= TSI148_LCSR_DDAT_DBW_16;
1558		break;
1559	case VME_D32:
1560		*attr |= TSI148_LCSR_DDAT_DBW_32;
1561		break;
1562	default:
1563		dev_err(dev, "Invalid data width\n");
1564		return -EINVAL;
1565	}
1566
1567	/* Setup address space */
1568	switch (aspace) {
1569	case VME_A16:
1570		*attr |= TSI148_LCSR_DDAT_AMODE_A16;
1571		break;
1572	case VME_A24:
1573		*attr |= TSI148_LCSR_DDAT_AMODE_A24;
1574		break;
1575	case VME_A32:
1576		*attr |= TSI148_LCSR_DDAT_AMODE_A32;
1577		break;
1578	case VME_A64:
1579		*attr |= TSI148_LCSR_DDAT_AMODE_A64;
1580		break;
1581	case VME_CRCSR:
1582		*attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1583		break;
1584	case VME_USER1:
1585		*attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1586		break;
1587	case VME_USER2:
1588		*attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1589		break;
1590	case VME_USER3:
1591		*attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1592		break;
1593	case VME_USER4:
1594		*attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1595		break;
1596	default:
1597		dev_err(dev, "Invalid address space\n");
1598		return -EINVAL;
1599		break;
1600	}
1601
1602	if (cycle & VME_SUPER)
1603		*attr |= TSI148_LCSR_DDAT_SUP;
1604	if (cycle & VME_PROG)
1605		*attr |= TSI148_LCSR_DDAT_PGM;
1606
1607	return 0;
1608}
1609
1610/*
1611 * Add a link list descriptor to the list
1612 */
1613static int tsi148_dma_list_add(struct vme_dma_list *list,
1614	struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1615{
1616	struct tsi148_dma_entry *entry, *prev;
1617	u32 address_high, address_low;
1618	struct vme_dma_pattern *pattern_attr;
1619	struct vme_dma_pci *pci_attr;
1620	struct vme_dma_vme *vme_attr;
1621	dma_addr_t desc_ptr;
1622	int retval = 0;
1623	struct vme_bridge *tsi148_bridge;
1624
1625	tsi148_bridge = list->parent->parent;
1626
1627	/* Descriptor must be aligned on 64-bit boundaries */
1628	entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1629	if (entry == NULL) {
1630		dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1631			"dma resource structure\n");
1632		retval = -ENOMEM;
1633		goto err_mem;
1634	}
1635
1636	/* Test descriptor alignment */
1637	if ((unsigned long)&entry->descriptor & 0x7) {
1638		dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1639			"byte boundary as required: %p\n",
1640			&entry->descriptor);
1641		retval = -EINVAL;
1642		goto err_align;
1643	}
1644
1645	/* Given we are going to fill out the structure, we probably don't
1646	 * need to zero it, but better safe than sorry for now.
1647	 */
1648	memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
1649
1650	/* Fill out source part */
1651	switch (src->type) {
1652	case VME_DMA_PATTERN:
1653		pattern_attr = src->private;
1654
1655		entry->descriptor.dsal = pattern_attr->pattern;
1656		entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1657		/* Default behaviour is 32 bit pattern */
1658		if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1659			entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1660
1661		/* It seems that the default behaviour is to increment */
1662		if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1663			entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1664
1665		break;
1666	case VME_DMA_PCI:
1667		pci_attr = src->private;
1668
1669		reg_split((unsigned long long)pci_attr->address, &address_high,
1670			&address_low);
1671		entry->descriptor.dsau = address_high;
1672		entry->descriptor.dsal = address_low;
1673		entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1674		break;
1675	case VME_DMA_VME:
1676		vme_attr = src->private;
1677
1678		reg_split((unsigned long long)vme_attr->address, &address_high,
1679			&address_low);
1680		entry->descriptor.dsau = address_high;
1681		entry->descriptor.dsal = address_low;
1682		entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1683
1684		retval = tsi148_dma_set_vme_src_attributes(
1685			tsi148_bridge->parent, &entry->descriptor.dsat,
1686			vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1687		if (retval < 0)
1688			goto err_source;
1689		break;
1690	default:
1691		dev_err(tsi148_bridge->parent, "Invalid source type\n");
1692		retval = -EINVAL;
1693		goto err_source;
1694		break;
1695	}
1696
1697	/* Assume last link - this will be over-written by adding another */
1698	entry->descriptor.dnlau = 0;
1699	entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1700
1701
1702	/* Fill out destination part */
1703	switch (dest->type) {
1704	case VME_DMA_PCI:
1705		pci_attr = dest->private;
1706
1707		reg_split((unsigned long long)pci_attr->address, &address_high,
1708			&address_low);
1709		entry->descriptor.ddau = address_high;
1710		entry->descriptor.ddal = address_low;
1711		entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1712		break;
1713	case VME_DMA_VME:
1714		vme_attr = dest->private;
1715
1716		reg_split((unsigned long long)vme_attr->address, &address_high,
1717			&address_low);
1718		entry->descriptor.ddau = address_high;
1719		entry->descriptor.ddal = address_low;
1720		entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1721
1722		retval = tsi148_dma_set_vme_dest_attributes(
1723			tsi148_bridge->parent, &entry->descriptor.ddat,
1724			vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1725		if (retval < 0)
1726			goto err_dest;
1727		break;
1728	default:
1729		dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1730		retval = -EINVAL;
1731		goto err_dest;
1732		break;
1733	}
1734
1735	/* Fill out count */
1736	entry->descriptor.dcnt = (u32)count;
1737
1738	/* Add to list */
1739	list_add_tail(&entry->list, &list->entries);
1740
1741	/* Fill out previous descriptors "Next Address" */
1742	if (entry->list.prev != &list->entries) {
1743		prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1744			list);
1745		/* We need the bus address for the pointer */
1746		desc_ptr = virt_to_bus(&entry->descriptor);
1747		reg_split(desc_ptr, &prev->descriptor.dnlau,
1748			&prev->descriptor.dnlal);
1749	}
1750
1751	return 0;
1752
1753err_dest:
1754err_source:
1755err_align:
1756		kfree(entry);
1757err_mem:
1758	return retval;
1759}
1760
1761/*
1762 * Check to see if the provided DMA channel is busy.
1763 */
1764static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1765{
1766	u32 tmp;
1767	struct tsi148_driver *bridge;
1768
1769	bridge = tsi148_bridge->driver_priv;
1770
1771	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1772		TSI148_LCSR_OFFSET_DSTA);
1773
1774	if (tmp & TSI148_LCSR_DSTA_BSY)
1775		return 0;
1776	else
1777		return 1;
1778
1779}
1780
1781/*
1782 * Execute a previously generated link list
1783 *
1784 * XXX Need to provide control register configuration.
1785 */
1786static int tsi148_dma_list_exec(struct vme_dma_list *list)
1787{
1788	struct vme_dma_resource *ctrlr;
1789	int channel, retval = 0;
1790	struct tsi148_dma_entry *entry;
1791	dma_addr_t bus_addr;
1792	u32 bus_addr_high, bus_addr_low;
1793	u32 val, dctlreg = 0;
1794	struct vme_bridge *tsi148_bridge;
1795	struct tsi148_driver *bridge;
1796
1797	ctrlr = list->parent;
1798
1799	tsi148_bridge = ctrlr->parent;
1800
1801	bridge = tsi148_bridge->driver_priv;
1802
1803	mutex_lock(&ctrlr->mtx);
1804
1805	channel = ctrlr->number;
1806
1807	if (!list_empty(&ctrlr->running)) {
1808		/*
1809		 * XXX We have an active DMA transfer and currently haven't
1810		 *     sorted out the mechanism for "pending" DMA transfers.
1811		 *     Return busy.
1812		 */
1813		/* Need to add to pending here */
1814		mutex_unlock(&ctrlr->mtx);
1815		return -EBUSY;
1816	} else {
1817		list_add(&list->list, &ctrlr->running);
1818	}
1819
1820	/* Get first bus address and write into registers */
1821	entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
1822		list);
1823
1824	bus_addr = virt_to_bus(&entry->descriptor);
1825
1826	mutex_unlock(&ctrlr->mtx);
1827
1828	reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1829
1830	iowrite32be(bus_addr_high, bridge->base +
1831		TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1832	iowrite32be(bus_addr_low, bridge->base +
1833		TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1834
1835	/* Start the operation */
1836	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1837		TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1838
1839	wait_event_interruptible(bridge->dma_queue[channel],
1840		tsi148_dma_busy(ctrlr->parent, channel));
1841	/*
1842	 * Read status register, this register is valid until we kick off a
1843	 * new transfer.
1844	 */
1845	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1846		TSI148_LCSR_OFFSET_DSTA);
1847
1848	if (val & TSI148_LCSR_DSTA_VBE) {
1849		dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1850		retval = -EIO;
1851	}
1852
1853	/* Remove list from running list */
1854	mutex_lock(&ctrlr->mtx);
1855	list_del(&list->list);
1856	mutex_unlock(&ctrlr->mtx);
1857
1858	return retval;
1859}
1860
1861/*
1862 * Clean up a previously generated link list
1863 *
1864 * We have a separate function, don't assume that the chain can't be reused.
1865 */
1866static int tsi148_dma_list_empty(struct vme_dma_list *list)
1867{
1868	struct list_head *pos, *temp;
1869	struct tsi148_dma_entry *entry;
1870
1871	/* detach and free each entry */
1872	list_for_each_safe(pos, temp, &list->entries) {
1873		list_del(pos);
1874		entry = list_entry(pos, struct tsi148_dma_entry, list);
1875		kfree(entry);
1876	}
1877
1878	return 0;
1879}
1880
1881/*
1882 * All 4 location monitors reside at the same base - this is therefore a
1883 * system wide configuration.
1884 *
1885 * This does not enable the LM monitor - that shoul…

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