/drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c
C | 783 lines | 471 code | 141 blank | 171 comment | 105 complexity | 36b64b5f2a213895c7ebe4b05e274b85 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1//------------------------------------------------------------------------------
2// <copyright file="ar6k_events.c" company="Atheros">
3// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
4//
5//
6// Permission to use, copy, modify, and/or distribute this software for any
7// purpose with or without fee is hereby granted, provided that the above
8// copyright notice and this permission notice appear in all copies.
9//
10// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17//
18//
19//------------------------------------------------------------------------------
20//==============================================================================
21// AR6K Driver layer event handling (i.e. interrupts, message polling)
22//
23// Author(s): ="Atheros"
24//==============================================================================
25
26#include "a_config.h"
27#include "athdefs.h"
28#include "hw/mbox_host_reg.h"
29#include "a_osapi.h"
30#include "../htc_debug.h"
31#include "hif.h"
32#include "htc_packet.h"
33#include "ar6k.h"
34
35extern void AR6KFreeIOPacket(struct ar6k_device *pDev, struct htc_packet *pPacket);
36extern struct htc_packet *AR6KAllocIOPacket(struct ar6k_device *pDev);
37
38static int DevServiceDebugInterrupt(struct ar6k_device *pDev);
39
40#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
41
42/* completion routine for ALL HIF layer async I/O */
43int DevRWCompletionHandler(void *context, int status)
44{
45 struct htc_packet *pPacket = (struct htc_packet *)context;
46
47 AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
48 ("+DevRWCompletionHandler (Pkt:0x%lX) , Status: %d \n",
49 (unsigned long)pPacket,
50 status));
51
52 COMPLETE_HTC_PACKET(pPacket,status);
53
54 AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
55 ("-DevRWCompletionHandler\n"));
56
57 return 0;
58}
59
60/* mailbox recv message polling */
61int DevPollMboxMsgRecv(struct ar6k_device *pDev,
62 u32 *pLookAhead,
63 int TimeoutMS)
64{
65 int status = 0;
66 int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
67
68 A_ASSERT(timeout > 0);
69
70 AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
71
72 while (true) {
73
74 if (pDev->GetPendingEventsFunc != NULL) {
75
76 struct hif_pending_events_info events;
77
78#ifdef THREAD_X
79 events.Polling =1;
80#endif
81
82 /* the HIF layer uses a special mechanism to get events, do this
83 * synchronously */
84 status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
85 &events,
86 NULL);
87 if (status)
88 {
89 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
90 break;
91 }
92
93 if (events.Events & HIF_RECV_MSG_AVAIL)
94 {
95 /* there is a message available, the lookahead should be valid now */
96 *pLookAhead = events.LookAhead;
97
98 break;
99 }
100 } else {
101
102 /* this is the standard HIF way.... */
103 /* load the register table */
104 status = HIFReadWrite(pDev->HIFDevice,
105 HOST_INT_STATUS_ADDRESS,
106 (u8 *)&pDev->IrqProcRegisters,
107 AR6K_IRQ_PROC_REGS_SIZE,
108 HIF_RD_SYNC_BYTE_INC,
109 NULL);
110
111 if (status){
112 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
113 break;
114 }
115
116 /* check for MBOX data and valid lookahead */
117 if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) {
118 if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
119 {
120 /* mailbox has a message and the look ahead is valid */
121 *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
122 break;
123 }
124 }
125
126 }
127
128 timeout--;
129
130 if (timeout <= 0) {
131 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
132 status = A_ERROR;
133
134 /* check if the target asserted */
135 if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
136 /* target signaled an assert, process this pending interrupt
137 * this will call the target failure handler */
138 DevServiceDebugInterrupt(pDev);
139 }
140
141 break;
142 }
143
144 /* delay a little */
145 A_MDELAY(DELAY_PER_INTERVAL_MS);
146 AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout));
147 }
148
149 AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
150
151 return status;
152}
153
154static int DevServiceCPUInterrupt(struct ar6k_device *pDev)
155{
156 int status;
157 u8 cpu_int_status;
158 u8 regBuffer[4];
159
160 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
161 cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
162 pDev->IrqEnableRegisters.cpu_int_status_enable;
163 A_ASSERT(cpu_int_status);
164 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
165 ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
166 cpu_int_status));
167
168 /* Clear the interrupt */
169 pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
170
171 /* set up the register transfer buffer to hit the register 4 times , this is done
172 * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
173 * restrict bus transfer lengths to be a multiple of 4-bytes */
174
175 /* set W1C value to clear the interrupt, this hits the register first */
176 regBuffer[0] = cpu_int_status;
177 /* the remaining 4 values are set to zero which have no-effect */
178 regBuffer[1] = 0;
179 regBuffer[2] = 0;
180 regBuffer[3] = 0;
181
182 status = HIFReadWrite(pDev->HIFDevice,
183 CPU_INT_STATUS_ADDRESS,
184 regBuffer,
185 4,
186 HIF_WR_SYNC_BYTE_FIX,
187 NULL);
188
189 A_ASSERT(status == 0);
190 return status;
191}
192
193
194static int DevServiceErrorInterrupt(struct ar6k_device *pDev)
195{
196 int status;
197 u8 error_int_status;
198 u8 regBuffer[4];
199
200 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
201 error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
202 A_ASSERT(error_int_status);
203 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
204 ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
205 error_int_status));
206
207 if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
208 /* Wakeup */
209 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
210 }
211
212 if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
213 /* Rx Underflow */
214 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
215 }
216
217 if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
218 /* Tx Overflow */
219 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
220 }
221
222 /* Clear the interrupt */
223 pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
224
225 /* set up the register transfer buffer to hit the register 4 times , this is done
226 * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
227 * restrict bus transfer lengths to be a multiple of 4-bytes */
228
229 /* set W1C value to clear the interrupt, this hits the register first */
230 regBuffer[0] = error_int_status;
231 /* the remaining 4 values are set to zero which have no-effect */
232 regBuffer[1] = 0;
233 regBuffer[2] = 0;
234 regBuffer[3] = 0;
235
236 status = HIFReadWrite(pDev->HIFDevice,
237 ERROR_INT_STATUS_ADDRESS,
238 regBuffer,
239 4,
240 HIF_WR_SYNC_BYTE_FIX,
241 NULL);
242
243 A_ASSERT(status == 0);
244 return status;
245}
246
247static int DevServiceDebugInterrupt(struct ar6k_device *pDev)
248{
249 u32 dummy;
250 int status;
251
252 /* Send a target failure event to the application */
253 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
254
255 if (pDev->TargetFailureCallback != NULL) {
256 pDev->TargetFailureCallback(pDev->HTCContext);
257 }
258
259 if (pDev->GMboxEnabled) {
260 DevNotifyGMboxTargetFailure(pDev);
261 }
262
263 /* clear the interrupt , the debug error interrupt is
264 * counter 0 */
265 /* read counter to clear interrupt */
266 status = HIFReadWrite(pDev->HIFDevice,
267 COUNT_DEC_ADDRESS,
268 (u8 *)&dummy,
269 4,
270 HIF_RD_SYNC_BYTE_INC,
271 NULL);
272
273 A_ASSERT(status == 0);
274 return status;
275}
276
277static int DevServiceCounterInterrupt(struct ar6k_device *pDev)
278{
279 u8 counter_int_status;
280
281 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
282
283 counter_int_status = pDev->IrqProcRegisters.counter_int_status &
284 pDev->IrqEnableRegisters.counter_int_status_enable;
285
286 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
287 ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
288 counter_int_status));
289
290 /* Check if the debug interrupt is pending
291 * NOTE: other modules like GMBOX may use the counter interrupt for
292 * credit flow control on other counters, we only need to check for the debug assertion
293 * counter interrupt */
294 if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
295 return DevServiceDebugInterrupt(pDev);
296 }
297
298 return 0;
299}
300
301/* callback when our fetch to get interrupt status registers completes */
302static void DevGetEventAsyncHandler(void *Context, struct htc_packet *pPacket)
303{
304 struct ar6k_device *pDev = (struct ar6k_device *)Context;
305 u32 lookAhead = 0;
306 bool otherInts = false;
307
308 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
309
310 do {
311
312 if (pPacket->Status) {
313 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
314 (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
315 /* bail out, don't unmask HIF interrupt */
316 break;
317 }
318
319 if (pDev->GetPendingEventsFunc != NULL) {
320 /* the HIF layer collected the information for us */
321 struct hif_pending_events_info *pEvents = (struct hif_pending_events_info *)pPacket->pBuffer;
322 if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
323 lookAhead = pEvents->LookAhead;
324 if (0 == lookAhead) {
325 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
326 }
327 }
328 if (pEvents->Events & HIF_OTHER_EVENTS) {
329 otherInts = true;
330 }
331 } else {
332 /* standard interrupt table handling.... */
333 struct ar6k_irq_proc_registers *pReg = (struct ar6k_irq_proc_registers *)pPacket->pBuffer;
334 u8 host_int_status;
335
336 host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
337
338 if (host_int_status & (1 << HTC_MAILBOX)) {
339 host_int_status &= ~(1 << HTC_MAILBOX);
340 if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
341 /* mailbox has a message and the look ahead is valid */
342 lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
343 if (0 == lookAhead) {
344 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
345 }
346 }
347 }
348
349 if (host_int_status) {
350 /* there are other interrupts to handle */
351 otherInts = true;
352 }
353 }
354
355 if (otherInts || (lookAhead == 0)) {
356 /* if there are other interrupts to process, we cannot do this in the async handler so
357 * ack the interrupt which will cause our sync handler to run again
358 * if however there are no more messages, we can now ack the interrupt */
359 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
360 (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
361 otherInts, lookAhead));
362 HIFAckInterrupt(pDev->HIFDevice);
363 } else {
364 int fetched = 0;
365 int status;
366
367 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
368 (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
369 lookAhead));
370 /* lookahead is non-zero and there are no other interrupts to service,
371 * go get the next message */
372 status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched);
373
374 if (!status && !fetched) {
375 /* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */
376 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n"));
377 DevAsyncIrqProcessComplete(pDev);
378 }
379 }
380
381 } while (false);
382
383 /* free this IO packet */
384 AR6KFreeIOPacket(pDev,pPacket);
385 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
386}
387
388/* called by the HTC layer when it wants us to check if the device has any more pending
389 * recv messages, this starts off a series of async requests to read interrupt registers */
390int DevCheckPendingRecvMsgsAsync(void *context)
391{
392 struct ar6k_device *pDev = (struct ar6k_device *)context;
393 int status = 0;
394 struct htc_packet *pIOPacket;
395
396 /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
397 * cause us to switch contexts */
398
399 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%lX)\n", (unsigned long)pDev));
400
401 do {
402
403 if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
404 /* break the async processing chain right here, no need to continue.
405 * The DevDsrHandler() will handle things in a loop when things are driven
406 * synchronously */
407 break;
408 }
409
410 /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
411 * the target, if upper layers determine that we are in a low-throughput mode, we can
412 * rely on taking another interrupt rather than re-checking the status registers which can
413 * re-wake the target */
414 if (pDev->RecheckIRQStatusCnt == 0) {
415 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
416 /* ack interrupt */
417 HIFAckInterrupt(pDev->HIFDevice);
418 break;
419 }
420
421 /* first allocate one of our HTC packets we created for async I/O
422 * we reuse HTC packet definitions so that we can use the completion mechanism
423 * in DevRWCompletionHandler() */
424 pIOPacket = AR6KAllocIOPacket(pDev);
425
426 if (NULL == pIOPacket) {
427 /* there should be only 1 asynchronous request out at a time to read these registers
428 * so this should actually never happen */
429 status = A_NO_MEMORY;
430 A_ASSERT(false);
431 break;
432 }
433
434 /* stick in our completion routine when the I/O operation completes */
435 pIOPacket->Completion = DevGetEventAsyncHandler;
436 pIOPacket->pContext = pDev;
437
438 if (pDev->GetPendingEventsFunc) {
439 /* HIF layer has it's own mechanism, pass the IO to it.. */
440 status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
441 (struct hif_pending_events_info *)pIOPacket->pBuffer,
442 pIOPacket);
443
444 } else {
445 /* standard way, read the interrupt register table asynchronously again */
446 status = HIFReadWrite(pDev->HIFDevice,
447 HOST_INT_STATUS_ADDRESS,
448 pIOPacket->pBuffer,
449 AR6K_IRQ_PROC_REGS_SIZE,
450 HIF_RD_ASYNC_BYTE_INC,
451 pIOPacket);
452 }
453
454 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
455 } while (false);
456
457 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
458
459 return status;
460}
461
462void DevAsyncIrqProcessComplete(struct ar6k_device *pDev)
463{
464 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
465 HIFAckInterrupt(pDev->HIFDevice);
466}
467
468/* process pending interrupts synchronously */
469static int ProcessPendingIRQs(struct ar6k_device *pDev, bool *pDone, bool *pASyncProcessing)
470{
471 int status = 0;
472 u8 host_int_status = 0;
473 u32 lookAhead = 0;
474
475 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%lX)\n", (unsigned long)pDev));
476
477 /*** NOTE: the HIF implementation guarantees that the context of this call allows
478 * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
479 * can block or switch thread/task ontexts.
480 * This is a fully schedulable context.
481 * */
482 do {
483
484 if (pDev->IrqEnableRegisters.int_status_enable == 0) {
485 /* interrupt enables have been cleared, do not try to process any pending interrupts that
486 * may result in more bus transactions. The target may be unresponsive at this
487 * point. */
488 break;
489 }
490
491 if (pDev->GetPendingEventsFunc != NULL) {
492 struct hif_pending_events_info events;
493
494#ifdef THREAD_X
495 events.Polling= 0;
496#endif
497 /* the HIF layer uses a special mechanism to get events
498 * get this synchronously */
499 status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
500 &events,
501 NULL);
502
503 if (status) {
504 break;
505 }
506
507 if (events.Events & HIF_RECV_MSG_AVAIL) {
508 lookAhead = events.LookAhead;
509 if (0 == lookAhead) {
510 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
511 }
512 }
513
514 if (!(events.Events & HIF_OTHER_EVENTS) ||
515 !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
516 /* no need to read the register table, no other interesting interrupts.
517 * Some interfaces (like SPI) can shadow interrupt sources without
518 * requiring the host to do a full table read */
519 break;
520 }
521
522 /* otherwise fall through and read the register table */
523 }
524
525 /*
526 * Read the first 28 bytes of the HTC register table. This will yield us
527 * the value of different int status registers and the lookahead
528 * registers.
529 * length = sizeof(int_status) + sizeof(cpu_int_status) +
530 * sizeof(error_int_status) + sizeof(counter_int_status) +
531 * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
532 * sizeof(hole) + sizeof(rx_lookahead) +
533 * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
534 * sizeof(error_status_enable) +
535 * sizeof(counter_int_status_enable);
536 *
537 */
538#ifdef CONFIG_MMC_SDHCI_S3C
539 pDev->IrqProcRegisters.host_int_status = 0;
540 pDev->IrqProcRegisters.rx_lookahead_valid = 0;
541 pDev->IrqProcRegisters.host_int_status2 = 0;
542 pDev->IrqProcRegisters.rx_lookahead[0] = 0;
543 pDev->IrqProcRegisters.rx_lookahead[1] = 0xaaa5555;
544#endif /* CONFIG_MMC_SDHCI_S3C */
545 status = HIFReadWrite(pDev->HIFDevice,
546 HOST_INT_STATUS_ADDRESS,
547 (u8 *)&pDev->IrqProcRegisters,
548 AR6K_IRQ_PROC_REGS_SIZE,
549 HIF_RD_SYNC_BYTE_INC,
550 NULL);
551
552 if (status) {
553 break;
554 }
555
556#ifdef ATH_DEBUG_MODULE
557 if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
558 DevDumpRegisters(pDev,
559 &pDev->IrqProcRegisters,
560 &pDev->IrqEnableRegisters);
561 }
562#endif
563
564 /* Update only those registers that are enabled */
565 host_int_status = pDev->IrqProcRegisters.host_int_status &
566 pDev->IrqEnableRegisters.int_status_enable;
567
568 if (NULL == pDev->GetPendingEventsFunc) {
569 /* only look at mailbox status if the HIF layer did not provide this function,
570 * on some HIF interfaces reading the RX lookahead is not valid to do */
571 if (host_int_status & (1 << HTC_MAILBOX)) {
572 /* mask out pending mailbox value, we use "lookAhead" as the real flag for
573 * mailbox processing below */
574 host_int_status &= ~(1 << HTC_MAILBOX);
575 if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
576 /* mailbox has a message and the look ahead is valid */
577 lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
578 if (0 == lookAhead) {
579 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
580 }
581 }
582 }
583 } else {
584 /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
585 host_int_status &= ~(1 << HTC_MAILBOX);
586 }
587
588 if (pDev->GMboxEnabled) {
589 /*call GMBOX layer to process any interrupts of interest */
590 status = DevCheckGMboxInterrupts(pDev);
591 }
592
593 } while (false);
594
595
596 do {
597
598 /* did the interrupt status fetches succeed? */
599 if (status) {
600 break;
601 }
602
603 if ((0 == host_int_status) && (0 == lookAhead)) {
604 /* nothing to process, the caller can use this to break out of a loop */
605 *pDone = true;
606 break;
607 }
608
609 if (lookAhead != 0) {
610 int fetched = 0;
611
612 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
613 /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
614 * mailbox...
615 * When emptying the recv mailbox we use the async handler above called from the
616 * completion routine of the callers read request. This can improve performance
617 * by reducing context switching when we rapidly pull packets */
618 status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched);
619 if (status) {
620 break;
621 }
622
623 if (!fetched) {
624 /* HTC could not pull any messages out due to lack of resources */
625 /* force DSR handler to ack the interrupt */
626 *pASyncProcessing = false;
627 pDev->RecheckIRQStatusCnt = 0;
628 }
629 }
630
631 /* now handle the rest of them */
632 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
633 (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
634 host_int_status));
635
636 if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
637 /* CPU Interrupt */
638 status = DevServiceCPUInterrupt(pDev);
639 if (status){
640 break;
641 }
642 }
643
644 if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
645 /* Error Interrupt */
646 status = DevServiceErrorInterrupt(pDev);
647 if (status){
648 break;
649 }
650 }
651
652 if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
653 /* Counter Interrupt */
654 status = DevServiceCounterInterrupt(pDev);
655 if (status){
656 break;
657 }
658 }
659
660 } while (false);
661
662 /* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
663 * the target, if upper layers determine that we are in a low-throughput mode, we can
664 * rely on taking another interrupt rather than re-checking the status registers which can
665 * re-wake the target.
666 *
667 * NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
668 * be used due to possible side-effects. For example, SPI requires the host to drain all
669 * messages from the mailbox before exiting the ISR routine. */
670 if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) {
671 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n"));
672 *pDone = true;
673 }
674
675 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
676 *pDone, *pASyncProcessing, status));
677
678 return status;
679}
680
681
682/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
683int DevDsrHandler(void *context)
684{
685 struct ar6k_device *pDev = (struct ar6k_device *)context;
686 int status = 0;
687 bool done = false;
688 bool asyncProc = false;
689
690 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
691
692 /* reset the recv counter that tracks when we need to yield from the DSR */
693 pDev->CurrentDSRRecvCount = 0;
694 /* reset counter used to flag a re-scan of IRQ status registers on the target */
695 pDev->RecheckIRQStatusCnt = 0;
696
697 while (!done) {
698 status = ProcessPendingIRQs(pDev, &done, &asyncProc);
699 if (status) {
700 break;
701 }
702
703 if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
704 /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
705 asyncProc = false;
706 /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
707 * this has a nice side effect of blocking us until all async read requests are completed.
708 * This behavior is required on some HIF implementations that do not allow ASYNC
709 * processing in interrupt handlers (like Windows CE) */
710
711 if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) {
712 /* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
713 * checking for more messages and return */
714 break;
715 }
716 }
717
718 if (asyncProc) {
719 /* the function performed some async I/O for performance, we
720 need to exit the ISR immediately, the check below will prevent the interrupt from being
721 Ack'd while we handle it asynchronously */
722 break;
723 }
724
725 }
726
727 if (!status && !asyncProc) {
728 /* Ack the interrupt only if :
729 * 1. we did not get any errors in processing interrupts
730 * 2. there are no outstanding async processing requests */
731 if (pDev->DSRCanYield) {
732 /* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
733 * The HIF layer must ACK the interrupt on behalf of HTC */
734 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount));
735 } else {
736 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
737 HIFAckInterrupt(pDev->HIFDevice);
738 }
739 }
740
741 AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
742 return status;
743}
744
745#ifdef ATH_DEBUG_MODULE
746void DumpAR6KDevState(struct ar6k_device *pDev)
747{
748 int status;
749 struct ar6k_irq_enable_registers regs;
750 struct ar6k_irq_proc_registers procRegs;
751
752 LOCK_AR6K(pDev);
753 /* copy into our temp area */
754 memcpy(®s,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
755 UNLOCK_AR6K(pDev);
756
757 /* load the register table from the device */
758 status = HIFReadWrite(pDev->HIFDevice,
759 HOST_INT_STATUS_ADDRESS,
760 (u8 *)&procRegs,
761 AR6K_IRQ_PROC_REGS_SIZE,
762 HIF_RD_SYNC_BYTE_INC,
763 NULL);
764
765 if (status) {
766 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
767 ("DumpAR6KDevState : Failed to read register table (%d) \n",status));
768 return;
769 }
770
771 DevDumpRegisters(pDev,&procRegs,®s);
772
773 if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
774 pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);
775 }
776
777 /* dump any bus state at the HIF layer */
778 HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
779
780}
781#endif
782
783