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/drivers/staging/rtl8192e/r8192E_hw.h

https://bitbucket.org/wisechild/galaxy-nexus
C++ Header | 491 lines | 400 code | 44 blank | 47 comment | 0 complexity | a5b132bfa27b03400103297af22f8612 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2	This is part of rtl8187 OpenSource driver.
  3	Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
  4	Released under the terms of GPL (General Public Licence)
  5
  6	Parts of this driver are based on the GPL part of the
  7	official Realtek driver.
  8	Parts of this driver are based on the rtl8180 driver skeleton
  9	from Patric Schenke & Andres Salomon.
 10	Parts of this driver are based on the Intel Pro Wireless
 11	2100 GPL driver.
 12
 13	We want to tanks the Authors of those projects
 14	and the Ndiswrapper project Authors.
 15*/
 16
 17/* Mariusz Matuszek added full registers definition with Realtek's name */
 18
 19/* this file contains register definitions for the rtl8187 MAC controller */
 20#ifndef R8180_HW
 21#define R8180_HW
 22
 23typedef enum _VERSION_8190{
 24	VERSION_8190_BD=0x3,
 25	VERSION_8190_BE
 26}VERSION_8190,*PVERSION_8190;
 27//added for different RF type
 28typedef enum _RT_RF_TYPE_DEF
 29{
 30	RF_1T2R = 0,
 31	RF_2T4R,
 32
 33	RF_819X_MAX_TYPE
 34}RT_RF_TYPE_DEF;
 35
 36typedef enum _BaseBand_Config_Type{
 37	BaseBand_Config_PHY_REG = 0,			//Radio Path A
 38	BaseBand_Config_AGC_TAB = 1,			//Radio Path B
 39}BaseBand_Config_Type, *PBaseBand_Config_Type;
 40
 41#define	RTL8187_REQT_READ	0xc0
 42#define	RTL8187_REQT_WRITE	0x40
 43#define	RTL8187_REQ_GET_REGS	0x05
 44#define	RTL8187_REQ_SET_REGS	0x05
 45
 46#define R8180_MAX_RETRY 255
 47#define MAX_TX_URB 5
 48#define MAX_RX_URB 16
 49#define RX_URB_SIZE 9100
 50
 51#define BB_ANTATTEN_CHAN14	0x0c
 52#define BB_ANTENNA_B 0x40
 53
 54#define BB_HOST_BANG (1<<30)
 55#define BB_HOST_BANG_EN (1<<2)
 56#define BB_HOST_BANG_CLK (1<<1)
 57#define BB_HOST_BANG_RW (1<<3)
 58#define BB_HOST_BANG_DATA	 1
 59
 60#define RTL8190_EEPROM_ID	0x8129
 61#define EEPROM_VID		0x02
 62#define EEPROM_DID		0x04
 63#define EEPROM_NODE_ADDRESS_BYTE_0	0x0C
 64
 65#define EEPROM_TxPowerDiff	0x1F
 66
 67
 68#define EEPROM_PwDiff		0x21	//0x21
 69#define EEPROM_CrystalCap	0x22	//0x22
 70
 71
 72
 73#define EEPROM_TxPwIndex_CCK_V1		0x29	//0x29~0x2B
 74#define EEPROM_TxPwIndex_OFDM_24G_V1	0x2C	//0x2C~0x2E
 75#define EEPROM_TxPwIndex_Ver		0x27	//0x27
 76
 77#define EEPROM_Default_TxPowerDiff		0x0
 78#define EEPROM_Default_ThermalMeter		0x77
 79#define EEPROM_Default_AntTxPowerDiff		0x0
 80#define EEPROM_Default_TxPwDiff_CrystalCap	0x5
 81#define EEPROM_Default_PwDiff			0x4
 82#define EEPROM_Default_CrystalCap		0x5
 83#define EEPROM_Default_TxPower			0x1010
 84#define EEPROM_ICVersion_ChannelPlan	0x7C	//0x7C:ChannelPlan, 0x7D:IC_Version
 85#define EEPROM_Customer_ID			0x7B	//0x7B:CustomerID
 86
 87#define EEPROM_RFInd_PowerDiff			0x28
 88#define EEPROM_ThermalMeter			0x29
 89#define EEPROM_TxPwDiff_CrystalCap		0x2A	//0x2A~0x2B
 90#define EEPROM_TxPwIndex_CCK			0x2C	//0x23
 91#define EEPROM_TxPwIndex_OFDM_24G	0x3A	//0x24~0x26
 92
 93#define EEPROM_Default_TxPowerLevel		0x10
 94
 95#define EEPROM_IC_VER				0x7d	//0x7D
 96#define EEPROM_CRC				0x7e	//0x7E~0x7F
 97
 98#define EEPROM_CID_DEFAULT			0x0
 99#define EEPROM_CID_CAMEO				0x1
100#define EEPROM_CID_RUNTOP				0x2
101#define EEPROM_CID_Senao				0x3
102#define EEPROM_CID_TOSHIBA				0x4	// Toshiba setting, Merge by Jacken, 2008/01/31
103#define EEPROM_CID_NetCore				0x5
104#define EEPROM_CID_Nettronix			0x6
105#define EEPROM_CID_Pronet				0x7
106#define EEPROM_CID_DLINK				0x8
107#define EEPROM_CID_WHQL 				0xFE  //added by sherry for dtm, 20080728
108
109enum _RTL8192Pci_HW {
110	MAC0 			= 0x000,
111	MAC1 			= 0x001,
112	MAC2 			= 0x002,
113	MAC3 			= 0x003,
114	MAC4 			= 0x004,
115	MAC5 			= 0x005,
116	PCIF			= 0x009, // PCI Function Register 0x0009h~0x000bh
117//----------------------------------------------------------------------------
118//       8190 PCIF bits							(Offset 0x009-000b, 24bit)
119//----------------------------------------------------------------------------
120#define MXDMA2_16bytes		0x000
121#define MXDMA2_32bytes		0x001
122#define MXDMA2_64bytes		0x010
123#define MXDMA2_128bytes		0x011
124#define MXDMA2_256bytes		0x100
125#define MXDMA2_512bytes		0x101
126#define MXDMA2_1024bytes	0x110
127#define MXDMA2_NoLimit		0x7
128
129#define	MULRW_SHIFT		3
130#define	MXDMA2_RX_SHIFT		4
131#define	MXDMA2_TX_SHIFT		0
132        PMR                     = 0x00c, // Power management register
133	EPROM_CMD 		= 0x00e,
134#define EPROM_CMD_RESERVED_MASK BIT5
135#define EPROM_CMD_9356SEL	BIT4
136#define EPROM_CMD_OPERATING_MODE_SHIFT 6
137#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
138#define EPROM_CMD_CONFIG 0x3
139#define EPROM_CMD_NORMAL 0
140#define EPROM_CMD_LOAD 1
141#define EPROM_CMD_PROGRAM 2
142#define EPROM_CS_SHIFT 3
143#define EPROM_CK_SHIFT 2
144#define EPROM_W_SHIFT 1
145#define EPROM_R_SHIFT 0
146
147	AFR			 = 0x010,
148#define AFR_CardBEn		(1<<0)
149#define AFR_CLKRUN_SEL		(1<<1)
150#define AFR_FuncRegEn		(1<<2)
151
152	ANAPAR			= 0x17,
153#define	BB_GLOBAL_RESET_BIT	0x1
154	BB_GLOBAL_RESET		= 0x020, // BasebandGlobal Reset Register
155	BSSIDR			= 0x02E, // BSSID Register
156	CMDR			= 0x037, // Command register
157#define 	CR_RST					0x10
158#define 	CR_RE					0x08
159#define 	CR_TE					0x04
160#define 	CR_MulRW				0x01
161	SIFS		= 0x03E,	// SIFS register
162	TCR			= 0x040, // Transmit Configuration Register
163	RCR			= 0x044, // Receive Configuration Register
164//----------------------------------------------------------------------------
165////       8190 (RCR) Receive Configuration Register	(Offset 0x44~47, 32 bit)
166////----------------------------------------------------------------------------
167#define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
168#define RCR_ONLYERLPKT		BIT31			// Early Receiving based on Packet Size.
169#define RCR_ENCS2		BIT30				// Enable Carrier Sense Detection Method 2
170#define RCR_ENCS1		BIT29				// Enable Carrier Sense Detection Method 1
171#define RCR_ENMBID		BIT27				// Enable Multiple BssId.
172#define RCR_ACKTXBW		(BIT24|BIT25)		// TXBW Setting of ACK frames
173#define RCR_CBSSID		BIT23				// Accept BSSID match packet
174#define RCR_APWRMGT		BIT22				// Accept power management packet
175#define	RCR_ADD3		BIT21			// Accept address 3 match packet
176#define RCR_AMF			BIT20				// Accept management type frame
177#define RCR_ACF			BIT19				// Accept control type frame
178#define RCR_ADF			BIT18				// Accept data type frame
179#define RCR_RXFTH		BIT13	// Rx FIFO Threshold
180#define RCR_AICV		BIT12				// Accept ICV error packet
181#define	RCR_ACRC32		BIT5			// Accept CRC32 error packet
182#define	RCR_AB			BIT3			// Accept broadcast packet
183#define	RCR_AM			BIT2			// Accept multicast packet
184#define	RCR_APM			BIT1			// Accept physical match packet
185#define	RCR_AAP			BIT0			// Accept all unicast packet
186#define RCR_MXDMA_OFFSET	8
187#define RCR_FIFO_OFFSET		13
188	SLOT_TIME		= 0x049, // Slot Time Register
189	ACK_TIMEOUT		= 0x04c, // Ack Timeout Register
190	PIFS_TIME		= 0x04d, // PIFS time
191	USTIME			= 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock.
192	EDCAPARA_BE		= 0x050, // EDCA Parameter of AC BE
193	EDCAPARA_BK		= 0x054, // EDCA Parameter of AC BK
194	EDCAPARA_VO		= 0x058, // EDCA Parameter of AC VO
195	EDCAPARA_VI		= 0x05C, // EDCA Parameter of AC VI
196#define	AC_PARAM_TXOP_LIMIT_OFFSET		16
197#define	AC_PARAM_ECW_MAX_OFFSET		12
198#define	AC_PARAM_ECW_MIN_OFFSET			8
199#define	AC_PARAM_AIFS_OFFSET				0
200	RFPC			= 0x05F, // Rx FIFO Packet Count
201	CWRR			= 0x060, // Contention Window Report Register
202	BCN_TCFG		= 0x062, // Beacon Time Configuration
203#define BCN_TCFG_CW_SHIFT		8
204#define BCN_TCFG_IFS			0
205	BCN_INTERVAL		= 0x070, // Beacon Interval (TU)
206	ATIMWND			= 0x072, // ATIM Window Size (TU)
207	BCN_DRV_EARLY_INT	= 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT
208#define	BCN_DRV_EARLY_INT_SWBCN_SHIFT	8
209#define	BCN_DRV_EARLY_INT_TIME_SHIFT	0
210	BCN_DMATIME		= 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA
211	BCN_ERR_THRESH		= 0x078, // Beacon Error Threshold
212	RWCAM			= 0x0A0, //IN 8190 Data Sheet is called CAMcmd
213	//----------------------------------------------------------------------------
214	////       8190 CAM Command Register     		(offset 0xA0, 4 byte)
215	////----------------------------------------------------------------------------
216#define   CAM_CM_SecCAMPolling		BIT31		//Security CAM Polling
217#define   CAM_CM_SecCAMClr			BIT30		//Clear all bits in CAM
218#define   CAM_CM_SecCAMWE			BIT16		//Security CAM enable
219#define   CAM_VALID			       BIT15
220#define   CAM_NOTVALID			0x0000
221#define   CAM_USEDK				BIT5
222
223#define   CAM_NONE				0x0
224#define   CAM_WEP40				0x01
225#define   CAM_TKIP				0x02
226#define   CAM_AES				0x04
227#define   CAM_WEP104			0x05
228
229#define   TOTAL_CAM_ENTRY				32
230
231#define   CAM_CONFIG_USEDK	true
232#define   CAM_CONFIG_NO_USEDK	false
233#define   CAM_WRITE		BIT16
234#define   CAM_READ		0x00000000
235#define   CAM_POLLINIG		BIT31
236#define   SCR_UseDK		0x01
237	WCAMI			= 0x0A4, // Software write CAM input content
238	RCAMO			= 0x0A8, // Software read/write CAM config
239	SECR			= 0x0B0, //Security Configuration Register
240#define	SCR_TxUseDK			BIT0			//Force Tx Use Default Key
241#define   SCR_RxUseDK			BIT1			//Force Rx Use Default Key
242#define   SCR_TxEncEnable		BIT2			//Enable Tx Encryption
243#define   SCR_RxDecEnable		BIT3			//Enable Rx Decryption
244#define   SCR_SKByA2				BIT4			//Search kEY BY A2
245#define   SCR_NoSKMC				BIT5			//No Key Search for Multicast
246	SWREGULATOR	= 0x0BD,	// Switching Regulator
247	INTA_MASK 		= 0x0f4,
248//----------------------------------------------------------------------------
249//       8190 IMR/ISR bits						(offset 0xfd,  8bits)
250//----------------------------------------------------------------------------
251#define IMR8190_DISABLED		0x0
252#define IMR_ATIMEND			BIT28			// ATIM Window End Interrupt
253#define IMR_TBDOK			BIT27			// Transmit Beacon OK Interrupt
254#define IMR_TBDER			BIT26			// Transmit Beacon Error Interrupt
255#define IMR_TXFOVW			BIT15			// Transmit FIFO Overflow
256#define IMR_TIMEOUT0			BIT14			// TimeOut0
257#define IMR_BcnInt			BIT13			// Beacon DMA Interrupt 0
258#define	IMR_RXFOVW			BIT12			// Receive FIFO Overflow
259#define IMR_RDU				BIT11			// Receive Descriptor Unavailable
260#define IMR_RXCMDOK			BIT10			// Receive Command Packet OK
261#define IMR_BDOK			BIT9			// Beacon Queue DMA OK Interrup
262#define IMR_HIGHDOK			BIT8			// High Queue DMA OK Interrupt
263#define	IMR_COMDOK			BIT7			// Command Queue DMA OK Interrupt
264#define IMR_MGNTDOK			BIT6			// Management Queue DMA OK Interrupt
265#define IMR_HCCADOK			BIT5			// HCCA Queue DMA OK Interrupt
266#define	IMR_BKDOK			BIT4			// AC_BK DMA OK Interrupt
267#define	IMR_BEDOK			BIT3			// AC_BE DMA OK Interrupt
268#define	IMR_VIDOK			BIT2			// AC_VI DMA OK Interrupt
269#define	IMR_VODOK			BIT1			// AC_VO DMA Interrupt
270#define	IMR_ROK				BIT0			// Receive DMA OK Interrupt
271	ISR			= 0x0f8, // Interrupt Status Register
272	TPPoll			= 0x0fd, // Transmit priority polling register
273#define TPPoll_BKQ		BIT0				// BK queue polling
274#define TPPoll_BEQ		BIT1				// BE queue polling
275#define TPPoll_VIQ		BIT2				// VI queue polling
276#define TPPoll_VOQ		BIT3				// VO queue polling
277#define TPPoll_BQ		BIT4				// Beacon queue polling
278#define TPPoll_CQ		BIT5				// Command queue polling
279#define TPPoll_MQ		BIT6				// Management queue polling
280#define TPPoll_HQ		BIT7				// High queue polling
281#define TPPoll_HCCAQ		BIT8				// HCCA queue polling
282#define TPPoll_StopBK	BIT9				// Stop BK queue
283#define TPPoll_StopBE	BIT10			// Stop BE queue
284#define TPPoll_StopVI		BIT11			// Stop VI queue
285#define TPPoll_StopVO	BIT12			// Stop VO queue
286#define TPPoll_StopMgt	BIT13			// Stop Mgnt queue
287#define TPPoll_StopHigh	BIT14			// Stop High queue
288#define TPPoll_StopHCCA	BIT15			// Stop HCCA queue
289#define TPPoll_SHIFT		8				// Queue ID mapping
290
291	PSR			= 0x0ff, // Page Select Register
292#define PSR_GEN			0x0				// Page 0 register general MAC Control
293#define PSR_CPU			0x1				// Page 1 register for CPU
294	CPU_GEN			= 0x100, // CPU Reset Register
295	BB_RESET			= 0x101, // Baseband Reset
296//----------------------------------------------------------------------------
297//       8190 CPU General Register		(offset 0x100, 4 byte)
298//----------------------------------------------------------------------------
299#define	CPU_CCK_LOOPBACK	0x00030000
300#define	CPU_GEN_SYSTEM_RESET	0x00000001
301#define	CPU_GEN_FIRMWARE_RESET	0x00000008
302#define	CPU_GEN_BOOT_RDY	0x00000010
303#define	CPU_GEN_FIRM_RDY	0x00000020
304#define	CPU_GEN_PUT_CODE_OK	0x00000080
305#define	CPU_GEN_BB_RST		0x00000100
306#define	CPU_GEN_PWR_STB_CPU	0x00000004
307#define CPU_GEN_NO_LOOPBACK_MSK	0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
308#define CPU_GEN_NO_LOOPBACK_SET	0x00080000 // Set BIT19 to 1
309#define	CPU_GEN_GPIO_UART		0x00007000
310
311	LED1Cfg			= 0x154,// LED1 Configuration Register
312 	LED0Cfg			= 0x155,// LED0 Configuration Register
313
314	AcmAvg			= 0x170, // ACM Average Period Register
315	AcmHwCtrl		= 0x171, // ACM Hardware Control Register
316//----------------------------------------------------------------------------
317//
318//       8190 AcmHwCtrl bits 					(offset 0x171, 1 byte)
319//----------------------------------------------------------------------------
320#define	AcmHw_HwEn		BIT0
321#define	AcmHw_BeqEn		BIT1
322#define	AcmHw_ViqEn		BIT2
323#define	AcmHw_VoqEn		BIT3
324#define	AcmHw_BeqStatus		BIT4
325#define	AcmHw_ViqStatus		BIT5
326#define	AcmHw_VoqStatus		BIT6
327	AcmFwCtrl		= 0x172, // ACM Firmware Control Register
328#define	AcmFw_BeqStatus		BIT0
329#define	AcmFw_ViqStatus		BIT1
330#define	AcmFw_VoqStatus		BIT2
331	VOAdmTime		= 0x174, // VO Queue Admitted Time Register
332	VIAdmTime		= 0x178, // VI Queue Admitted Time Register
333	BEAdmTime		= 0x17C, // BE Queue Admitted Time Register
334	RQPN1			= 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk
335	RQPN2			= 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High
336	RQPN3			= 0x188, // Reserved Queue Page Number, Bcn, Public,
337	QPRR			= 0x1E0, // Queue Page Report per TID
338	QPNR			= 0x1F0, // Queue Packet Number report per TID
339/* there's 9 tx descriptor base address available */
340	BQDA			= 0x200, // Beacon Queue Descriptor Address
341	HQDA			= 0x204, // High Priority Queue Descriptor Address
342	CQDA			= 0x208, // Command Queue Descriptor Address
343	MQDA			= 0x20C, // Management Queue Descriptor Address
344	HCCAQDA			= 0x210, // HCCA Queue Descriptor Address
345	VOQDA			= 0x214, // VO Queue Descriptor Address
346	VIQDA			= 0x218, // VI Queue Descriptor Address
347	BEQDA			= 0x21C, // BE Queue Descriptor Address
348	BKQDA			= 0x220, // BK Queue Descriptor Address
349/* there's 2 rx descriptor base address availalbe */
350	RCQDA			= 0x224, // Receive command Queue Descriptor Address
351	RDQDA			= 0x228, // Receive Queue Descriptor Start Address
352
353	MAR0			= 0x240, // Multicast filter.
354	MAR4			= 0x244,
355
356	CCX_PERIOD		= 0x250, // CCX Measurement Period Register, in unit of TU.
357	CLM_RESULT		= 0x251, // CCA Busy fraction register.
358	NHM_PERIOD		= 0x252, // NHM Measurement Period register, in unit of TU.
359
360	NHM_THRESHOLD0		= 0x253, // Noise Histogram Meashorement0.
361	NHM_THRESHOLD1		= 0x254, // Noise Histogram Meashorement1.
362	NHM_THRESHOLD2		= 0x255, // Noise Histogram Meashorement2.
363	NHM_THRESHOLD3		= 0x256, // Noise Histogram Meashorement3.
364	NHM_THRESHOLD4		= 0x257, // Noise Histogram Meashorement4.
365	NHM_THRESHOLD5		= 0x258, // Noise Histogram Meashorement5.
366	NHM_THRESHOLD6		= 0x259, // Noise Histogram Meashorement6
367
368	MCTRL			= 0x25A, // Measurement Control
369
370	NHM_RPI_COUNTER0	= 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
371	NHM_RPI_COUNTER1	= 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1].
372	NHM_RPI_COUNTER2	= 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2].
373	NHM_RPI_COUNTER3	= 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3].
374	NHM_RPI_COUNTER4	= 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4].
375	NHM_RPI_COUNTER5	= 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5].
376	NHM_RPI_COUNTER6	= 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6].
377	NHM_RPI_COUNTER7	= 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7].
378        WFCRC0                  = 0x2f0,
379        WFCRC1                  = 0x2f4,
380        WFCRC2                  = 0x2f8,
381
382	BW_OPMODE		= 0x300, // Bandwidth operation mode
383#define	BW_OPMODE_11J			BIT0
384#define	BW_OPMODE_5G			BIT1
385#define	BW_OPMODE_20MHZ			BIT2
386	IC_VERRSION		= 0x301,	//IC_VERSION
387	MSR			= 0x303, // Media Status register
388#define MSR_LINK_MASK      ((1<<0)|(1<<1))
389#define MSR_LINK_MANAGED   2
390#define MSR_LINK_NONE      0
391#define MSR_LINK_SHIFT     0
392#define MSR_LINK_ADHOC     1
393#define MSR_LINK_MASTER    3
394#define MSR_LINK_ENEDCA	   (1<<4)
395	RETRY_LIMIT		= 0x304, // Retry Limit [15:8]-short, [7:0]-long
396#define RETRY_LIMIT_SHORT_SHIFT 8
397#define RETRY_LIMIT_LONG_SHIFT 0
398	TSFR			= 0x308,
399	RRSR			= 0x310, // Response Rate Set
400#define RRSR_RSC_OFFSET			21
401#define RRSR_SHORT_OFFSET			23
402#define RRSR_RSC_DUPLICATE			0x600000
403#define RRSR_RSC_UPSUBCHNL			0x400000
404#define RRSR_RSC_LOWSUBCHNL		0x200000
405#define RRSR_SHORT					0x800000
406#define RRSR_1M						BIT0
407#define RRSR_2M						BIT1
408#define RRSR_5_5M					BIT2
409#define RRSR_11M					BIT3
410#define RRSR_6M						BIT4
411#define RRSR_9M						BIT5
412#define RRSR_12M					BIT6
413#define RRSR_18M					BIT7
414#define RRSR_24M					BIT8
415#define RRSR_36M					BIT9
416#define RRSR_48M					BIT10
417#define RRSR_54M					BIT11
418#define RRSR_MCS0					BIT12
419#define RRSR_MCS1					BIT13
420#define RRSR_MCS2					BIT14
421#define RRSR_MCS3					BIT15
422#define RRSR_MCS4					BIT16
423#define RRSR_MCS5					BIT17
424#define RRSR_MCS6					BIT18
425#define RRSR_MCS7					BIT19
426#define BRSR_AckShortPmb			BIT23		// CCK ACK: use Short Preamble or not
427	UFWP			= 0x318,
428	RATR0			= 0x320, // Rate Adaptive Table register1
429//----------------------------------------------------------------------------
430//       8190 Rate Adaptive Table Register	(offset 0x320, 4 byte)
431//----------------------------------------------------------------------------
432//CCK
433#define	RATR_1M			0x00000001
434#define	RATR_2M			0x00000002
435#define	RATR_55M		0x00000004
436#define	RATR_11M		0x00000008
437//OFDM
438#define	RATR_6M			0x00000010
439#define	RATR_9M			0x00000020
440#define	RATR_12M		0x00000040
441#define	RATR_18M		0x00000080
442#define	RATR_24M		0x00000100
443#define	RATR_36M		0x00000200
444#define	RATR_48M		0x00000400
445#define	RATR_54M		0x00000800
446//MCS 1 Spatial Stream
447#define	RATR_MCS0		0x00001000
448#define	RATR_MCS1		0x00002000
449#define	RATR_MCS2		0x00004000
450#define	RATR_MCS3		0x00008000
451#define	RATR_MCS4		0x00010000
452#define	RATR_MCS5		0x00020000
453#define	RATR_MCS6		0x00040000
454#define	RATR_MCS7		0x00080000
455//MCS 2 Spatial Stream
456#define	RATR_MCS8		0x00100000
457#define	RATR_MCS9		0x00200000
458#define	RATR_MCS10		0x00400000
459#define	RATR_MCS11		0x00800000
460#define	RATR_MCS12		0x01000000
461#define	RATR_MCS13		0x02000000
462#define	RATR_MCS14		0x04000000
463#define	RATR_MCS15		0x08000000
464// ALL CCK Rate
465#define RATE_ALL_CCK		RATR_1M|RATR_2M|RATR_55M|RATR_11M
466#define RATE_ALL_OFDM_AG	RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|RATR_36M|RATR_48M|RATR_54M
467#define RATE_ALL_OFDM_1SS	RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
468									RATR_MCS4|RATR_MCS5|RATR_MCS6	|RATR_MCS7
469#define RATE_ALL_OFDM_2SS	RATR_MCS8|RATR_MCS9	|RATR_MCS10|RATR_MCS11| \
470									RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
471
472
473	DRIVER_RSSI		= 0x32c,	// Driver tell Firmware current RSSI
474	MCS_TXAGC		= 0x340, // MCS AGC
475	CCK_TXAGC		= 0x348, // CCK AGC
476	MacBlkCtrl		= 0x403, // Mac block on/off control register
477
478};
479
480#define GPI 0x108
481#define GPO 0x109
482#define GPE 0x10a
483
484#define	ANAPAR_FOR_8192PciE							0x17		// Analog parameter register
485
486#define	MSR_NOLINK					0x00
487#define	MSR_ADHOC					0x01
488#define	MSR_INFRA					0x02
489#define	MSR_AP						0x03
490
491#endif