/drivers/staging/rtl8192e/r8192E_hw.h

https://bitbucket.org/wisechild/galaxy-nexus · C++ Header · 491 lines · 400 code · 44 blank · 47 comment · 0 complexity · a5b132bfa27b03400103297af22f8612 MD5 · raw file

  1. /*
  2. This is part of rtl8187 OpenSource driver.
  3. Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
  4. Released under the terms of GPL (General Public Licence)
  5. Parts of this driver are based on the GPL part of the
  6. official Realtek driver.
  7. Parts of this driver are based on the rtl8180 driver skeleton
  8. from Patric Schenke & Andres Salomon.
  9. Parts of this driver are based on the Intel Pro Wireless
  10. 2100 GPL driver.
  11. We want to tanks the Authors of those projects
  12. and the Ndiswrapper project Authors.
  13. */
  14. /* Mariusz Matuszek added full registers definition with Realtek's name */
  15. /* this file contains register definitions for the rtl8187 MAC controller */
  16. #ifndef R8180_HW
  17. #define R8180_HW
  18. typedef enum _VERSION_8190{
  19. VERSION_8190_BD=0x3,
  20. VERSION_8190_BE
  21. }VERSION_8190,*PVERSION_8190;
  22. //added for different RF type
  23. typedef enum _RT_RF_TYPE_DEF
  24. {
  25. RF_1T2R = 0,
  26. RF_2T4R,
  27. RF_819X_MAX_TYPE
  28. }RT_RF_TYPE_DEF;
  29. typedef enum _BaseBand_Config_Type{
  30. BaseBand_Config_PHY_REG = 0, //Radio Path A
  31. BaseBand_Config_AGC_TAB = 1, //Radio Path B
  32. }BaseBand_Config_Type, *PBaseBand_Config_Type;
  33. #define RTL8187_REQT_READ 0xc0
  34. #define RTL8187_REQT_WRITE 0x40
  35. #define RTL8187_REQ_GET_REGS 0x05
  36. #define RTL8187_REQ_SET_REGS 0x05
  37. #define R8180_MAX_RETRY 255
  38. #define MAX_TX_URB 5
  39. #define MAX_RX_URB 16
  40. #define RX_URB_SIZE 9100
  41. #define BB_ANTATTEN_CHAN14 0x0c
  42. #define BB_ANTENNA_B 0x40
  43. #define BB_HOST_BANG (1<<30)
  44. #define BB_HOST_BANG_EN (1<<2)
  45. #define BB_HOST_BANG_CLK (1<<1)
  46. #define BB_HOST_BANG_RW (1<<3)
  47. #define BB_HOST_BANG_DATA 1
  48. #define RTL8190_EEPROM_ID 0x8129
  49. #define EEPROM_VID 0x02
  50. #define EEPROM_DID 0x04
  51. #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
  52. #define EEPROM_TxPowerDiff 0x1F
  53. #define EEPROM_PwDiff 0x21 //0x21
  54. #define EEPROM_CrystalCap 0x22 //0x22
  55. #define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B
  56. #define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E
  57. #define EEPROM_TxPwIndex_Ver 0x27 //0x27
  58. #define EEPROM_Default_TxPowerDiff 0x0
  59. #define EEPROM_Default_ThermalMeter 0x77
  60. #define EEPROM_Default_AntTxPowerDiff 0x0
  61. #define EEPROM_Default_TxPwDiff_CrystalCap 0x5
  62. #define EEPROM_Default_PwDiff 0x4
  63. #define EEPROM_Default_CrystalCap 0x5
  64. #define EEPROM_Default_TxPower 0x1010
  65. #define EEPROM_ICVersion_ChannelPlan 0x7C //0x7C:ChannelPlan, 0x7D:IC_Version
  66. #define EEPROM_Customer_ID 0x7B //0x7B:CustomerID
  67. #define EEPROM_RFInd_PowerDiff 0x28
  68. #define EEPROM_ThermalMeter 0x29
  69. #define EEPROM_TxPwDiff_CrystalCap 0x2A //0x2A~0x2B
  70. #define EEPROM_TxPwIndex_CCK 0x2C //0x23
  71. #define EEPROM_TxPwIndex_OFDM_24G 0x3A //0x24~0x26
  72. #define EEPROM_Default_TxPowerLevel 0x10
  73. #define EEPROM_IC_VER 0x7d //0x7D
  74. #define EEPROM_CRC 0x7e //0x7E~0x7F
  75. #define EEPROM_CID_DEFAULT 0x0
  76. #define EEPROM_CID_CAMEO 0x1
  77. #define EEPROM_CID_RUNTOP 0x2
  78. #define EEPROM_CID_Senao 0x3
  79. #define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31
  80. #define EEPROM_CID_NetCore 0x5
  81. #define EEPROM_CID_Nettronix 0x6
  82. #define EEPROM_CID_Pronet 0x7
  83. #define EEPROM_CID_DLINK 0x8
  84. #define EEPROM_CID_WHQL 0xFE //added by sherry for dtm, 20080728
  85. enum _RTL8192Pci_HW {
  86. MAC0 = 0x000,
  87. MAC1 = 0x001,
  88. MAC2 = 0x002,
  89. MAC3 = 0x003,
  90. MAC4 = 0x004,
  91. MAC5 = 0x005,
  92. PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh
  93. //----------------------------------------------------------------------------
  94. // 8190 PCIF bits (Offset 0x009-000b, 24bit)
  95. //----------------------------------------------------------------------------
  96. #define MXDMA2_16bytes 0x000
  97. #define MXDMA2_32bytes 0x001
  98. #define MXDMA2_64bytes 0x010
  99. #define MXDMA2_128bytes 0x011
  100. #define MXDMA2_256bytes 0x100
  101. #define MXDMA2_512bytes 0x101
  102. #define MXDMA2_1024bytes 0x110
  103. #define MXDMA2_NoLimit 0x7
  104. #define MULRW_SHIFT 3
  105. #define MXDMA2_RX_SHIFT 4
  106. #define MXDMA2_TX_SHIFT 0
  107. PMR = 0x00c, // Power management register
  108. EPROM_CMD = 0x00e,
  109. #define EPROM_CMD_RESERVED_MASK BIT5
  110. #define EPROM_CMD_9356SEL BIT4
  111. #define EPROM_CMD_OPERATING_MODE_SHIFT 6
  112. #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
  113. #define EPROM_CMD_CONFIG 0x3
  114. #define EPROM_CMD_NORMAL 0
  115. #define EPROM_CMD_LOAD 1
  116. #define EPROM_CMD_PROGRAM 2
  117. #define EPROM_CS_SHIFT 3
  118. #define EPROM_CK_SHIFT 2
  119. #define EPROM_W_SHIFT 1
  120. #define EPROM_R_SHIFT 0
  121. AFR = 0x010,
  122. #define AFR_CardBEn (1<<0)
  123. #define AFR_CLKRUN_SEL (1<<1)
  124. #define AFR_FuncRegEn (1<<2)
  125. ANAPAR = 0x17,
  126. #define BB_GLOBAL_RESET_BIT 0x1
  127. BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register
  128. BSSIDR = 0x02E, // BSSID Register
  129. CMDR = 0x037, // Command register
  130. #define CR_RST 0x10
  131. #define CR_RE 0x08
  132. #define CR_TE 0x04
  133. #define CR_MulRW 0x01
  134. SIFS = 0x03E, // SIFS register
  135. TCR = 0x040, // Transmit Configuration Register
  136. RCR = 0x044, // Receive Configuration Register
  137. //----------------------------------------------------------------------------
  138. //// 8190 (RCR) Receive Configuration Register (Offset 0x44~47, 32 bit)
  139. ////----------------------------------------------------------------------------
  140. #define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
  141. #define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
  142. #define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2
  143. #define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1
  144. #define RCR_ENMBID BIT27 // Enable Multiple BssId.
  145. #define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames
  146. #define RCR_CBSSID BIT23 // Accept BSSID match packet
  147. #define RCR_APWRMGT BIT22 // Accept power management packet
  148. #define RCR_ADD3 BIT21 // Accept address 3 match packet
  149. #define RCR_AMF BIT20 // Accept management type frame
  150. #define RCR_ACF BIT19 // Accept control type frame
  151. #define RCR_ADF BIT18 // Accept data type frame
  152. #define RCR_RXFTH BIT13 // Rx FIFO Threshold
  153. #define RCR_AICV BIT12 // Accept ICV error packet
  154. #define RCR_ACRC32 BIT5 // Accept CRC32 error packet
  155. #define RCR_AB BIT3 // Accept broadcast packet
  156. #define RCR_AM BIT2 // Accept multicast packet
  157. #define RCR_APM BIT1 // Accept physical match packet
  158. #define RCR_AAP BIT0 // Accept all unicast packet
  159. #define RCR_MXDMA_OFFSET 8
  160. #define RCR_FIFO_OFFSET 13
  161. SLOT_TIME = 0x049, // Slot Time Register
  162. ACK_TIMEOUT = 0x04c, // Ack Timeout Register
  163. PIFS_TIME = 0x04d, // PIFS time
  164. USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock.
  165. EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE
  166. EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK
  167. EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO
  168. EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI
  169. #define AC_PARAM_TXOP_LIMIT_OFFSET 16
  170. #define AC_PARAM_ECW_MAX_OFFSET 12
  171. #define AC_PARAM_ECW_MIN_OFFSET 8
  172. #define AC_PARAM_AIFS_OFFSET 0
  173. RFPC = 0x05F, // Rx FIFO Packet Count
  174. CWRR = 0x060, // Contention Window Report Register
  175. BCN_TCFG = 0x062, // Beacon Time Configuration
  176. #define BCN_TCFG_CW_SHIFT 8
  177. #define BCN_TCFG_IFS 0
  178. BCN_INTERVAL = 0x070, // Beacon Interval (TU)
  179. ATIMWND = 0x072, // ATIM Window Size (TU)
  180. BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT
  181. #define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8
  182. #define BCN_DRV_EARLY_INT_TIME_SHIFT 0
  183. BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA
  184. BCN_ERR_THRESH = 0x078, // Beacon Error Threshold
  185. RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd
  186. //----------------------------------------------------------------------------
  187. //// 8190 CAM Command Register (offset 0xA0, 4 byte)
  188. ////----------------------------------------------------------------------------
  189. #define CAM_CM_SecCAMPolling BIT31 //Security CAM Polling
  190. #define CAM_CM_SecCAMClr BIT30 //Clear all bits in CAM
  191. #define CAM_CM_SecCAMWE BIT16 //Security CAM enable
  192. #define CAM_VALID BIT15
  193. #define CAM_NOTVALID 0x0000
  194. #define CAM_USEDK BIT5
  195. #define CAM_NONE 0x0
  196. #define CAM_WEP40 0x01
  197. #define CAM_TKIP 0x02
  198. #define CAM_AES 0x04
  199. #define CAM_WEP104 0x05
  200. #define TOTAL_CAM_ENTRY 32
  201. #define CAM_CONFIG_USEDK true
  202. #define CAM_CONFIG_NO_USEDK false
  203. #define CAM_WRITE BIT16
  204. #define CAM_READ 0x00000000
  205. #define CAM_POLLINIG BIT31
  206. #define SCR_UseDK 0x01
  207. WCAMI = 0x0A4, // Software write CAM input content
  208. RCAMO = 0x0A8, // Software read/write CAM config
  209. SECR = 0x0B0, //Security Configuration Register
  210. #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
  211. #define SCR_RxUseDK BIT1 //Force Rx Use Default Key
  212. #define SCR_TxEncEnable BIT2 //Enable Tx Encryption
  213. #define SCR_RxDecEnable BIT3 //Enable Rx Decryption
  214. #define SCR_SKByA2 BIT4 //Search kEY BY A2
  215. #define SCR_NoSKMC BIT5 //No Key Search for Multicast
  216. SWREGULATOR = 0x0BD, // Switching Regulator
  217. INTA_MASK = 0x0f4,
  218. //----------------------------------------------------------------------------
  219. // 8190 IMR/ISR bits (offset 0xfd, 8bits)
  220. //----------------------------------------------------------------------------
  221. #define IMR8190_DISABLED 0x0
  222. #define IMR_ATIMEND BIT28 // ATIM Window End Interrupt
  223. #define IMR_TBDOK BIT27 // Transmit Beacon OK Interrupt
  224. #define IMR_TBDER BIT26 // Transmit Beacon Error Interrupt
  225. #define IMR_TXFOVW BIT15 // Transmit FIFO Overflow
  226. #define IMR_TIMEOUT0 BIT14 // TimeOut0
  227. #define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0
  228. #define IMR_RXFOVW BIT12 // Receive FIFO Overflow
  229. #define IMR_RDU BIT11 // Receive Descriptor Unavailable
  230. #define IMR_RXCMDOK BIT10 // Receive Command Packet OK
  231. #define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup
  232. #define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt
  233. #define IMR_COMDOK BIT7 // Command Queue DMA OK Interrupt
  234. #define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt
  235. #define IMR_HCCADOK BIT5 // HCCA Queue DMA OK Interrupt
  236. #define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt
  237. #define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt
  238. #define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt
  239. #define IMR_VODOK BIT1 // AC_VO DMA Interrupt
  240. #define IMR_ROK BIT0 // Receive DMA OK Interrupt
  241. ISR = 0x0f8, // Interrupt Status Register
  242. TPPoll = 0x0fd, // Transmit priority polling register
  243. #define TPPoll_BKQ BIT0 // BK queue polling
  244. #define TPPoll_BEQ BIT1 // BE queue polling
  245. #define TPPoll_VIQ BIT2 // VI queue polling
  246. #define TPPoll_VOQ BIT3 // VO queue polling
  247. #define TPPoll_BQ BIT4 // Beacon queue polling
  248. #define TPPoll_CQ BIT5 // Command queue polling
  249. #define TPPoll_MQ BIT6 // Management queue polling
  250. #define TPPoll_HQ BIT7 // High queue polling
  251. #define TPPoll_HCCAQ BIT8 // HCCA queue polling
  252. #define TPPoll_StopBK BIT9 // Stop BK queue
  253. #define TPPoll_StopBE BIT10 // Stop BE queue
  254. #define TPPoll_StopVI BIT11 // Stop VI queue
  255. #define TPPoll_StopVO BIT12 // Stop VO queue
  256. #define TPPoll_StopMgt BIT13 // Stop Mgnt queue
  257. #define TPPoll_StopHigh BIT14 // Stop High queue
  258. #define TPPoll_StopHCCA BIT15 // Stop HCCA queue
  259. #define TPPoll_SHIFT 8 // Queue ID mapping
  260. PSR = 0x0ff, // Page Select Register
  261. #define PSR_GEN 0x0 // Page 0 register general MAC Control
  262. #define PSR_CPU 0x1 // Page 1 register for CPU
  263. CPU_GEN = 0x100, // CPU Reset Register
  264. BB_RESET = 0x101, // Baseband Reset
  265. //----------------------------------------------------------------------------
  266. // 8190 CPU General Register (offset 0x100, 4 byte)
  267. //----------------------------------------------------------------------------
  268. #define CPU_CCK_LOOPBACK 0x00030000
  269. #define CPU_GEN_SYSTEM_RESET 0x00000001
  270. #define CPU_GEN_FIRMWARE_RESET 0x00000008
  271. #define CPU_GEN_BOOT_RDY 0x00000010
  272. #define CPU_GEN_FIRM_RDY 0x00000020
  273. #define CPU_GEN_PUT_CODE_OK 0x00000080
  274. #define CPU_GEN_BB_RST 0x00000100
  275. #define CPU_GEN_PWR_STB_CPU 0x00000004
  276. #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
  277. #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
  278. #define CPU_GEN_GPIO_UART 0x00007000
  279. LED1Cfg = 0x154,// LED1 Configuration Register
  280. LED0Cfg = 0x155,// LED0 Configuration Register
  281. AcmAvg = 0x170, // ACM Average Period Register
  282. AcmHwCtrl = 0x171, // ACM Hardware Control Register
  283. //----------------------------------------------------------------------------
  284. //
  285. // 8190 AcmHwCtrl bits (offset 0x171, 1 byte)
  286. //----------------------------------------------------------------------------
  287. #define AcmHw_HwEn BIT0
  288. #define AcmHw_BeqEn BIT1
  289. #define AcmHw_ViqEn BIT2
  290. #define AcmHw_VoqEn BIT3
  291. #define AcmHw_BeqStatus BIT4
  292. #define AcmHw_ViqStatus BIT5
  293. #define AcmHw_VoqStatus BIT6
  294. AcmFwCtrl = 0x172, // ACM Firmware Control Register
  295. #define AcmFw_BeqStatus BIT0
  296. #define AcmFw_ViqStatus BIT1
  297. #define AcmFw_VoqStatus BIT2
  298. VOAdmTime = 0x174, // VO Queue Admitted Time Register
  299. VIAdmTime = 0x178, // VI Queue Admitted Time Register
  300. BEAdmTime = 0x17C, // BE Queue Admitted Time Register
  301. RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk
  302. RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High
  303. RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public,
  304. QPRR = 0x1E0, // Queue Page Report per TID
  305. QPNR = 0x1F0, // Queue Packet Number report per TID
  306. /* there's 9 tx descriptor base address available */
  307. BQDA = 0x200, // Beacon Queue Descriptor Address
  308. HQDA = 0x204, // High Priority Queue Descriptor Address
  309. CQDA = 0x208, // Command Queue Descriptor Address
  310. MQDA = 0x20C, // Management Queue Descriptor Address
  311. HCCAQDA = 0x210, // HCCA Queue Descriptor Address
  312. VOQDA = 0x214, // VO Queue Descriptor Address
  313. VIQDA = 0x218, // VI Queue Descriptor Address
  314. BEQDA = 0x21C, // BE Queue Descriptor Address
  315. BKQDA = 0x220, // BK Queue Descriptor Address
  316. /* there's 2 rx descriptor base address availalbe */
  317. RCQDA = 0x224, // Receive command Queue Descriptor Address
  318. RDQDA = 0x228, // Receive Queue Descriptor Start Address
  319. MAR0 = 0x240, // Multicast filter.
  320. MAR4 = 0x244,
  321. CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU.
  322. CLM_RESULT = 0x251, // CCA Busy fraction register.
  323. NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU.
  324. NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0.
  325. NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1.
  326. NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2.
  327. NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3.
  328. NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4.
  329. NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5.
  330. NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6
  331. MCTRL = 0x25A, // Measurement Control
  332. NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
  333. NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1].
  334. NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2].
  335. NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3].
  336. NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4].
  337. NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5].
  338. NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6].
  339. NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7].
  340. WFCRC0 = 0x2f0,
  341. WFCRC1 = 0x2f4,
  342. WFCRC2 = 0x2f8,
  343. BW_OPMODE = 0x300, // Bandwidth operation mode
  344. #define BW_OPMODE_11J BIT0
  345. #define BW_OPMODE_5G BIT1
  346. #define BW_OPMODE_20MHZ BIT2
  347. IC_VERRSION = 0x301, //IC_VERSION
  348. MSR = 0x303, // Media Status register
  349. #define MSR_LINK_MASK ((1<<0)|(1<<1))
  350. #define MSR_LINK_MANAGED 2
  351. #define MSR_LINK_NONE 0
  352. #define MSR_LINK_SHIFT 0
  353. #define MSR_LINK_ADHOC 1
  354. #define MSR_LINK_MASTER 3
  355. #define MSR_LINK_ENEDCA (1<<4)
  356. RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long
  357. #define RETRY_LIMIT_SHORT_SHIFT 8
  358. #define RETRY_LIMIT_LONG_SHIFT 0
  359. TSFR = 0x308,
  360. RRSR = 0x310, // Response Rate Set
  361. #define RRSR_RSC_OFFSET 21
  362. #define RRSR_SHORT_OFFSET 23
  363. #define RRSR_RSC_DUPLICATE 0x600000
  364. #define RRSR_RSC_UPSUBCHNL 0x400000
  365. #define RRSR_RSC_LOWSUBCHNL 0x200000
  366. #define RRSR_SHORT 0x800000
  367. #define RRSR_1M BIT0
  368. #define RRSR_2M BIT1
  369. #define RRSR_5_5M BIT2
  370. #define RRSR_11M BIT3
  371. #define RRSR_6M BIT4
  372. #define RRSR_9M BIT5
  373. #define RRSR_12M BIT6
  374. #define RRSR_18M BIT7
  375. #define RRSR_24M BIT8
  376. #define RRSR_36M BIT9
  377. #define RRSR_48M BIT10
  378. #define RRSR_54M BIT11
  379. #define RRSR_MCS0 BIT12
  380. #define RRSR_MCS1 BIT13
  381. #define RRSR_MCS2 BIT14
  382. #define RRSR_MCS3 BIT15
  383. #define RRSR_MCS4 BIT16
  384. #define RRSR_MCS5 BIT17
  385. #define RRSR_MCS6 BIT18
  386. #define RRSR_MCS7 BIT19
  387. #define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not
  388. UFWP = 0x318,
  389. RATR0 = 0x320, // Rate Adaptive Table register1
  390. //----------------------------------------------------------------------------
  391. // 8190 Rate Adaptive Table Register (offset 0x320, 4 byte)
  392. //----------------------------------------------------------------------------
  393. //CCK
  394. #define RATR_1M 0x00000001
  395. #define RATR_2M 0x00000002
  396. #define RATR_55M 0x00000004
  397. #define RATR_11M 0x00000008
  398. //OFDM
  399. #define RATR_6M 0x00000010
  400. #define RATR_9M 0x00000020
  401. #define RATR_12M 0x00000040
  402. #define RATR_18M 0x00000080
  403. #define RATR_24M 0x00000100
  404. #define RATR_36M 0x00000200
  405. #define RATR_48M 0x00000400
  406. #define RATR_54M 0x00000800
  407. //MCS 1 Spatial Stream
  408. #define RATR_MCS0 0x00001000
  409. #define RATR_MCS1 0x00002000
  410. #define RATR_MCS2 0x00004000
  411. #define RATR_MCS3 0x00008000
  412. #define RATR_MCS4 0x00010000
  413. #define RATR_MCS5 0x00020000
  414. #define RATR_MCS6 0x00040000
  415. #define RATR_MCS7 0x00080000
  416. //MCS 2 Spatial Stream
  417. #define RATR_MCS8 0x00100000
  418. #define RATR_MCS9 0x00200000
  419. #define RATR_MCS10 0x00400000
  420. #define RATR_MCS11 0x00800000
  421. #define RATR_MCS12 0x01000000
  422. #define RATR_MCS13 0x02000000
  423. #define RATR_MCS14 0x04000000
  424. #define RATR_MCS15 0x08000000
  425. // ALL CCK Rate
  426. #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
  427. #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|RATR_36M|RATR_48M|RATR_54M
  428. #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
  429. RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7
  430. #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
  431. RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
  432. DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI
  433. MCS_TXAGC = 0x340, // MCS AGC
  434. CCK_TXAGC = 0x348, // CCK AGC
  435. MacBlkCtrl = 0x403, // Mac block on/off control register
  436. };
  437. #define GPI 0x108
  438. #define GPO 0x109
  439. #define GPE 0x10a
  440. #define ANAPAR_FOR_8192PciE 0x17 // Analog parameter register
  441. #define MSR_NOLINK 0x00
  442. #define MSR_ADHOC 0x01
  443. #define MSR_INFRA 0x02
  444. #define MSR_AP 0x03
  445. #endif