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/drivers/staging/iio/meter/ade7758.h

https://bitbucket.org/wisechild/galaxy-nexus
C++ Header | 188 lines | 146 code | 20 blank | 22 comment | 0 complexity | 972f67ff9b169ffe642332f3255a5931 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * ADE7758 Poly Phase Multifunction Energy Metering IC driver
  3. *
  4. * Copyright 2010-2011 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2.
  7. */
  8. #ifndef _ADE7758_H
  9. #define _ADE7758_H
  10. #define ADE7758_AWATTHR 0x01
  11. #define ADE7758_BWATTHR 0x02
  12. #define ADE7758_CWATTHR 0x03
  13. #define ADE7758_AVARHR 0x04
  14. #define ADE7758_BVARHR 0x05
  15. #define ADE7758_CVARHR 0x06
  16. #define ADE7758_AVAHR 0x07
  17. #define ADE7758_BVAHR 0x08
  18. #define ADE7758_CVAHR 0x09
  19. #define ADE7758_AIRMS 0x0A
  20. #define ADE7758_BIRMS 0x0B
  21. #define ADE7758_CIRMS 0x0C
  22. #define ADE7758_AVRMS 0x0D
  23. #define ADE7758_BVRMS 0x0E
  24. #define ADE7758_CVRMS 0x0F
  25. #define ADE7758_FREQ 0x10
  26. #define ADE7758_TEMP 0x11
  27. #define ADE7758_WFORM 0x12
  28. #define ADE7758_OPMODE 0x13
  29. #define ADE7758_MMODE 0x14
  30. #define ADE7758_WAVMODE 0x15
  31. #define ADE7758_COMPMODE 0x16
  32. #define ADE7758_LCYCMODE 0x17
  33. #define ADE7758_MASK 0x18
  34. #define ADE7758_STATUS 0x19
  35. #define ADE7758_RSTATUS 0x1A
  36. #define ADE7758_ZXTOUT 0x1B
  37. #define ADE7758_LINECYC 0x1C
  38. #define ADE7758_SAGCYC 0x1D
  39. #define ADE7758_SAGLVL 0x1E
  40. #define ADE7758_VPINTLVL 0x1F
  41. #define ADE7758_IPINTLVL 0x20
  42. #define ADE7758_VPEAK 0x21
  43. #define ADE7758_IPEAK 0x22
  44. #define ADE7758_GAIN 0x23
  45. #define ADE7758_AVRMSGAIN 0x24
  46. #define ADE7758_BVRMSGAIN 0x25
  47. #define ADE7758_CVRMSGAIN 0x26
  48. #define ADE7758_AIGAIN 0x27
  49. #define ADE7758_BIGAIN 0x28
  50. #define ADE7758_CIGAIN 0x29
  51. #define ADE7758_AWG 0x2A
  52. #define ADE7758_BWG 0x2B
  53. #define ADE7758_CWG 0x2C
  54. #define ADE7758_AVARG 0x2D
  55. #define ADE7758_BVARG 0x2E
  56. #define ADE7758_CVARG 0x2F
  57. #define ADE7758_AVAG 0x30
  58. #define ADE7758_BVAG 0x31
  59. #define ADE7758_CVAG 0x32
  60. #define ADE7758_AVRMSOS 0x33
  61. #define ADE7758_BVRMSOS 0x34
  62. #define ADE7758_CVRMSOS 0x35
  63. #define ADE7758_AIRMSOS 0x36
  64. #define ADE7758_BIRMSOS 0x37
  65. #define ADE7758_CIRMSOS 0x38
  66. #define ADE7758_AWAITOS 0x39
  67. #define ADE7758_BWAITOS 0x3A
  68. #define ADE7758_CWAITOS 0x3B
  69. #define ADE7758_AVAROS 0x3C
  70. #define ADE7758_BVAROS 0x3D
  71. #define ADE7758_CVAROS 0x3E
  72. #define ADE7758_APHCAL 0x3F
  73. #define ADE7758_BPHCAL 0x40
  74. #define ADE7758_CPHCAL 0x41
  75. #define ADE7758_WDIV 0x42
  76. #define ADE7758_VADIV 0x44
  77. #define ADE7758_VARDIV 0x43
  78. #define ADE7758_APCFNUM 0x45
  79. #define ADE7758_APCFDEN 0x46
  80. #define ADE7758_VARCFNUM 0x47
  81. #define ADE7758_VARCFDEN 0x48
  82. #define ADE7758_CHKSUM 0x7E
  83. #define ADE7758_VERSION 0x7F
  84. #define ADE7758_READ_REG(a) a
  85. #define ADE7758_WRITE_REG(a) ((a) | 0x80)
  86. #define ADE7758_MAX_TX 8
  87. #define ADE7758_MAX_RX 4
  88. #define ADE7758_STARTUP_DELAY 1
  89. #define AD7758_NUM_WAVSEL 5
  90. #define AD7758_NUM_PHSEL 3
  91. #define AD7758_NUM_WAVESRC (AD7758_NUM_WAVSEL * AD7758_NUM_PHSEL)
  92. #define AD7758_PHASE_A 0
  93. #define AD7758_PHASE_B 1
  94. #define AD7758_PHASE_C 2
  95. #define AD7758_CURRENT 0
  96. #define AD7758_VOLTAGE 1
  97. #define AD7758_ACT_PWR 2
  98. #define AD7758_REACT_PWR 3
  99. #define AD7758_APP_PWR 4
  100. #define AD7758_WT(p, w) (((w) << 2) | (p))
  101. #define DRIVER_NAME "ade7758"
  102. /**
  103. * struct ade7758_state - device instance specific data
  104. * @us: actual spi_device
  105. * @trig: data ready trigger registered with iio
  106. * @tx: transmit buffer
  107. * @rx: receive buffer
  108. * @buf_lock: mutex to protect tx and rx
  109. **/
  110. struct ade7758_state {
  111. struct spi_device *us;
  112. struct iio_trigger *trig;
  113. u8 *tx;
  114. u8 *rx;
  115. struct mutex buf_lock;
  116. u32 available_scan_masks[AD7758_NUM_WAVESRC];
  117. struct iio_chan_spec *ade7758_ring_channels;
  118. struct spi_transfer ring_xfer[4];
  119. struct spi_message ring_msg;
  120. /*
  121. * DMA (thus cache coherency maintenance) requires the
  122. * transfer buffers to live in their own cache lines.
  123. */
  124. unsigned char rx_buf[8] ____cacheline_aligned;
  125. unsigned char tx_buf[8];
  126. };
  127. #ifdef CONFIG_IIO_RING_BUFFER
  128. /* At the moment triggers are only used for ring buffer
  129. * filling. This may change!
  130. */
  131. void ade7758_remove_trigger(struct iio_dev *indio_dev);
  132. int ade7758_probe_trigger(struct iio_dev *indio_dev);
  133. ssize_t ade7758_read_data_from_ring(struct device *dev,
  134. struct device_attribute *attr,
  135. char *buf);
  136. int ade7758_configure_ring(struct iio_dev *indio_dev);
  137. void ade7758_unconfigure_ring(struct iio_dev *indio_dev);
  138. int ade7758_initialize_ring(struct iio_ring_buffer *ring);
  139. void ade7758_uninitialize_ring(struct iio_ring_buffer *ring);
  140. int ade7758_set_irq(struct device *dev, bool enable);
  141. int ade7758_spi_write_reg_8(struct device *dev,
  142. u8 reg_address, u8 val);
  143. int ade7758_spi_read_reg_8(struct device *dev,
  144. u8 reg_address, u8 *val);
  145. #else /* CONFIG_IIO_RING_BUFFER */
  146. static inline void ade7758_remove_trigger(struct iio_dev *indio_dev)
  147. {
  148. }
  149. static inline int ade7758_probe_trigger(struct iio_dev *indio_dev)
  150. {
  151. return 0;
  152. }
  153. static int ade7758_configure_ring(struct iio_dev *indio_dev)
  154. {
  155. return 0;
  156. }
  157. static inline void ade7758_unconfigure_ring(struct iio_dev *indio_dev)
  158. {
  159. }
  160. static inline int ade7758_initialize_ring(struct iio_ring_buffer *ring)
  161. {
  162. return 0;
  163. }
  164. static inline void ade7758_uninitialize_ring(struct iio_ring_buffer *ring)
  165. {
  166. }
  167. #endif /* CONFIG_IIO_RING_BUFFER */
  168. #endif