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/drivers/staging/iio/dds/ad9832.h

https://bitbucket.org/wisechild/galaxy-nexus
C++ Header | 128 lines | 71 code | 12 blank | 45 comment | 0 complexity | 426f418a71b9bfa17f82c685b9b5a945 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0 
    

  1. /*
    2. 

  2.  * AD9832 SPI DDS driver
    3. 

  3.  *
    4. 

  4.  * Copyright 2011 Analog Devices Inc.
    5. 

  5.  *
    6. 

  6.  * Licensed under the GPL-2 or later.
    7. 

  7.  */
    8. 

  8. #ifndef IIO_DDS_AD9832_H_
    9. 

  9. #define IIO_DDS_AD9832_H_
    10. 

  10. 

  11. /* Registers */
    12. 

  12. 

  13. #define AD9832_FREQ0LL		0x0
    14. 

  14. #define AD9832_FREQ0HL		0x1
    15. 

  15. #define AD9832_FREQ0LM		0x2
    16. 

  16. #define AD9832_FREQ0HM		0x3
    17. 

  17. #define AD9832_FREQ1LL		0x4
    18. 

  18. #define AD9832_FREQ1HL		0x5
    19. 

  19. #define AD9832_FREQ1LM		0x6
    20. 

  20. #define AD9832_FREQ1HM		0x7
    21. 

  21. #define AD9832_PHASE0L		0x8
    22. 

  22. #define AD9832_PHASE0H		0x9
    23. 

  23. #define AD9832_PHASE1L		0xA
    24. 

  24. #define AD9832_PHASE1H		0xB
    25. 

  25. #define AD9832_PHASE2L		0xC
    26. 

  26. #define AD9832_PHASE2H		0xD
    27. 

  27. #define AD9832_PHASE3L		0xE
    28. 

  28. #define AD9832_PHASE3H		0xF
    29. 

  29. 

  30. #define AD9832_PHASE_SYM	0x10
    31. 

  31. #define AD9832_FREQ_SYM		0x11
    32. 

  32. #define AD9832_PINCTRL_EN	0x12
    33. 

  33. #define AD9832_OUTPUT_EN	0x13
    34. 

  34. 

  35. /* Command Control Bits */
    36. 

  36. 

  37. #define AD9832_CMD_PHA8BITSW	0x1
    38. 

  38. #define AD9832_CMD_PHA16BITSW	0x0
    39. 

  39. #define AD9832_CMD_FRE8BITSW	0x3
    40. 

  40. #define AD9832_CMD_FRE16BITSW	0x2
    41. 

  41. #define AD9832_CMD_FPSELECT	0x6
    42. 

  42. #define AD9832_CMD_SYNCSELSRC	0x8
    43. 

  43. #define AD9832_CMD_SLEEPRESCLR	0xC
    44. 

  44. 

  45. #define AD9832_FREQ		(1 << 11)
    46. 

  46. #define AD9832_PHASE(x)		(((x) & 3) << 9)
    47. 

  47. #define AD9832_SYNC		(1 << 13)
    48. 

  48. #define AD9832_SELSRC		(1 << 12)
    49. 

  49. #define AD9832_SLEEP		(1 << 13)
    50. 

  50. #define AD9832_RESET		(1 << 12)
    51. 

  51. #define AD9832_CLR		(1 << 11)
    52. 

  52. #define CMD_SHIFT		12
    53. 

  53. #define ADD_SHIFT		8
    54. 

  54. #define AD9832_FREQ_BITS	32
    55. 

  55. #define AD9832_PHASE_BITS	12
    56. 

  56. #define RES_MASK(bits)		((1 << (bits)) - 1)
    57. 

  57. 

  58. /**
    59. 

  59.  * struct ad9832_state - driver instance specific data
    60. 

  60.  * @indio_dev:		the industrial I/O device
    61. 

  61.  * @spi:		spi_device
    62. 

  62.  * @reg:		supply regulator
    63. 

  63.  * @mclk:		external master clock
    64. 

  64.  * @ctrl_fp:		cached frequency/phase control word
    65. 

  65.  * @ctrl_ss:		cached sync/selsrc control word
    66. 

  66.  * @ctrl_src:		cached sleep/reset/clr word
    67. 

  67.  * @xfer:		default spi transfer
    68. 

  68.  * @msg:		default spi message
    69. 

  69.  * @freq_xfer:		tuning word spi transfer
    70. 

  70.  * @freq_msg:		tuning word spi message
    71. 

  71.  * @phase_xfer:		tuning word spi transfer
    72. 

  72.  * @phase_msg:		tuning word spi message
    73. 

  73.  * @data:		spi transmit buffer
    74. 

  74.  * @phase_data:		tuning word spi transmit buffer
    75. 

  75.  * @freq_data:		tuning word spi transmit buffer
    76. 

  76.  */
    77. 

  77. 

  78. struct ad9832_state {
    79. 

  79. 	struct iio_dev			*indio_dev;
    80. 

  80. 	struct spi_device		*spi;
    81. 

  81. 	struct regulator		*reg;
    82. 

  82. 	unsigned long			mclk;
    83. 

  83. 	unsigned short			ctrl_fp;
    84. 

  84. 	unsigned short			ctrl_ss;
    85. 

  85. 	unsigned short			ctrl_src;
    86. 

  86. 	struct spi_transfer		xfer;
    87. 

  87. 	struct spi_message		msg;
    88. 

  88. 	struct spi_transfer		freq_xfer[4];
    89. 

  89. 	struct spi_message		freq_msg;
    90. 

  90. 	struct spi_transfer		phase_xfer[2];
    91. 

  91. 	struct spi_message		phase_msg;
    92. 

  92. 	/*
    93. 

  93. 	 * DMA (thus cache coherency maintenance) requires the
    94. 

  94. 	 * transfer buffers to live in their own cache lines.
    95. 

  95. 	 */
    96. 

  96. 	union {
    97. 

  97. 		unsigned short		freq_data[4]____cacheline_aligned;
    98. 

  98. 		unsigned short		phase_data[2];
    99. 

  99. 		unsigned short		data;
    100. 

  100. 	};
    101. 

  101. };
    102. 

  102. 

  103. /*
    104. 

  104.  * TODO: struct ad9832_platform_data needs to go into include/linux/iio
    105. 

  105.  */
    106. 

  106. 

  107. /**
    108. 

  108.  * struct ad9832_platform_data - platform specific information
    109. 

  109.  * @mclk:		master clock in Hz
    110. 

  110.  * @freq0:		power up freq0 tuning word in Hz
    111. 

  111.  * @freq1:		power up freq1 tuning word in Hz
    112. 

  112.  * @phase0:		power up phase0 value [0..4095] correlates with 0..2PI
    113. 

  113.  * @phase1:		power up phase1 value [0..4095] correlates with 0..2PI
    114. 

  114.  * @phase2:		power up phase2 value [0..4095] correlates with 0..2PI
    115. 

  115.  * @phase3:		power up phase3 value [0..4095] correlates with 0..2PI
    116. 

  116.  */
    117. 

  117. 

  118. struct ad9832_platform_data {
    119. 

  119. 	unsigned long		mclk;
    120. 

  120. 	unsigned long		freq0;
    121. 

  121. 	unsigned long		freq1;
    122. 

  122. 	unsigned short		phase0;
    123. 

  123. 	unsigned short		phase1;
    124. 

  124. 	unsigned short		phase2;
    125. 

  125. 	unsigned short		phase3;
    126. 

  126. };
    127. 

  127. 

  128. #endif /* IIO_DDS_AD9832_H_ */
    129. 

  129.