/drivers/net/sis900.c
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Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
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1/* sis900.c: A SiS 900/7016 PCI Fast Ethernet driver for Linux.
2 Copyright 1999 Silicon Integrated System Corporation
3 Revision: 1.08.10 Apr. 2 2006
4
5 Modified from the driver which is originally written by Donald Becker.
6
7 This software may be used and distributed according to the terms
8 of the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on this skeleton fall under the GPL and must retain
10 the authorship (implicit copyright) notice.
11
12 References:
13 SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
14 preliminary Rev. 1.0 Jan. 14, 1998
15 SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
16 preliminary Rev. 1.0 Nov. 10, 1998
17 SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
18 preliminary Rev. 1.0 Jan. 18, 1998
19
20 Rev 1.08.10 Apr. 2 2006 Daniele Venzano add vlan (jumbo packets) support
21 Rev 1.08.09 Sep. 19 2005 Daniele Venzano add Wake on LAN support
22 Rev 1.08.08 Jan. 22 2005 Daniele Venzano use netif_msg for debugging messages
23 Rev 1.08.07 Nov. 2 2003 Daniele Venzano <venza@brownhat.org> add suspend/resume support
24 Rev 1.08.06 Sep. 24 2002 Mufasa Yang bug fix for Tx timeout & add SiS963 support
25 Rev 1.08.05 Jun. 6 2002 Mufasa Yang bug fix for read_eeprom & Tx descriptor over-boundary
26 Rev 1.08.04 Apr. 25 2002 Mufasa Yang <mufasa@sis.com.tw> added SiS962 support
27 Rev 1.08.03 Feb. 1 2002 Matt Domsch <Matt_Domsch@dell.com> update to use library crc32 function
28 Rev 1.08.02 Nov. 30 2001 Hui-Fen Hsu workaround for EDB & bug fix for dhcp problem
29 Rev 1.08.01 Aug. 25 2001 Hui-Fen Hsu update for 630ET & workaround for ICS1893 PHY
30 Rev 1.08.00 Jun. 11 2001 Hui-Fen Hsu workaround for RTL8201 PHY and some bug fix
31 Rev 1.07.11 Apr. 2 2001 Hui-Fen Hsu updates PCI drivers to use the new pci_set_dma_mask for kernel 2.4.3
32 Rev 1.07.10 Mar. 1 2001 Hui-Fen Hsu <hfhsu@sis.com.tw> some bug fix & 635M/B support
33 Rev 1.07.09 Feb. 9 2001 Dave Jones <davej@suse.de> PCI enable cleanup
34 Rev 1.07.08 Jan. 8 2001 Lei-Chun Chang added RTL8201 PHY support
35 Rev 1.07.07 Nov. 29 2000 Lei-Chun Chang added kernel-doc extractable documentation and 630 workaround fix
36 Rev 1.07.06 Nov. 7 2000 Jeff Garzik <jgarzik@pobox.com> some bug fix and cleaning
37 Rev 1.07.05 Nov. 6 2000 metapirat<metapirat@gmx.de> contribute media type select by ifconfig
38 Rev 1.07.04 Sep. 6 2000 Lei-Chun Chang added ICS1893 PHY support
39 Rev 1.07.03 Aug. 24 2000 Lei-Chun Chang (lcchang@sis.com.tw) modified 630E equalizer workaround rule
40 Rev 1.07.01 Aug. 08 2000 Ollie Lho minor update for SiS 630E and SiS 630E A1
41 Rev 1.07 Mar. 07 2000 Ollie Lho bug fix in Rx buffer ring
42 Rev 1.06.04 Feb. 11 2000 Jeff Garzik <jgarzik@pobox.com> softnet and init for kernel 2.4
43 Rev 1.06.03 Dec. 23 1999 Ollie Lho Third release
44 Rev 1.06.02 Nov. 23 1999 Ollie Lho bug in mac probing fixed
45 Rev 1.06.01 Nov. 16 1999 Ollie Lho CRC calculation provide by Joseph Zbiciak (im14u2c@primenet.com)
46 Rev 1.06 Nov. 4 1999 Ollie Lho (ollie@sis.com.tw) Second release
47 Rev 1.05.05 Oct. 29 1999 Ollie Lho (ollie@sis.com.tw) Single buffer Tx/Rx
48 Chin-Shan Li (lcs@sis.com.tw) Added AMD Am79c901 HomePNA PHY support
49 Rev 1.05 Aug. 7 1999 Jim Huang (cmhuang@sis.com.tw) Initial release
50*/
51
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/kernel.h>
55#include <linux/sched.h>
56#include <linux/string.h>
57#include <linux/timer.h>
58#include <linux/errno.h>
59#include <linux/ioport.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
63#include <linux/netdevice.h>
64#include <linux/init.h>
65#include <linux/mii.h>
66#include <linux/etherdevice.h>
67#include <linux/skbuff.h>
68#include <linux/delay.h>
69#include <linux/ethtool.h>
70#include <linux/crc32.h>
71#include <linux/bitops.h>
72#include <linux/dma-mapping.h>
73
74#include <asm/processor.h> /* Processor type for cache alignment. */
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/uaccess.h> /* User space memory access functions */
78
79#include "sis900.h"
80
81#define SIS900_MODULE_NAME "sis900"
82#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
83
84static const char version[] __devinitconst =
85 KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
86
87static int max_interrupt_work = 40;
88static int multicast_filter_limit = 128;
89
90static int sis900_debug = -1; /* Use SIS900_DEF_MSG as value */
91
92#define SIS900_DEF_MSG \
93 (NETIF_MSG_DRV | \
94 NETIF_MSG_LINK | \
95 NETIF_MSG_RX_ERR | \
96 NETIF_MSG_TX_ERR)
97
98/* Time in jiffies before concluding the transmitter is hung. */
99#define TX_TIMEOUT (4*HZ)
100
101enum {
102 SIS_900 = 0,
103 SIS_7016
104};
105static const char * card_names[] = {
106 "SiS 900 PCI Fast Ethernet",
107 "SiS 7016 PCI Fast Ethernet"
108};
109static DEFINE_PCI_DEVICE_TABLE(sis900_pci_tbl) = {
110 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_900,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
112 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7016,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
114 {0,}
115};
116MODULE_DEVICE_TABLE (pci, sis900_pci_tbl);
117
118static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex);
119
120static const struct mii_chip_info {
121 const char * name;
122 u16 phy_id0;
123 u16 phy_id1;
124 u8 phy_types;
125#define HOME 0x0001
126#define LAN 0x0002
127#define MIX 0x0003
128#define UNKNOWN 0x0
129} mii_chip_table[] = {
130 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
131 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
132 { "SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, LAN },
133 { "Altimata AC101LF PHY", 0x0022, 0x5520, LAN },
134 { "ADM 7001 LAN PHY", 0x002e, 0xcc60, LAN },
135 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
136 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
137 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
138 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
139 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
140 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
141 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
142 { "VIA 6103 PHY", 0x0101, 0x8f20, LAN },
143 {NULL,},
144};
145
146struct mii_phy {
147 struct mii_phy * next;
148 int phy_addr;
149 u16 phy_id0;
150 u16 phy_id1;
151 u16 status;
152 u8 phy_types;
153};
154
155typedef struct _BufferDesc {
156 u32 link;
157 u32 cmdsts;
158 u32 bufptr;
159} BufferDesc;
160
161struct sis900_private {
162 struct pci_dev * pci_dev;
163
164 spinlock_t lock;
165
166 struct mii_phy * mii;
167 struct mii_phy * first_mii; /* record the first mii structure */
168 unsigned int cur_phy;
169 struct mii_if_info mii_info;
170
171 struct timer_list timer; /* Link status detection timer. */
172 u8 autong_complete; /* 1: auto-negotiate complete */
173
174 u32 msg_enable;
175
176 unsigned int cur_rx, dirty_rx; /* producer/comsumer pointers for Tx/Rx ring */
177 unsigned int cur_tx, dirty_tx;
178
179 /* The saved address of a sent/receive-in-place packet buffer */
180 struct sk_buff *tx_skbuff[NUM_TX_DESC];
181 struct sk_buff *rx_skbuff[NUM_RX_DESC];
182 BufferDesc *tx_ring;
183 BufferDesc *rx_ring;
184
185 dma_addr_t tx_ring_dma;
186 dma_addr_t rx_ring_dma;
187
188 unsigned int tx_full; /* The Tx queue is full. */
189 u8 host_bridge_rev;
190 u8 chipset_rev;
191};
192
193MODULE_AUTHOR("Jim Huang <cmhuang@sis.com.tw>, Ollie Lho <ollie@sis.com.tw>");
194MODULE_DESCRIPTION("SiS 900 PCI Fast Ethernet driver");
195MODULE_LICENSE("GPL");
196
197module_param(multicast_filter_limit, int, 0444);
198module_param(max_interrupt_work, int, 0444);
199module_param(sis900_debug, int, 0444);
200MODULE_PARM_DESC(multicast_filter_limit, "SiS 900/7016 maximum number of filtered multicast addresses");
201MODULE_PARM_DESC(max_interrupt_work, "SiS 900/7016 maximum events handled per interrupt");
202MODULE_PARM_DESC(sis900_debug, "SiS 900/7016 bitmapped debugging message level");
203
204#ifdef CONFIG_NET_POLL_CONTROLLER
205static void sis900_poll(struct net_device *dev);
206#endif
207static int sis900_open(struct net_device *net_dev);
208static int sis900_mii_probe (struct net_device * net_dev);
209static void sis900_init_rxfilter (struct net_device * net_dev);
210static u16 read_eeprom(long ioaddr, int location);
211static int mdio_read(struct net_device *net_dev, int phy_id, int location);
212static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
213static void sis900_timer(unsigned long data);
214static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
215static void sis900_tx_timeout(struct net_device *net_dev);
216static void sis900_init_tx_ring(struct net_device *net_dev);
217static void sis900_init_rx_ring(struct net_device *net_dev);
218static netdev_tx_t sis900_start_xmit(struct sk_buff *skb,
219 struct net_device *net_dev);
220static int sis900_rx(struct net_device *net_dev);
221static void sis900_finish_xmit (struct net_device *net_dev);
222static irqreturn_t sis900_interrupt(int irq, void *dev_instance);
223static int sis900_close(struct net_device *net_dev);
224static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
225static u16 sis900_mcast_bitnr(u8 *addr, u8 revision);
226static void set_rx_mode(struct net_device *net_dev);
227static void sis900_reset(struct net_device *net_dev);
228static void sis630_set_eq(struct net_device *net_dev, u8 revision);
229static int sis900_set_config(struct net_device *dev, struct ifmap *map);
230static u16 sis900_default_phy(struct net_device * net_dev);
231static void sis900_set_capability( struct net_device *net_dev ,struct mii_phy *phy);
232static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr);
233static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr);
234static void sis900_set_mode (long ioaddr, int speed, int duplex);
235static const struct ethtool_ops sis900_ethtool_ops;
236
237/**
238 * sis900_get_mac_addr - Get MAC address for stand alone SiS900 model
239 * @pci_dev: the sis900 pci device
240 * @net_dev: the net device to get address for
241 *
242 * Older SiS900 and friends, use EEPROM to store MAC address.
243 * MAC address is read from read_eeprom() into @net_dev->dev_addr and
244 * @net_dev->perm_addr.
245 */
246
247static int __devinit sis900_get_mac_addr(struct pci_dev * pci_dev, struct net_device *net_dev)
248{
249 long ioaddr = pci_resource_start(pci_dev, 0);
250 u16 signature;
251 int i;
252
253 /* check to see if we have sane EEPROM */
254 signature = (u16) read_eeprom(ioaddr, EEPROMSignature);
255 if (signature == 0xffff || signature == 0x0000) {
256 printk (KERN_WARNING "%s: Error EERPOM read %x\n",
257 pci_name(pci_dev), signature);
258 return 0;
259 }
260
261 /* get MAC address from EEPROM */
262 for (i = 0; i < 3; i++)
263 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
264
265 /* Store MAC Address in perm_addr */
266 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
267
268 return 1;
269}
270
271/**
272 * sis630e_get_mac_addr - Get MAC address for SiS630E model
273 * @pci_dev: the sis900 pci device
274 * @net_dev: the net device to get address for
275 *
276 * SiS630E model, use APC CMOS RAM to store MAC address.
277 * APC CMOS RAM is accessed through ISA bridge.
278 * MAC address is read into @net_dev->dev_addr and
279 * @net_dev->perm_addr.
280 */
281
282static int __devinit sis630e_get_mac_addr(struct pci_dev * pci_dev,
283 struct net_device *net_dev)
284{
285 struct pci_dev *isa_bridge = NULL;
286 u8 reg;
287 int i;
288
289 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, isa_bridge);
290 if (!isa_bridge)
291 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0018, isa_bridge);
292 if (!isa_bridge) {
293 printk(KERN_WARNING "%s: Can not find ISA bridge\n",
294 pci_name(pci_dev));
295 return 0;
296 }
297 pci_read_config_byte(isa_bridge, 0x48, ®);
298 pci_write_config_byte(isa_bridge, 0x48, reg | 0x40);
299
300 for (i = 0; i < 6; i++) {
301 outb(0x09 + i, 0x70);
302 ((u8 *)(net_dev->dev_addr))[i] = inb(0x71);
303 }
304
305 /* Store MAC Address in perm_addr */
306 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
307
308 pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40);
309 pci_dev_put(isa_bridge);
310
311 return 1;
312}
313
314
315/**
316 * sis635_get_mac_addr - Get MAC address for SIS635 model
317 * @pci_dev: the sis900 pci device
318 * @net_dev: the net device to get address for
319 *
320 * SiS635 model, set MAC Reload Bit to load Mac address from APC
321 * to rfdr. rfdr is accessed through rfcr. MAC address is read into
322 * @net_dev->dev_addr and @net_dev->perm_addr.
323 */
324
325static int __devinit sis635_get_mac_addr(struct pci_dev * pci_dev,
326 struct net_device *net_dev)
327{
328 long ioaddr = net_dev->base_addr;
329 u32 rfcrSave;
330 u32 i;
331
332 rfcrSave = inl(rfcr + ioaddr);
333
334 outl(rfcrSave | RELOAD, ioaddr + cr);
335 outl(0, ioaddr + cr);
336
337 /* disable packet filtering before setting filter */
338 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
339
340 /* load MAC addr to filter data register */
341 for (i = 0 ; i < 3 ; i++) {
342 outl((i << RFADDR_shift), ioaddr + rfcr);
343 *( ((u16 *)net_dev->dev_addr) + i) = inw(ioaddr + rfdr);
344 }
345
346 /* Store MAC Address in perm_addr */
347 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
348
349 /* enable packet filtering */
350 outl(rfcrSave | RFEN, rfcr + ioaddr);
351
352 return 1;
353}
354
355/**
356 * sis96x_get_mac_addr - Get MAC address for SiS962 or SiS963 model
357 * @pci_dev: the sis900 pci device
358 * @net_dev: the net device to get address for
359 *
360 * SiS962 or SiS963 model, use EEPROM to store MAC address. And EEPROM
361 * is shared by
362 * LAN and 1394. When access EEPROM, send EEREQ signal to hardware first
363 * and wait for EEGNT. If EEGNT is ON, EEPROM is permitted to be access
364 * by LAN, otherwise is not. After MAC address is read from EEPROM, send
365 * EEDONE signal to refuse EEPROM access by LAN.
366 * The EEPROM map of SiS962 or SiS963 is different to SiS900.
367 * The signature field in SiS962 or SiS963 spec is meaningless.
368 * MAC address is read into @net_dev->dev_addr and @net_dev->perm_addr.
369 */
370
371static int __devinit sis96x_get_mac_addr(struct pci_dev * pci_dev,
372 struct net_device *net_dev)
373{
374 long ioaddr = net_dev->base_addr;
375 long ee_addr = ioaddr + mear;
376 u32 waittime = 0;
377 int i;
378
379 outl(EEREQ, ee_addr);
380 while(waittime < 2000) {
381 if(inl(ee_addr) & EEGNT) {
382
383 /* get MAC address from EEPROM */
384 for (i = 0; i < 3; i++)
385 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
386
387 /* Store MAC Address in perm_addr */
388 memcpy(net_dev->perm_addr, net_dev->dev_addr, ETH_ALEN);
389
390 outl(EEDONE, ee_addr);
391 return 1;
392 } else {
393 udelay(1);
394 waittime ++;
395 }
396 }
397 outl(EEDONE, ee_addr);
398 return 0;
399}
400
401static const struct net_device_ops sis900_netdev_ops = {
402 .ndo_open = sis900_open,
403 .ndo_stop = sis900_close,
404 .ndo_start_xmit = sis900_start_xmit,
405 .ndo_set_config = sis900_set_config,
406 .ndo_set_multicast_list = set_rx_mode,
407 .ndo_change_mtu = eth_change_mtu,
408 .ndo_validate_addr = eth_validate_addr,
409 .ndo_set_mac_address = eth_mac_addr,
410 .ndo_do_ioctl = mii_ioctl,
411 .ndo_tx_timeout = sis900_tx_timeout,
412#ifdef CONFIG_NET_POLL_CONTROLLER
413 .ndo_poll_controller = sis900_poll,
414#endif
415};
416
417/**
418 * sis900_probe - Probe for sis900 device
419 * @pci_dev: the sis900 pci device
420 * @pci_id: the pci device ID
421 *
422 * Check and probe sis900 net device for @pci_dev.
423 * Get mac address according to the chip revision,
424 * and assign SiS900-specific entries in the device structure.
425 * ie: sis900_open(), sis900_start_xmit(), sis900_close(), etc.
426 */
427
428static int __devinit sis900_probe(struct pci_dev *pci_dev,
429 const struct pci_device_id *pci_id)
430{
431 struct sis900_private *sis_priv;
432 struct net_device *net_dev;
433 struct pci_dev *dev;
434 dma_addr_t ring_dma;
435 void *ring_space;
436 long ioaddr;
437 int i, ret;
438 const char *card_name = card_names[pci_id->driver_data];
439 const char *dev_name = pci_name(pci_dev);
440
441/* when built into the kernel, we only print version if device is found */
442#ifndef MODULE
443 static int printed_version;
444 if (!printed_version++)
445 printk(version);
446#endif
447
448 /* setup various bits in PCI command register */
449 ret = pci_enable_device(pci_dev);
450 if(ret) return ret;
451
452 i = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
453 if(i){
454 printk(KERN_ERR "sis900.c: architecture does not support "
455 "32bit PCI busmaster DMA\n");
456 return i;
457 }
458
459 pci_set_master(pci_dev);
460
461 net_dev = alloc_etherdev(sizeof(struct sis900_private));
462 if (!net_dev)
463 return -ENOMEM;
464 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
465
466 /* We do a request_region() to register /proc/ioports info. */
467 ioaddr = pci_resource_start(pci_dev, 0);
468 ret = pci_request_regions(pci_dev, "sis900");
469 if (ret)
470 goto err_out;
471
472 sis_priv = netdev_priv(net_dev);
473 net_dev->base_addr = ioaddr;
474 net_dev->irq = pci_dev->irq;
475 sis_priv->pci_dev = pci_dev;
476 spin_lock_init(&sis_priv->lock);
477
478 pci_set_drvdata(pci_dev, net_dev);
479
480 ring_space = pci_alloc_consistent(pci_dev, TX_TOTAL_SIZE, &ring_dma);
481 if (!ring_space) {
482 ret = -ENOMEM;
483 goto err_out_cleardev;
484 }
485 sis_priv->tx_ring = (BufferDesc *)ring_space;
486 sis_priv->tx_ring_dma = ring_dma;
487
488 ring_space = pci_alloc_consistent(pci_dev, RX_TOTAL_SIZE, &ring_dma);
489 if (!ring_space) {
490 ret = -ENOMEM;
491 goto err_unmap_tx;
492 }
493 sis_priv->rx_ring = (BufferDesc *)ring_space;
494 sis_priv->rx_ring_dma = ring_dma;
495
496 /* The SiS900-specific entries in the device structure. */
497 net_dev->netdev_ops = &sis900_netdev_ops;
498 net_dev->watchdog_timeo = TX_TIMEOUT;
499 net_dev->ethtool_ops = &sis900_ethtool_ops;
500
501 if (sis900_debug > 0)
502 sis_priv->msg_enable = sis900_debug;
503 else
504 sis_priv->msg_enable = SIS900_DEF_MSG;
505
506 sis_priv->mii_info.dev = net_dev;
507 sis_priv->mii_info.mdio_read = mdio_read;
508 sis_priv->mii_info.mdio_write = mdio_write;
509 sis_priv->mii_info.phy_id_mask = 0x1f;
510 sis_priv->mii_info.reg_num_mask = 0x1f;
511
512 /* Get Mac address according to the chip revision */
513 sis_priv->chipset_rev = pci_dev->revision;
514 if(netif_msg_probe(sis_priv))
515 printk(KERN_DEBUG "%s: detected revision %2.2x, "
516 "trying to get MAC address...\n",
517 dev_name, sis_priv->chipset_rev);
518
519 ret = 0;
520 if (sis_priv->chipset_rev == SIS630E_900_REV)
521 ret = sis630e_get_mac_addr(pci_dev, net_dev);
522 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
523 ret = sis635_get_mac_addr(pci_dev, net_dev);
524 else if (sis_priv->chipset_rev == SIS96x_900_REV)
525 ret = sis96x_get_mac_addr(pci_dev, net_dev);
526 else
527 ret = sis900_get_mac_addr(pci_dev, net_dev);
528
529 if (!ret || !is_valid_ether_addr(net_dev->dev_addr)) {
530 random_ether_addr(net_dev->dev_addr);
531 printk(KERN_WARNING "%s: Unreadable or invalid MAC address,"
532 "using random generated one\n", dev_name);
533 }
534
535 /* 630ET : set the mii access mode as software-mode */
536 if (sis_priv->chipset_rev == SIS630ET_900_REV)
537 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
538
539 /* probe for mii transceiver */
540 if (sis900_mii_probe(net_dev) == 0) {
541 printk(KERN_WARNING "%s: Error probing MII device.\n",
542 dev_name);
543 ret = -ENODEV;
544 goto err_unmap_rx;
545 }
546
547 /* save our host bridge revision */
548 dev = pci_get_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, NULL);
549 if (dev) {
550 sis_priv->host_bridge_rev = dev->revision;
551 pci_dev_put(dev);
552 }
553
554 ret = register_netdev(net_dev);
555 if (ret)
556 goto err_unmap_rx;
557
558 /* print some information about our NIC */
559 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n",
560 net_dev->name, card_name, ioaddr, net_dev->irq,
561 net_dev->dev_addr);
562
563 /* Detect Wake on Lan support */
564 ret = (inl(net_dev->base_addr + CFGPMC) & PMESP) >> 27;
565 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
566 printk(KERN_INFO "%s: Wake on LAN only available from suspend to RAM.", net_dev->name);
567
568 return 0;
569
570 err_unmap_rx:
571 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
572 sis_priv->rx_ring_dma);
573 err_unmap_tx:
574 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
575 sis_priv->tx_ring_dma);
576 err_out_cleardev:
577 pci_set_drvdata(pci_dev, NULL);
578 pci_release_regions(pci_dev);
579 err_out:
580 free_netdev(net_dev);
581 return ret;
582}
583
584/**
585 * sis900_mii_probe - Probe MII PHY for sis900
586 * @net_dev: the net device to probe for
587 *
588 * Search for total of 32 possible mii phy addresses.
589 * Identify and set current phy if found one,
590 * return error if it failed to found.
591 */
592
593static int __devinit sis900_mii_probe(struct net_device * net_dev)
594{
595 struct sis900_private *sis_priv = netdev_priv(net_dev);
596 const char *dev_name = pci_name(sis_priv->pci_dev);
597 u16 poll_bit = MII_STAT_LINK, status = 0;
598 unsigned long timeout = jiffies + 5 * HZ;
599 int phy_addr;
600
601 sis_priv->mii = NULL;
602
603 /* search for total of 32 possible mii phy addresses */
604 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
605 struct mii_phy * mii_phy = NULL;
606 u16 mii_status;
607 int i;
608
609 mii_phy = NULL;
610 for(i = 0; i < 2; i++)
611 mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
612
613 if (mii_status == 0xffff || mii_status == 0x0000) {
614 if (netif_msg_probe(sis_priv))
615 printk(KERN_DEBUG "%s: MII at address %d"
616 " not accessible\n",
617 dev_name, phy_addr);
618 continue;
619 }
620
621 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {
622 printk(KERN_WARNING "Cannot allocate mem for struct mii_phy\n");
623 mii_phy = sis_priv->first_mii;
624 while (mii_phy) {
625 struct mii_phy *phy;
626 phy = mii_phy;
627 mii_phy = mii_phy->next;
628 kfree(phy);
629 }
630 return 0;
631 }
632
633 mii_phy->phy_id0 = mdio_read(net_dev, phy_addr, MII_PHY_ID0);
634 mii_phy->phy_id1 = mdio_read(net_dev, phy_addr, MII_PHY_ID1);
635 mii_phy->phy_addr = phy_addr;
636 mii_phy->status = mii_status;
637 mii_phy->next = sis_priv->mii;
638 sis_priv->mii = mii_phy;
639 sis_priv->first_mii = mii_phy;
640
641 for (i = 0; mii_chip_table[i].phy_id1; i++)
642 if ((mii_phy->phy_id0 == mii_chip_table[i].phy_id0 ) &&
643 ((mii_phy->phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){
644 mii_phy->phy_types = mii_chip_table[i].phy_types;
645 if (mii_chip_table[i].phy_types == MIX)
646 mii_phy->phy_types =
647 (mii_status & (MII_STAT_CAN_TX_FDX | MII_STAT_CAN_TX)) ? LAN : HOME;
648 printk(KERN_INFO "%s: %s transceiver found "
649 "at address %d.\n",
650 dev_name,
651 mii_chip_table[i].name,
652 phy_addr);
653 break;
654 }
655
656 if( !mii_chip_table[i].phy_id1 ) {
657 printk(KERN_INFO "%s: Unknown PHY transceiver found at address %d.\n",
658 dev_name, phy_addr);
659 mii_phy->phy_types = UNKNOWN;
660 }
661 }
662
663 if (sis_priv->mii == NULL) {
664 printk(KERN_INFO "%s: No MII transceivers found!\n", dev_name);
665 return 0;
666 }
667
668 /* select default PHY for mac */
669 sis_priv->mii = NULL;
670 sis900_default_phy( net_dev );
671
672 /* Reset phy if default phy is internal sis900 */
673 if ((sis_priv->mii->phy_id0 == 0x001D) &&
674 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
675 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
676
677 /* workaround for ICS1893 PHY */
678 if ((sis_priv->mii->phy_id0 == 0x0015) &&
679 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
680 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
681
682 if(status & MII_STAT_LINK){
683 while (poll_bit) {
684 yield();
685
686 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
687 if (time_after_eq(jiffies, timeout)) {
688 printk(KERN_WARNING "%s: reset phy and link down now\n",
689 dev_name);
690 return -ETIME;
691 }
692 }
693 }
694
695 if (sis_priv->chipset_rev == SIS630E_900_REV) {
696 /* SiS 630E has some bugs on default value of PHY registers */
697 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
698 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
699 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
700 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
701 //mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, 0x1000);
702 }
703
704 if (sis_priv->mii->status & MII_STAT_LINK)
705 netif_carrier_on(net_dev);
706 else
707 netif_carrier_off(net_dev);
708
709 return 1;
710}
711
712/**
713 * sis900_default_phy - Select default PHY for sis900 mac.
714 * @net_dev: the net device to probe for
715 *
716 * Select first detected PHY with link as default.
717 * If no one is link on, select PHY whose types is HOME as default.
718 * If HOME doesn't exist, select LAN.
719 */
720
721static u16 sis900_default_phy(struct net_device * net_dev)
722{
723 struct sis900_private *sis_priv = netdev_priv(net_dev);
724 struct mii_phy *phy = NULL, *phy_home = NULL,
725 *default_phy = NULL, *phy_lan = NULL;
726 u16 status;
727
728 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
729 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
730 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
731
732 /* Link ON & Not select default PHY & not ghost PHY */
733 if ((status & MII_STAT_LINK) && !default_phy &&
734 (phy->phy_types != UNKNOWN))
735 default_phy = phy;
736 else {
737 status = mdio_read(net_dev, phy->phy_addr, MII_CONTROL);
738 mdio_write(net_dev, phy->phy_addr, MII_CONTROL,
739 status | MII_CNTL_AUTO | MII_CNTL_ISOLATE);
740 if (phy->phy_types == HOME)
741 phy_home = phy;
742 else if(phy->phy_types == LAN)
743 phy_lan = phy;
744 }
745 }
746
747 if (!default_phy && phy_home)
748 default_phy = phy_home;
749 else if (!default_phy && phy_lan)
750 default_phy = phy_lan;
751 else if (!default_phy)
752 default_phy = sis_priv->first_mii;
753
754 if (sis_priv->mii != default_phy) {
755 sis_priv->mii = default_phy;
756 sis_priv->cur_phy = default_phy->phy_addr;
757 printk(KERN_INFO "%s: Using transceiver found at address %d as default\n",
758 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
759 }
760
761 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
762
763 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
764 status &= (~MII_CNTL_ISOLATE);
765
766 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
767 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
768 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
769
770 return status;
771}
772
773
774/**
775 * sis900_set_capability - set the media capability of network adapter.
776 * @net_dev : the net device to probe for
777 * @phy : default PHY
778 *
779 * Set the media capability of network adapter according to
780 * mii status register. It's necessary before auto-negotiate.
781 */
782
783static void sis900_set_capability(struct net_device *net_dev, struct mii_phy *phy)
784{
785 u16 cap;
786 u16 status;
787
788 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
789 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
790
791 cap = MII_NWAY_CSMA_CD |
792 ((phy->status & MII_STAT_CAN_TX_FDX)? MII_NWAY_TX_FDX:0) |
793 ((phy->status & MII_STAT_CAN_TX) ? MII_NWAY_TX:0) |
794 ((phy->status & MII_STAT_CAN_T_FDX) ? MII_NWAY_T_FDX:0)|
795 ((phy->status & MII_STAT_CAN_T) ? MII_NWAY_T:0);
796
797 mdio_write(net_dev, phy->phy_addr, MII_ANADV, cap);
798}
799
800
801/* Delay between EEPROM clock transitions. */
802#define eeprom_delay() inl(ee_addr)
803
804/**
805 * read_eeprom - Read Serial EEPROM
806 * @ioaddr: base i/o address
807 * @location: the EEPROM location to read
808 *
809 * Read Serial EEPROM through EEPROM Access Register.
810 * Note that location is in word (16 bits) unit
811 */
812
813static u16 __devinit read_eeprom(long ioaddr, int location)
814{
815 int i;
816 u16 retval = 0;
817 long ee_addr = ioaddr + mear;
818 u32 read_cmd = location | EEread;
819
820 outl(0, ee_addr);
821 eeprom_delay();
822 outl(EECS, ee_addr);
823 eeprom_delay();
824
825 /* Shift the read command (9) bits out. */
826 for (i = 8; i >= 0; i--) {
827 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
828 outl(dataval, ee_addr);
829 eeprom_delay();
830 outl(dataval | EECLK, ee_addr);
831 eeprom_delay();
832 }
833 outl(EECS, ee_addr);
834 eeprom_delay();
835
836 /* read the 16-bits data in */
837 for (i = 16; i > 0; i--) {
838 outl(EECS, ee_addr);
839 eeprom_delay();
840 outl(EECS | EECLK, ee_addr);
841 eeprom_delay();
842 retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
843 eeprom_delay();
844 }
845
846 /* Terminate the EEPROM access. */
847 outl(0, ee_addr);
848 eeprom_delay();
849
850 return retval;
851}
852
853/* Read and write the MII management registers using software-generated
854 serial MDIO protocol. Note that the command bits and data bits are
855 send out separately */
856#define mdio_delay() inl(mdio_addr)
857
858static void mdio_idle(long mdio_addr)
859{
860 outl(MDIO | MDDIR, mdio_addr);
861 mdio_delay();
862 outl(MDIO | MDDIR | MDC, mdio_addr);
863}
864
865/* Syncronize the MII management interface by shifting 32 one bits out. */
866static void mdio_reset(long mdio_addr)
867{
868 int i;
869
870 for (i = 31; i >= 0; i--) {
871 outl(MDDIR | MDIO, mdio_addr);
872 mdio_delay();
873 outl(MDDIR | MDIO | MDC, mdio_addr);
874 mdio_delay();
875 }
876}
877
878/**
879 * mdio_read - read MII PHY register
880 * @net_dev: the net device to read
881 * @phy_id: the phy address to read
882 * @location: the phy regiester id to read
883 *
884 * Read MII registers through MDIO and MDC
885 * using MDIO management frame structure and protocol(defined by ISO/IEC).
886 * Please see SiS7014 or ICS spec
887 */
888
889static int mdio_read(struct net_device *net_dev, int phy_id, int location)
890{
891 long mdio_addr = net_dev->base_addr + mear;
892 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
893 u16 retval = 0;
894 int i;
895
896 mdio_reset(mdio_addr);
897 mdio_idle(mdio_addr);
898
899 for (i = 15; i >= 0; i--) {
900 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
901 outl(dataval, mdio_addr);
902 mdio_delay();
903 outl(dataval | MDC, mdio_addr);
904 mdio_delay();
905 }
906
907 /* Read the 16 data bits. */
908 for (i = 16; i > 0; i--) {
909 outl(0, mdio_addr);
910 mdio_delay();
911 retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0);
912 outl(MDC, mdio_addr);
913 mdio_delay();
914 }
915 outl(0x00, mdio_addr);
916
917 return retval;
918}
919
920/**
921 * mdio_write - write MII PHY register
922 * @net_dev: the net device to write
923 * @phy_id: the phy address to write
924 * @location: the phy regiester id to write
925 * @value: the register value to write with
926 *
927 * Write MII registers with @value through MDIO and MDC
928 * using MDIO management frame structure and protocol(defined by ISO/IEC)
929 * please see SiS7014 or ICS spec
930 */
931
932static void mdio_write(struct net_device *net_dev, int phy_id, int location,
933 int value)
934{
935 long mdio_addr = net_dev->base_addr + mear;
936 int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
937 int i;
938
939 mdio_reset(mdio_addr);
940 mdio_idle(mdio_addr);
941
942 /* Shift the command bits out. */
943 for (i = 15; i >= 0; i--) {
944 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
945 outb(dataval, mdio_addr);
946 mdio_delay();
947 outb(dataval | MDC, mdio_addr);
948 mdio_delay();
949 }
950 mdio_delay();
951
952 /* Shift the value bits out. */
953 for (i = 15; i >= 0; i--) {
954 int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR;
955 outl(dataval, mdio_addr);
956 mdio_delay();
957 outl(dataval | MDC, mdio_addr);
958 mdio_delay();
959 }
960 mdio_delay();
961
962 /* Clear out extra bits. */
963 for (i = 2; i > 0; i--) {
964 outb(0, mdio_addr);
965 mdio_delay();
966 outb(MDC, mdio_addr);
967 mdio_delay();
968 }
969 outl(0x00, mdio_addr);
970}
971
972
973/**
974 * sis900_reset_phy - reset sis900 mii phy.
975 * @net_dev: the net device to write
976 * @phy_addr: default phy address
977 *
978 * Some specific phy can't work properly without reset.
979 * This function will be called during initialization and
980 * link status change from ON to DOWN.
981 */
982
983static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr)
984{
985 int i;
986 u16 status;
987
988 for (i = 0; i < 2; i++)
989 status = mdio_read(net_dev, phy_addr, MII_STATUS);
990
991 mdio_write( net_dev, phy_addr, MII_CONTROL, MII_CNTL_RESET );
992
993 return status;
994}
995
996#ifdef CONFIG_NET_POLL_CONTROLLER
997/*
998 * Polling 'interrupt' - used by things like netconsole to send skbs
999 * without having to re-enable interrupts. It's not called while
1000 * the interrupt routine is executing.
1001*/
1002static void sis900_poll(struct net_device *dev)
1003{
1004 disable_irq(dev->irq);
1005 sis900_interrupt(dev->irq, dev);
1006 enable_irq(dev->irq);
1007}
1008#endif
1009
1010/**
1011 * sis900_open - open sis900 device
1012 * @net_dev: the net device to open
1013 *
1014 * Do some initialization and start net interface.
1015 * enable interrupts and set sis900 timer.
1016 */
1017
1018static int
1019sis900_open(struct net_device *net_dev)
1020{
1021 struct sis900_private *sis_priv = netdev_priv(net_dev);
1022 long ioaddr = net_dev->base_addr;
1023 int ret;
1024
1025 /* Soft reset the chip. */
1026 sis900_reset(net_dev);
1027
1028 /* Equalizer workaround Rule */
1029 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1030
1031 ret = request_irq(net_dev->irq, sis900_interrupt, IRQF_SHARED,
1032 net_dev->name, net_dev);
1033 if (ret)
1034 return ret;
1035
1036 sis900_init_rxfilter(net_dev);
1037
1038 sis900_init_tx_ring(net_dev);
1039 sis900_init_rx_ring(net_dev);
1040
1041 set_rx_mode(net_dev);
1042
1043 netif_start_queue(net_dev);
1044
1045 /* Workaround for EDB */
1046 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1047
1048 /* Enable all known interrupts by setting the interrupt mask. */
1049 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1050 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
1051 outl(IE, ioaddr + ier);
1052
1053 sis900_check_mode(net_dev, sis_priv->mii);
1054
1055 /* Set the timer to switch to check for link beat and perhaps switch
1056 to an alternate media type. */
1057 init_timer(&sis_priv->timer);
1058 sis_priv->timer.expires = jiffies + HZ;
1059 sis_priv->timer.data = (unsigned long)net_dev;
1060 sis_priv->timer.function = sis900_timer;
1061 add_timer(&sis_priv->timer);
1062
1063 return 0;
1064}
1065
1066/**
1067 * sis900_init_rxfilter - Initialize the Rx filter
1068 * @net_dev: the net device to initialize for
1069 *
1070 * Set receive filter address to our MAC address
1071 * and enable packet filtering.
1072 */
1073
1074static void
1075sis900_init_rxfilter (struct net_device * net_dev)
1076{
1077 struct sis900_private *sis_priv = netdev_priv(net_dev);
1078 long ioaddr = net_dev->base_addr;
1079 u32 rfcrSave;
1080 u32 i;
1081
1082 rfcrSave = inl(rfcr + ioaddr);
1083
1084 /* disable packet filtering before setting filter */
1085 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
1086
1087 /* load MAC addr to filter data register */
1088 for (i = 0 ; i < 3 ; i++) {
1089 u32 w;
1090
1091 w = (u32) *((u16 *)(net_dev->dev_addr)+i);
1092 outl((i << RFADDR_shift), ioaddr + rfcr);
1093 outl(w, ioaddr + rfdr);
1094
1095 if (netif_msg_hw(sis_priv)) {
1096 printk(KERN_DEBUG "%s: Receive Filter Addrss[%d]=%x\n",
1097 net_dev->name, i, inl(ioaddr + rfdr));
1098 }
1099 }
1100
1101 /* enable packet filtering */
1102 outl(rfcrSave | RFEN, rfcr + ioaddr);
1103}
1104
1105/**
1106 * sis900_init_tx_ring - Initialize the Tx descriptor ring
1107 * @net_dev: the net device to initialize for
1108 *
1109 * Initialize the Tx descriptor ring,
1110 */
1111
1112static void
1113sis900_init_tx_ring(struct net_device *net_dev)
1114{
1115 struct sis900_private *sis_priv = netdev_priv(net_dev);
1116 long ioaddr = net_dev->base_addr;
1117 int i;
1118
1119 sis_priv->tx_full = 0;
1120 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1121
1122 for (i = 0; i < NUM_TX_DESC; i++) {
1123 sis_priv->tx_skbuff[i] = NULL;
1124
1125 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1126 ((i+1)%NUM_TX_DESC)*sizeof(BufferDesc);
1127 sis_priv->tx_ring[i].cmdsts = 0;
1128 sis_priv->tx_ring[i].bufptr = 0;
1129 }
1130
1131 /* load Transmit Descriptor Register */
1132 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1133 if (netif_msg_hw(sis_priv))
1134 printk(KERN_DEBUG "%s: TX descriptor register loaded with: %8.8x\n",
1135 net_dev->name, inl(ioaddr + txdp));
1136}
1137
1138/**
1139 * sis900_init_rx_ring - Initialize the Rx descriptor ring
1140 * @net_dev: the net device to initialize for
1141 *
1142 * Initialize the Rx descriptor ring,
1143 * and pre-allocate recevie buffers (socket buffer)
1144 */
1145
1146static void
1147sis900_init_rx_ring(struct net_device *net_dev)
1148{
1149 struct sis900_private *sis_priv = netdev_priv(net_dev);
1150 long ioaddr = net_dev->base_addr;
1151 int i;
1152
1153 sis_priv->cur_rx = 0;
1154 sis_priv->dirty_rx = 0;
1155
1156 /* init RX descriptor */
1157 for (i = 0; i < NUM_RX_DESC; i++) {
1158 sis_priv->rx_skbuff[i] = NULL;
1159
1160 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1161 ((i+1)%NUM_RX_DESC)*sizeof(BufferDesc);
1162 sis_priv->rx_ring[i].cmdsts = 0;
1163 sis_priv->rx_ring[i].bufptr = 0;
1164 }
1165
1166 /* allocate sock buffers */
1167 for (i = 0; i < NUM_RX_DESC; i++) {
1168 struct sk_buff *skb;
1169
1170 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1171 /* not enough memory for skbuff, this makes a "hole"
1172 on the buffer ring, it is not clear how the
1173 hardware will react to this kind of degenerated
1174 buffer */
1175 break;
1176 }
1177 sis_priv->rx_skbuff[i] = skb;
1178 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1179 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
1180 skb->data, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1181 }
1182 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1183
1184 /* load Receive Descriptor Register */
1185 outl(sis_priv->rx_ring_dma, ioaddr + rxdp);
1186 if (netif_msg_hw(sis_priv))
1187 printk(KERN_DEBUG "%s: RX descriptor register loaded with: %8.8x\n",
1188 net_dev->name, inl(ioaddr + rxdp));
1189}
1190
1191/**
1192 * sis630_set_eq - set phy equalizer value for 630 LAN
1193 * @net_dev: the net device to set equalizer value
1194 * @revision: 630 LAN revision number
1195 *
1196 * 630E equalizer workaround rule(Cyrus Huang 08/15)
1197 * PHY register 14h(Test)
1198 * Bit 14: 0 -- Automatically detect (default)
1199 * 1 -- Manually set Equalizer filter
1200 * Bit 13: 0 -- (Default)
1201 * 1 -- Speed up convergence of equalizer setting
1202 * Bit 9 : 0 -- (Default)
1203 * 1 -- Disable Baseline Wander
1204 * Bit 3~7 -- Equalizer filter setting
1205 * Link ON: Set Bit 9, 13 to 1, Bit 14 to 0
1206 * Then calculate equalizer value
1207 * Then set equalizer value, and set Bit 14 to 1, Bit 9 to 0
1208 * Link Off:Set Bit 13 to 1, Bit 14 to 0
1209 * Calculate Equalizer value:
1210 * When Link is ON and Bit 14 is 0, SIS900PHY will auto-detect proper equalizer value.
1211 * When the equalizer is stable, this value is not a fixed value. It will be within
1212 * a small range(eg. 7~9). Then we get a minimum and a maximum value(eg. min=7, max=9)
1213 * 0 <= max <= 4 --> set equalizer to max
1214 * 5 <= max <= 14 --> set equalizer to max+1 or set equalizer to max+2 if max == min
1215 * max >= 15 --> set equalizer to max+5 or set equalizer to max+6 if max == min
1216 */
1217
1218static void sis630_set_eq(struct net_device *net_dev, u8 revision)
1219{
1220 struct sis900_private *sis_priv = netdev_priv(net_dev);
1221 u16 reg14h, eq_value=0, max_value=0, min_value=0;
1222 int i, maxcount=10;
1223
1224 if ( !(revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1225 revision == SIS630A_900_REV || revision == SIS630ET_900_REV) )
1226 return;
1227
1228 if (netif_carrier_ok(net_dev)) {
1229 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1230 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1231 (0x2200 | reg14h) & 0xBFFF);
1232 for (i=0; i < maxcount; i++) {
1233 eq_value = (0x00F8 & mdio_read(net_dev,
1234 sis_priv->cur_phy, MII_RESV)) >> 3;
1235 if (i == 0)
1236 max_value=min_value=eq_value;
1237 max_value = (eq_value > max_value) ?
1238 eq_value : max_value;
1239 min_value = (eq_value < min_value) ?
1240 eq_value : min_value;
1241 }
1242 /* 630E rule to determine the equalizer value */
1243 if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1244 revision == SIS630ET_900_REV) {
1245 if (max_value < 5)
1246 eq_value = max_value;
1247 else if (max_value >= 5 && max_value < 15)
1248 eq_value = (max_value == min_value) ?
1249 max_value+2 : max_value+1;
1250 else if (max_value >= 15)
1251 eq_value=(max_value == min_value) ?
1252 max_value+6 : max_value+5;
1253 }
1254 /* 630B0&B1 rule to determine the equalizer value */
1255 if (revision == SIS630A_900_REV &&
1256 (sis_priv->host_bridge_rev == SIS630B0 ||
1257 sis_priv->host_bridge_rev == SIS630B1)) {
1258 if (max_value == 0)
1259 eq_value = 3;
1260 else
1261 eq_value = (max_value + min_value + 1)/2;
1262 }
1263 /* write equalizer value and setting */
1264 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1265 reg14h = (reg14h & 0xFF07) | ((eq_value << 3) & 0x00F8);
1266 reg14h = (reg14h | 0x6000) & 0xFDFF;
1267 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1268 } else {
1269 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1270 if (revision == SIS630A_900_REV &&
1271 (sis_priv->host_bridge_rev == SIS630B0 ||
1272 sis_priv->host_bridge_rev == SIS630B1))
1273 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1274 (reg14h | 0x2200) & 0xBFFF);
1275 else
1276 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1277 (reg14h | 0x2000) & 0xBFFF);
1278 }
1279}
1280
1281/**
1282 * sis900_timer - sis900 timer routine
1283 * @data: pointer to sis900 net device
1284 *
1285 * On each timer ticks we check two things,
1286 * link status (ON/OFF) and link mode (10/100/Full/Half)
1287 */
1288
1289static void sis900_timer(unsigned long data)
1290{
1291 struct net_device *net_dev = (struct net_device *)data;
1292 struct sis900_private *sis_priv = netdev_priv(net_dev);
1293 struct mii_phy *mii_phy = sis_priv->mii;
1294 static const int next_tick = 5*HZ;
1295 u16 status;
1296
1297 if (!sis_priv->autong_complete){
1298 int uninitialized_var(speed), duplex = 0;
1299
1300 sis900_read_mode(net_dev, &speed, &duplex);
1301 if (duplex){
1302 sis900_set_mode(net_dev->base_addr, speed, duplex);
1303 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1304 netif_start_queue(net_dev);
1305 }
1306
1307 sis_priv->timer.expires = jiffies + HZ;
1308 add_timer(&sis_priv->timer);
1309 return;
1310 }
1311
1312 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1313 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1314
1315 /* Link OFF -> ON */
1316 if (!netif_carrier_ok(net_dev)) {
1317 LookForLink:
1318 /* Search for new PHY */
1319 status = sis900_default_phy(net_dev);
1320 mii_phy = sis_priv->mii;
1321
1322 if (status & MII_STAT_LINK){
1323 sis900_check_mode(net_dev, mii_phy);
1324 netif_carrier_on(net_dev);
1325 }
1326 } else {
1327 /* Link ON -> OFF */
1328 if (!(status & MII_STAT_LINK)){
1329 netif_carrier_off(net_dev);
1330 if(netif_msg_link(sis_priv))
1331 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1332
1333 /* Change mode issue */
1334 if ((mii_phy->phy_id0 == 0x001D) &&
1335 ((mii_phy->phy_id1 & 0xFFF0) == 0x8000))
1336 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1337
1338 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1339
1340 goto LookForLink;
1341 }
1342 }
1343
1344 sis_priv->timer.expires = jiffies + next_tick;
1345 add_timer(&sis_priv->timer);
1346}
1347
1348/**
1349 * sis900_check_mode - check the media mode for sis900
1350 * @net_dev: the net device to be checked
1351 * @mii_phy: the mii phy
1352 *
1353 * Older driver gets the media mode from mii status output
1354 * register. Now we set our media capability and auto-negotiate
1355 * to get the upper bound of speed and duplex between two ends.
1356 * If the types of mii phy is HOME, it doesn't need to auto-negotiate
1357 * and autong_complete should be set to 1.
1358 */
1359
1360static void sis900_check_mode(struct net_device *net_dev, struct mii_phy *mii_phy)
1361{
1362 struct sis900_private *sis_priv = netdev_priv(net_dev);
1363 long ioaddr = net_dev->base_addr;
1364 int speed, duplex;
1365
1366 if (mii_phy->phy_types == LAN) {
1367 outl(~EXD & inl(ioaddr + cfg), ioaddr + cfg);
1368 sis900_set_capability(net_dev , mii_phy);
1369 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1370 } else {
1371 outl(EXD | inl(ioaddr + cfg), ioaddr + cfg);
1372 speed = HW_SPEED_HOME;
1373 duplex = FDX_CAPABLE_HALF_SELECTED;
1374 sis900_set_mode(ioaddr, speed, duplex);
1375 sis_priv->autong_complete = 1;
1376 }
1377}
1378
1379/**
1380 * sis900_set_mode - Set the media mode of mac register.
1381 * @ioaddr: the address of the device
1382 * @speed : the transmit speed to be determined
1383 * @duplex: the duplex mode to be determined
1384 *
1385 * Set the media mode of mac register txcfg/rxcfg according to
1386 * speed and duplex of phy. Bit EDB_MASTER_EN indicates the EDB
1387 * bus is used instead of PCI bus. When this bit is set 1, the
1388 * Max DMA Burst Size for TX/RX DMA should be no larger than 16
1389 * double words.
1390 */
1391
1392static void sis900_set_mode (long ioaddr, int speed, int duplex)
1393{
1394 u32 tx_flags = 0, rx_flags = 0;
1395
1396 if (inl(ioaddr + cfg) & EDB_MASTER_EN) {
1397 tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) |
1398 (TX_FILL_THRESH << TxFILLT_shift);
1399 rx_flags = DMA_BURST_64 << RxMXDMA_shift;
1400 } else {
1401 tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) |
1402 (TX_FILL_THRESH << TxFILLT_shift);
1403 rx_flags = DMA_BURST_512 << RxMXDMA_shift;
1404 }
1405
1406 if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) {
1407 rx_flags |= (RxDRNT_10 << RxDRNT_shift);
1408 tx_flags |= (TxDRNT_10 << TxDRNT_shift);
1409 } else {
1410 rx_flags |= (RxDRNT_100 << RxDRNT_shift);
1411 tx_flags |= (TxDRNT_100 << TxDRNT_shift);
1412 }
1413
1414 if (duplex == FDX_CAPABLE_FULL_SELECTED) {
1415 tx_flags |= (TxCSI | TxHBI);
1416 rx_flags |= RxATX;
1417 }
1418
1419#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1420 /* Can accept Jumbo packet */
1421 rx_flags |= RxAJAB;
1422#endif
1423
1424 outl (tx_flags, ioaddr + txcfg);
1425 outl (rx_flags, ioaddr + rxcfg);
1426}
1427
1428/**
1429 * sis900_auto_negotiate - Set the Auto-Negotiation Enable/Reset bit.
1430 * @net_dev: the net device to read mode for
1431 * @phy_addr: mii phy address
1432 *
1433 * If the adapter is link-on, set the auto-negotiate enable/reset bit.
1434 * autong_complete should be set to 0 when starting auto-negotiation.
1435 * autong_complete should be set to 1 if we didn't start auto-negotiation.
1436 * sis900_timer will wait for link on again if autong_complete = 0.
1437 */
1438
1439static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr)
1440{
1441 struct sis900_private *sis_priv = netdev_priv(net_dev);
1442 int i = 0;
1443 u32 status;
1444
1445 for (i = 0; i < 2; i++)
1446 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1447
1448 if (!(status & MII_STAT_LINK)){
1449 if(netif_msg_link(sis_priv))
1450 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1451 sis_priv->autong_complete = 1;
1452 netif_carrier_off(net_dev);
1453 return;
1454 }
1455
1456 /* (Re)start AutoNegotiate */
1457 mdio_write(net_dev, phy_addr, MII_CONTROL,
1458 MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1459 sis_priv->autong_complete = 0;
1460}
1461
1462
1463/**
1464 * sis900_read_mode - read media mode for sis900 internal phy
1465 * @net_dev: the net device to read mode for
1466 * @speed : the transmit speed to be determined
1467 * @duplex : the duplex mode to be determined
1468 *
1469 * The capability of remote end will be put in mii register autorec
1470 * after auto-negotiation. Use AND operation to get the upper bound
1471 * of speed and duplex between two ends.
1472 */
1473
1474static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex)
1475{
1476 struct sis900_private *sis_priv = netdev_priv(net_dev);
1477 struct mii_phy *phy = sis_priv->mii;
1478 int phy_addr = sis_priv->cur_phy;
1479 u32 status;
1480 u16 autoadv, autorec;
1481 int i;
1482
1483 for (i = 0; i < 2; i++)
1484 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1485
1486 if (!(status & MII_STAT_LINK))
1487 return;
1488
1489 /* AutoNegotiate completed */
1490 autoadv = mdio_read(net_dev, phy_addr, MII_ANADV);
1491 autorec = mdio_read(net_dev, phy_addr, MII_ANLPAR);
1492 status = autoadv & autorec;
1493
1494 *speed = HW_SPEED_10_MBPS;
1495 *duplex = FDX_CAPABLE_HALF_SELECTED;
1496
1497 if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX))
1498 *speed = HW_SPEED_100_MBPS;
1499 if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX))
1500 *duplex = FDX_CAPABLE_FULL_SELECTED;
1501
1502 sis_priv->autong_complete = 1;
1503
1504 /* Workaround for Realtek RTL8201 PHY issue */
1505 if ((phy->phy_id0 == 0x0000) && ((phy->phy_id1 & 0xFFF0) == 0x8200)) {
1506 if (mdio_read(net_dev, phy_addr, MII_CONTROL) & MII_CNTL_FDX)
1507 *duplex = FDX_CAPABLE_FULL_SELECTED;
1508 if (mdio_read(net_dev, phy_addr, 0x0019) & 0x01)
1509 *speed = HW_SPEED_100_MBPS;
1510 }
1511
1512 if(netif_msg_link(sis_priv))
1513 printk(KERN_INFO "%s: Media Link On %s %s-duplex\n",
1514 net_dev->name,
1515 *speed == HW_SPEED_100_MBPS ?
1516 "100mbps" : "10mbps",
1517 *duplex == FDX_CAPABLE_FULL_SELECTED ?
1518 "full" : "half");
1519}
1520
1521/**
1522 * sis900_tx_timeout - sis900 transmit timeout routine
1523 * @net_dev: the net device to transmit
1524 *
1525 * print transmit timeout status
1526 * disable interrupts and do some tasks
1527 */
1528
1529static void sis900_tx_timeout(struct net_device *net_dev)
1530{
1531 struct sis900_private *sis_priv = netdev_priv(net_dev);
1532 long ioaddr = net_dev->base_addr;
1533 unsigned long flags;
1534 int i;
1535
1536 if(netif_msg_tx_err(sis_priv))
1537 printk(KERN_INFO "%s: Transmit timeout, status %8.8x %8.8x\n",
1538 net_dev->name, inl(ioaddr + cr), inl(ioaddr + isr));
1539
1540 /* Disable interrupts by clearing the interrupt mask. */
1541 outl(0x0000, ioaddr + imr);
1542
1543 /* use spinlock to prevent interrupt handler accessing buffer ring */
1544 spin_lock_irqsave(&sis_priv->lock, flags);
1545
1546 /* discard unsent packets */
1547 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1548 for (i = 0; i < NUM_TX_DESC; i++) {
1549 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1550
1551 if (skb) {
1552 pci_unmap_single(sis_priv->pci_dev,
1553 sis_priv->tx_ring[i].bufptr, skb->len,
1554 PCI_DMA_TODEVICE);
1555 dev_kfree_skb_irq(skb);
1556 sis_priv->tx_skbuff[i] = NULL;
1557 sis_priv->tx_ring[i].cmdsts = 0;
1558 sis_priv->tx_ring[i].bufptr = 0;
1559 net_dev->stats.tx_dropped++;
1560 }
1561 }
1562 sis_priv->tx_full = 0;
1563 netif_wake_queue(net_dev);
1564
1565 spin_unlock_irqrestore(&sis_priv->lock, flags);
1566
1567 net_dev->trans_start = jiffies; /* prevent tx timeout */
1568
1569 /* load Transmit Descriptor Register */
1570 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1571
1572 /* Enable all known interrupts by setting the interrupt mask. */
1573 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1574}
1575
1576/**
1577 * sis900_start_xmit - sis900 start transmit routine
1578 * @skb: socket buffer pointer to put the data being transmitted
1579 * @net_dev: the net device to transmit with
1580 *
1581 * Set the transmit buffer descriptor,
1582 * and write TxENA to enable transmit state machine.
1583 * tell upper layer if the buffer is full
1584 */
1585
1586static netdev_tx_t
1587sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
1588{
1589 struct sis900_private *sis_priv = netdev_priv(net_dev);
1590 long ioaddr = net_dev->base_addr;
1591 unsigned int entry;
1592 unsigned long flags;
1593 unsigned int index_cur_tx, index_dirty_tx;
1594 unsigned int count_dirty_tx;
1595
1596 /* Don't transmit data before the complete of auto-negotiation */
1597 if(!sis_priv->autong_complete){
1598 netif_stop_queue(net_dev);
1599 return NETDEV_TX_BUSY;
1600 }
1601
1602 spin_lock_irqsave(&sis_priv->lock, flags);
1603
1604 /* Calculate the next Tx descriptor entry. */
1605 entry = sis_priv->cur_tx % NUM_TX_DESC;
1606 sis_priv->tx_skbuff[entry] = skb;
1607
1608 /* set the transmit buffer descriptor and enable Transmit State Machine */
1609 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1610 skb->data, skb->len, PCI_DMA_TODEVICE);
1611 sis_priv->tx_ring[entry].cmdsts = (OWN | skb->len);
1612 outl(TxENA | inl(ioaddr + cr), ioaddr + cr);
1613
1614 sis_priv->cur_tx ++;
1615 index_cur_tx = sis_priv->cur_tx;
1616 index_dirty_tx = sis_priv->dirty_tx;
1617
1618 for (count_dirty_tx = 0; index_cur_tx != index_dirty_tx; index_dirty_tx++)
1619 count_dirty_tx ++;
1620
1621 if (index_cur_tx == index_dirty_tx) {
1622 /* dirty_tx is met in the cycle of cur_tx, buffer full */
1623 sis_priv->tx_full = 1;
1624 netif_stop_queue(net_dev);
1625 } else if (count_dirty_tx < NUM_TX_DESC) {
1626 /* Typical path, tell upper layer that more transmission is possible */
1627 netif_start_queue(net_dev);
1628 } else {
1629 /* buffer full, tell upper layer no more transmission */
1630 sis_priv->tx_full = 1;
1631 netif_stop_queue(net_dev);
1632 }
1633
1634 spin_unlock_irqrestore(&sis_priv->lock, flags);
1635
1636 if (netif_msg_tx_queued(sis_priv))
1637 printk(KERN_DEBUG "%s: Queued Tx packet at %p size %d "
1638 "to slot %d.\n",
1639 net_dev->name, skb->data, (int)skb->len, entry);
1640
1641 return NETDEV_TX_OK;
1642}
1643
1644/**
1645 * sis900_interrupt - sis900 interrupt handler
1646 * @irq: the irq number
1647 * @dev_instance: the client data object
1648 *
1649 * The interrupt handler does all of the Rx thread work,
1650 * and cleans up after the Tx thread
1651 */
1652
1653static irqreturn_t sis900_i…Large files files are truncated, but you can click here to view the full file