/drivers/net/wireless/bcm4329/include/sbpcmcia.h

https://bitbucket.org/wisechild/galaxy-nexus · C++ Header · 109 lines · 53 code · 31 blank · 25 comment · 0 complexity · 7a568bd76beab0b7766f08c5113b11c9 MD5 · raw file

  1. /*
  2. * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
  3. *
  4. * Copyright (C) 1999-2010, Broadcom Corporation
  5. *
  6. * Unless you and Broadcom execute a separate written software license
  7. * agreement governing use of this software, this software is licensed to you
  8. * under the terms of the GNU General Public License version 2 (the "GPL"),
  9. * available at http://www.broadcom.com/licenses/GPLv2.php, with the
  10. * following added to such license:
  11. *
  12. * As a special exception, the copyright holders of this software give you
  13. * permission to link this software with independent modules, and to copy and
  14. * distribute the resulting executable under terms of your choice, provided that
  15. * you also meet, for each linked independent module, the terms and conditions of
  16. * the license of that module. An independent module is a module which is not
  17. * derived from this software. The special exception does not apply to any
  18. * modifications of the software.
  19. *
  20. * Notwithstanding the above, under no circumstances may you combine this
  21. * software in any way with any other Broadcom software provided under a license
  22. * other than the GPL, without Broadcom's express prior written consent.
  23. *
  24. * $Id: sbpcmcia.h,v 13.31.4.1.2.3.8.7 2009/06/22 05:14:24 Exp $
  25. */
  26. #ifndef _SBPCMCIA_H
  27. #define _SBPCMCIA_H
  28. #define PCMCIA_FCR (0x700 / 2)
  29. #define FCR0_OFF 0
  30. #define FCR1_OFF (0x40 / 2)
  31. #define FCR2_OFF (0x80 / 2)
  32. #define FCR3_OFF (0xc0 / 2)
  33. #define PCMCIA_FCR0 (0x700 / 2)
  34. #define PCMCIA_FCR1 (0x740 / 2)
  35. #define PCMCIA_FCR2 (0x780 / 2)
  36. #define PCMCIA_FCR3 (0x7c0 / 2)
  37. #define PCMCIA_COR 0
  38. #define COR_RST 0x80
  39. #define COR_LEV 0x40
  40. #define COR_IRQEN 0x04
  41. #define COR_BLREN 0x01
  42. #define COR_FUNEN 0x01
  43. #define PCICIA_FCSR (2 / 2)
  44. #define PCICIA_PRR (4 / 2)
  45. #define PCICIA_SCR (6 / 2)
  46. #define PCICIA_ESR (8 / 2)
  47. #define PCM_MEMOFF 0x0000
  48. #define F0_MEMOFF 0x1000
  49. #define F1_MEMOFF 0x2000
  50. #define F2_MEMOFF 0x3000
  51. #define F3_MEMOFF 0x4000
  52. #define MEM_ADDR0 (0x728 / 2)
  53. #define MEM_ADDR1 (0x72a / 2)
  54. #define MEM_ADDR2 (0x72c / 2)
  55. #define PCMCIA_ADDR0 (0x072e / 2)
  56. #define PCMCIA_ADDR1 (0x0730 / 2)
  57. #define PCMCIA_ADDR2 (0x0732 / 2)
  58. #define MEM_SEG (0x0734 / 2)
  59. #define SROM_CS (0x0736 / 2)
  60. #define SROM_DATAL (0x0738 / 2)
  61. #define SROM_DATAH (0x073a / 2)
  62. #define SROM_ADDRL (0x073c / 2)
  63. #define SROM_ADDRH (0x073e / 2)
  64. #define SROM_INFO2 (0x0772 / 2)
  65. #define SROM_INFO (0x07be / 2)
  66. #define SROM_IDLE 0
  67. #define SROM_WRITE 1
  68. #define SROM_READ 2
  69. #define SROM_WEN 4
  70. #define SROM_WDS 7
  71. #define SROM_DONE 8
  72. #define SRI_SZ_MASK 0x03
  73. #define SRI_BLANK 0x04
  74. #define SRI_OTP 0x80
  75. #define SBTML_INT_ACK 0x40000
  76. #define SBTML_INT_EN 0x20000
  77. #define SBTMH_INT_STATUS 0x40000
  78. #endif