/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
C | 714 lines | 514 code | 112 blank | 88 comment | 52 complexity | d192872da222dd2ea3238e2db7dc1c61 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-helpers.h"
39#include "iwl-agn-hw.h"
40#include "iwl-agn.h"
41#include "iwl-agn-calib.h"
42
43#define IWL_AC_UNSET -1
44
45struct queue_to_fifo_ac {
46 s8 fifo, ac;
47};
48
49static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
50 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
51 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
52 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
53 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
54 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
55 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
56 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
57 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
58 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
59 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
60};
61
62static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
63 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
64 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
65 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
66 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
67 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
68 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
69 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
70 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
71 { IWL_TX_FIFO_BE_IPAN, 2, },
72 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
73};
74
75static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
76 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
77 0, COEX_UNASSOC_IDLE_FLAGS},
78 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
79 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
80 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
81 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
82 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
83 0, COEX_CALIBRATION_FLAGS},
84 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
85 0, COEX_PERIODIC_CALIBRATION_FLAGS},
86 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
87 0, COEX_CONNECTION_ESTAB_FLAGS},
88 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
89 0, COEX_ASSOCIATED_IDLE_FLAGS},
90 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
91 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
92 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
93 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
94 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
95 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
96 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
97 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
98 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
99 0, COEX_STAND_ALONE_DEBUG_FLAGS},
100 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
101 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
102 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
103 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
104};
105
106/*
107 * ucode
108 */
109static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
110 struct fw_desc *image, u32 dst_addr)
111{
112 dma_addr_t phy_addr = image->p_addr;
113 u32 byte_cnt = image->len;
114 int ret;
115
116 priv->ucode_write_complete = 0;
117
118 iwl_write_direct32(priv,
119 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
120 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
121
122 iwl_write_direct32(priv,
123 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
124
125 iwl_write_direct32(priv,
126 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
127 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
128
129 iwl_write_direct32(priv,
130 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
131 (iwl_get_dma_hi_addr(phy_addr)
132 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
133
134 iwl_write_direct32(priv,
135 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
136 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
137 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
138 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
139
140 iwl_write_direct32(priv,
141 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
142 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
143 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
144 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
145
146 IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
147 ret = wait_event_timeout(priv->wait_command_queue,
148 priv->ucode_write_complete, 5 * HZ);
149 if (!ret) {
150 IWL_ERR(priv, "Could not load the %s uCode section\n",
151 name);
152 return -ETIMEDOUT;
153 }
154
155 return 0;
156}
157
158static int iwlagn_load_given_ucode(struct iwl_priv *priv,
159 struct fw_img *image)
160{
161 int ret = 0;
162
163 ret = iwlagn_load_section(priv, "INST", &image->code,
164 IWLAGN_RTC_INST_LOWER_BOUND);
165 if (ret)
166 return ret;
167
168 return iwlagn_load_section(priv, "DATA", &image->data,
169 IWLAGN_RTC_DATA_LOWER_BOUND);
170}
171
172/*
173 * Calibration
174 */
175static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
176{
177 struct iwl_calib_xtal_freq_cmd cmd;
178 __le16 *xtal_calib =
179 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
180
181 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
182 cmd.hdr.first_group = 0;
183 cmd.hdr.groups_num = 1;
184 cmd.hdr.data_valid = 1;
185 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
186 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
187 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
188 (u8 *)&cmd, sizeof(cmd));
189}
190
191static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
192{
193 struct iwl_calib_temperature_offset_cmd cmd;
194 __le16 *offset_calib =
195 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_TEMPERATURE);
196 cmd.hdr.op_code = IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD;
197 cmd.hdr.first_group = 0;
198 cmd.hdr.groups_num = 1;
199 cmd.hdr.data_valid = 1;
200 cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
201 if (!(cmd.radio_sensor_offset))
202 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
203 cmd.reserved = 0;
204 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
205 cmd.radio_sensor_offset);
206 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
207 (u8 *)&cmd, sizeof(cmd));
208}
209
210static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
211{
212 struct iwl_calib_cfg_cmd calib_cfg_cmd;
213 struct iwl_host_cmd cmd = {
214 .id = CALIBRATION_CFG_CMD,
215 .len = { sizeof(struct iwl_calib_cfg_cmd), },
216 .data = { &calib_cfg_cmd, },
217 };
218
219 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
220 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
221 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
222 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
223 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
224
225 return iwl_send_cmd(priv, &cmd);
226}
227
228void iwlagn_rx_calib_result(struct iwl_priv *priv,
229 struct iwl_rx_mem_buffer *rxb)
230{
231 struct iwl_rx_packet *pkt = rxb_addr(rxb);
232 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
233 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
234 int index;
235
236 /* reduce the size of the length field itself */
237 len -= 4;
238
239 /* Define the order in which the results will be sent to the runtime
240 * uCode. iwl_send_calib_results sends them in a row according to
241 * their index. We sort them here
242 */
243 switch (hdr->op_code) {
244 case IWL_PHY_CALIBRATE_DC_CMD:
245 index = IWL_CALIB_DC;
246 break;
247 case IWL_PHY_CALIBRATE_LO_CMD:
248 index = IWL_CALIB_LO;
249 break;
250 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
251 index = IWL_CALIB_TX_IQ;
252 break;
253 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
254 index = IWL_CALIB_TX_IQ_PERD;
255 break;
256 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
257 index = IWL_CALIB_BASE_BAND;
258 break;
259 default:
260 IWL_ERR(priv, "Unknown calibration notification %d\n",
261 hdr->op_code);
262 return;
263 }
264 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
265}
266
267int iwlagn_init_alive_start(struct iwl_priv *priv)
268{
269 int ret;
270
271 if (priv->cfg->bt_params &&
272 priv->cfg->bt_params->advanced_bt_coexist) {
273 /*
274 * Tell uCode we are ready to perform calibration
275 * need to perform this before any calibration
276 * no need to close the envlope since we are going
277 * to load the runtime uCode later.
278 */
279 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
280 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
281 if (ret)
282 return ret;
283
284 }
285
286 ret = iwlagn_send_calib_cfg(priv);
287 if (ret)
288 return ret;
289
290 /**
291 * temperature offset calibration is only needed for runtime ucode,
292 * so prepare the value now.
293 */
294 if (priv->cfg->need_temp_offset_calib)
295 return iwlagn_set_temperature_offset_calib(priv);
296
297 return 0;
298}
299
300static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
301{
302 struct iwl_wimax_coex_cmd coex_cmd;
303
304 if (priv->cfg->base_params->support_wimax_coexist) {
305 /* UnMask wake up src at associated sleep */
306 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
307
308 /* UnMask wake up src at unassociated sleep */
309 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
310 memcpy(coex_cmd.sta_prio, cu_priorities,
311 sizeof(struct iwl_wimax_coex_event_entry) *
312 COEX_NUM_OF_EVENTS);
313
314 /* enabling the coexistence feature */
315 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
316
317 /* enabling the priorities tables */
318 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
319 } else {
320 /* coexistence is disabled */
321 memset(&coex_cmd, 0, sizeof(coex_cmd));
322 }
323 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
324 sizeof(coex_cmd), &coex_cmd);
325}
326
327static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
328 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
329 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
330 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
331 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
332 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
333 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
334 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
335 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
336 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
337 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
338 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
339 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
340 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
341 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
342 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
343 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
344 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
345 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
346 0, 0, 0, 0, 0, 0, 0
347};
348
349void iwlagn_send_prio_tbl(struct iwl_priv *priv)
350{
351 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
352
353 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
354 sizeof(iwlagn_bt_prio_tbl));
355 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
356 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
357 IWL_ERR(priv, "failed to send BT prio tbl command\n");
358}
359
360int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
361{
362 struct iwl_bt_coex_prot_env_cmd env_cmd;
363 int ret;
364
365 env_cmd.action = action;
366 env_cmd.type = type;
367 ret = iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
368 sizeof(env_cmd), &env_cmd);
369 if (ret)
370 IWL_ERR(priv, "failed to send BT env command\n");
371 return ret;
372}
373
374
375static int iwlagn_alive_notify(struct iwl_priv *priv)
376{
377 const struct queue_to_fifo_ac *queue_to_fifo;
378 struct iwl_rxon_context *ctx;
379 u32 a;
380 unsigned long flags;
381 int i, chan;
382 u32 reg_val;
383 int ret;
384
385 spin_lock_irqsave(&priv->lock, flags);
386
387 priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
388 a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
389 for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
390 a += 4)
391 iwl_write_targ_mem(priv, a, 0);
392 for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
393 a += 4)
394 iwl_write_targ_mem(priv, a, 0);
395 for (; a < priv->scd_base_addr +
396 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
397 iwl_write_targ_mem(priv, a, 0);
398
399 iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
400 priv->scd_bc_tbls.dma >> 10);
401
402 /* Enable DMA channel */
403 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
404 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
405 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
406 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
407
408 /* Update FH chicken bits */
409 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
410 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
411 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
412
413 iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
414 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
415 iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
416
417 /* initiate the queues */
418 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
419 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
420 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
421 iwl_write_targ_mem(priv, priv->scd_base_addr +
422 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
423 iwl_write_targ_mem(priv, priv->scd_base_addr +
424 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
425 sizeof(u32),
426 ((SCD_WIN_SIZE <<
427 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
428 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
429 ((SCD_FRAME_LIMIT <<
430 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
431 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
432 }
433
434 iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
435 IWL_MASK(0, priv->hw_params.max_txq_num));
436
437 /* Activate all Tx DMA/FIFO channels */
438 iwlagn_txq_set_sched(priv, IWL_MASK(0, 7));
439
440 /* map queues to FIFOs */
441 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
442 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
443 else
444 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
445
446 iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
447
448 /* make sure all queue are not stopped */
449 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
450 for (i = 0; i < 4; i++)
451 atomic_set(&priv->queue_stop_count[i], 0);
452 for_each_context(priv, ctx)
453 ctx->last_tx_rejected = false;
454
455 /* reset to 0 to enable all the queue first */
456 priv->txq_ctx_active_msk = 0;
457
458 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
459 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
460
461 for (i = 0; i < 10; i++) {
462 int fifo = queue_to_fifo[i].fifo;
463 int ac = queue_to_fifo[i].ac;
464
465 iwl_txq_ctx_activate(priv, i);
466
467 if (fifo == IWL_TX_FIFO_UNUSED)
468 continue;
469
470 if (ac != IWL_AC_UNSET)
471 iwl_set_swq_id(&priv->txq[i], ac, i);
472 iwlagn_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
473 }
474
475 spin_unlock_irqrestore(&priv->lock, flags);
476
477 /* Enable L1-Active */
478 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
479 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
480
481 ret = iwlagn_send_wimax_coex(priv);
482 if (ret)
483 return ret;
484
485 ret = iwlagn_set_Xtal_calib(priv);
486 if (ret)
487 return ret;
488
489 return iwl_send_calib_results(priv);
490}
491
492
493/**
494 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
495 * using sample data 100 bytes apart. If these sample points are good,
496 * it's a pretty good bet that everything between them is good, too.
497 */
498static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
499 struct fw_desc *fw_desc)
500{
501 __le32 *image = (__le32 *)fw_desc->v_addr;
502 u32 len = fw_desc->len;
503 u32 val;
504 u32 i;
505
506 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
507
508 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
509 /* read data comes through single port, auto-incr addr */
510 /* NOTE: Use the debugless read so we don't flood kernel log
511 * if IWL_DL_IO is set */
512 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
513 i + IWLAGN_RTC_INST_LOWER_BOUND);
514 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
515 if (val != le32_to_cpu(*image))
516 return -EIO;
517 }
518
519 return 0;
520}
521
522static void iwl_print_mismatch_inst(struct iwl_priv *priv,
523 struct fw_desc *fw_desc)
524{
525 __le32 *image = (__le32 *)fw_desc->v_addr;
526 u32 len = fw_desc->len;
527 u32 val;
528 u32 offs;
529 int errors = 0;
530
531 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
532
533 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
534 IWLAGN_RTC_INST_LOWER_BOUND);
535
536 for (offs = 0;
537 offs < len && errors < 20;
538 offs += sizeof(u32), image++) {
539 /* read data comes through single port, auto-incr addr */
540 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
541 if (val != le32_to_cpu(*image)) {
542 IWL_ERR(priv, "uCode INST section at "
543 "offset 0x%x, is 0x%x, s/b 0x%x\n",
544 offs, val, le32_to_cpu(*image));
545 errors++;
546 }
547 }
548}
549
550/**
551 * iwl_verify_ucode - determine which instruction image is in SRAM,
552 * and verify its contents
553 */
554static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
555{
556 if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
557 IWL_DEBUG_INFO(priv, "uCode is good in inst SRAM\n");
558 return 0;
559 }
560
561 IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
562
563 iwl_print_mismatch_inst(priv, &img->code);
564 return -EIO;
565}
566
567struct iwlagn_alive_data {
568 bool valid;
569 u8 subtype;
570};
571
572static void iwlagn_alive_fn(struct iwl_priv *priv,
573 struct iwl_rx_packet *pkt,
574 void *data)
575{
576 struct iwlagn_alive_data *alive_data = data;
577 struct iwl_alive_resp *palive;
578
579 palive = &pkt->u.alive_frame;
580
581 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
582 "0x%01X 0x%01X\n",
583 palive->is_valid, palive->ver_type,
584 palive->ver_subtype);
585
586 priv->device_pointers.error_event_table =
587 le32_to_cpu(palive->error_event_table_ptr);
588 priv->device_pointers.log_event_table =
589 le32_to_cpu(palive->log_event_table_ptr);
590
591 alive_data->subtype = palive->ver_subtype;
592 alive_data->valid = palive->is_valid == UCODE_VALID_OK;
593}
594
595#define UCODE_ALIVE_TIMEOUT HZ
596#define UCODE_CALIB_TIMEOUT (2*HZ)
597
598int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
599 struct fw_img *image,
600 int subtype, int alternate_subtype)
601{
602 struct iwl_notification_wait alive_wait;
603 struct iwlagn_alive_data alive_data;
604 int ret;
605 enum iwlagn_ucode_subtype old_type;
606
607 ret = iwlagn_start_device(priv);
608 if (ret)
609 return ret;
610
611 iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
612 iwlagn_alive_fn, &alive_data);
613
614 old_type = priv->ucode_type;
615 priv->ucode_type = subtype;
616
617 ret = iwlagn_load_given_ucode(priv, image);
618 if (ret) {
619 priv->ucode_type = old_type;
620 iwlagn_remove_notification(priv, &alive_wait);
621 return ret;
622 }
623
624 /* Remove all resets to allow NIC to operate */
625 iwl_write32(priv, CSR_RESET, 0);
626
627 /*
628 * Some things may run in the background now, but we
629 * just wait for the ALIVE notification here.
630 */
631 ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
632 if (ret) {
633 priv->ucode_type = old_type;
634 return ret;
635 }
636
637 if (!alive_data.valid) {
638 IWL_ERR(priv, "Loaded ucode is not valid!\n");
639 priv->ucode_type = old_type;
640 return -EIO;
641 }
642
643 if (alive_data.subtype != subtype &&
644 alive_data.subtype != alternate_subtype) {
645 IWL_ERR(priv,
646 "Loaded ucode is not expected type (got %d, expected %d)!\n",
647 alive_data.subtype, subtype);
648 priv->ucode_type = old_type;
649 return -EIO;
650 }
651
652 ret = iwl_verify_ucode(priv, image);
653 if (ret) {
654 priv->ucode_type = old_type;
655 return ret;
656 }
657
658 /* delay a bit to give rfkill time to run */
659 msleep(5);
660
661 ret = iwlagn_alive_notify(priv);
662 if (ret) {
663 IWL_WARN(priv,
664 "Could not complete ALIVE transition: %d\n", ret);
665 priv->ucode_type = old_type;
666 return ret;
667 }
668
669 return 0;
670}
671
672int iwlagn_run_init_ucode(struct iwl_priv *priv)
673{
674 struct iwl_notification_wait calib_wait;
675 int ret;
676
677 lockdep_assert_held(&priv->mutex);
678
679 /* No init ucode required? Curious, but maybe ok */
680 if (!priv->ucode_init.code.len)
681 return 0;
682
683 if (priv->ucode_type != UCODE_SUBTYPE_NONE_LOADED)
684 return 0;
685
686 iwlagn_init_notification_wait(priv, &calib_wait,
687 CALIBRATION_COMPLETE_NOTIFICATION,
688 NULL, NULL);
689
690 /* Will also start the device */
691 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
692 UCODE_SUBTYPE_INIT, -1);
693 if (ret)
694 goto error;
695
696 ret = iwlagn_init_alive_start(priv);
697 if (ret)
698 goto error;
699
700 /*
701 * Some things may run in the background now, but we
702 * just wait for the calibration complete notification.
703 */
704 ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
705
706 goto out;
707
708 error:
709 iwlagn_remove_notification(priv, &calib_wait);
710 out:
711 /* Whatever happened, stop the device */
712 iwlagn_stop_device(priv);
713 return ret;
714}