/drivers/gpu/drm/nouveau/nouveau_state.c

https://bitbucket.org/wisechild/galaxy-nexus · C · 1140 lines · 974 code · 108 blank · 58 comment · 99 complexity · 2954adb33297fa9c51c9c2156b30974f MD5 · raw file

  1. /*
  2. * Copyright 2005 Stephane Marchesin
  3. * Copyright 2008 Stuart Bennett
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. */
  25. #include <linux/swab.h>
  26. #include <linux/slab.h>
  27. #include "drmP.h"
  28. #include "drm.h"
  29. #include "drm_sarea.h"
  30. #include "drm_crtc_helper.h"
  31. #include <linux/vgaarb.h>
  32. #include <linux/vga_switcheroo.h>
  33. #include "nouveau_drv.h"
  34. #include "nouveau_drm.h"
  35. #include "nouveau_fbcon.h"
  36. #include "nouveau_ramht.h"
  37. #include "nouveau_pm.h"
  38. #include "nv50_display.h"
  39. static void nouveau_stub_takedown(struct drm_device *dev) {}
  40. static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  41. static int nouveau_init_engine_ptrs(struct drm_device *dev)
  42. {
  43. struct drm_nouveau_private *dev_priv = dev->dev_private;
  44. struct nouveau_engine *engine = &dev_priv->engine;
  45. switch (dev_priv->chipset & 0xf0) {
  46. case 0x00:
  47. engine->instmem.init = nv04_instmem_init;
  48. engine->instmem.takedown = nv04_instmem_takedown;
  49. engine->instmem.suspend = nv04_instmem_suspend;
  50. engine->instmem.resume = nv04_instmem_resume;
  51. engine->instmem.get = nv04_instmem_get;
  52. engine->instmem.put = nv04_instmem_put;
  53. engine->instmem.map = nv04_instmem_map;
  54. engine->instmem.unmap = nv04_instmem_unmap;
  55. engine->instmem.flush = nv04_instmem_flush;
  56. engine->mc.init = nv04_mc_init;
  57. engine->mc.takedown = nv04_mc_takedown;
  58. engine->timer.init = nv04_timer_init;
  59. engine->timer.read = nv04_timer_read;
  60. engine->timer.takedown = nv04_timer_takedown;
  61. engine->fb.init = nv04_fb_init;
  62. engine->fb.takedown = nv04_fb_takedown;
  63. engine->fifo.channels = 16;
  64. engine->fifo.init = nv04_fifo_init;
  65. engine->fifo.takedown = nv04_fifo_fini;
  66. engine->fifo.disable = nv04_fifo_disable;
  67. engine->fifo.enable = nv04_fifo_enable;
  68. engine->fifo.reassign = nv04_fifo_reassign;
  69. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  70. engine->fifo.channel_id = nv04_fifo_channel_id;
  71. engine->fifo.create_context = nv04_fifo_create_context;
  72. engine->fifo.destroy_context = nv04_fifo_destroy_context;
  73. engine->fifo.load_context = nv04_fifo_load_context;
  74. engine->fifo.unload_context = nv04_fifo_unload_context;
  75. engine->display.early_init = nv04_display_early_init;
  76. engine->display.late_takedown = nv04_display_late_takedown;
  77. engine->display.create = nv04_display_create;
  78. engine->display.init = nv04_display_init;
  79. engine->display.destroy = nv04_display_destroy;
  80. engine->gpio.init = nouveau_stub_init;
  81. engine->gpio.takedown = nouveau_stub_takedown;
  82. engine->gpio.get = NULL;
  83. engine->gpio.set = NULL;
  84. engine->gpio.irq_enable = NULL;
  85. engine->pm.clock_get = nv04_pm_clock_get;
  86. engine->pm.clock_pre = nv04_pm_clock_pre;
  87. engine->pm.clock_set = nv04_pm_clock_set;
  88. engine->vram.init = nouveau_mem_detect;
  89. engine->vram.flags_valid = nouveau_mem_flags_valid;
  90. break;
  91. case 0x10:
  92. engine->instmem.init = nv04_instmem_init;
  93. engine->instmem.takedown = nv04_instmem_takedown;
  94. engine->instmem.suspend = nv04_instmem_suspend;
  95. engine->instmem.resume = nv04_instmem_resume;
  96. engine->instmem.get = nv04_instmem_get;
  97. engine->instmem.put = nv04_instmem_put;
  98. engine->instmem.map = nv04_instmem_map;
  99. engine->instmem.unmap = nv04_instmem_unmap;
  100. engine->instmem.flush = nv04_instmem_flush;
  101. engine->mc.init = nv04_mc_init;
  102. engine->mc.takedown = nv04_mc_takedown;
  103. engine->timer.init = nv04_timer_init;
  104. engine->timer.read = nv04_timer_read;
  105. engine->timer.takedown = nv04_timer_takedown;
  106. engine->fb.init = nv10_fb_init;
  107. engine->fb.takedown = nv10_fb_takedown;
  108. engine->fb.init_tile_region = nv10_fb_init_tile_region;
  109. engine->fb.set_tile_region = nv10_fb_set_tile_region;
  110. engine->fb.free_tile_region = nv10_fb_free_tile_region;
  111. engine->fifo.channels = 32;
  112. engine->fifo.init = nv10_fifo_init;
  113. engine->fifo.takedown = nv04_fifo_fini;
  114. engine->fifo.disable = nv04_fifo_disable;
  115. engine->fifo.enable = nv04_fifo_enable;
  116. engine->fifo.reassign = nv04_fifo_reassign;
  117. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  118. engine->fifo.channel_id = nv10_fifo_channel_id;
  119. engine->fifo.create_context = nv10_fifo_create_context;
  120. engine->fifo.destroy_context = nv04_fifo_destroy_context;
  121. engine->fifo.load_context = nv10_fifo_load_context;
  122. engine->fifo.unload_context = nv10_fifo_unload_context;
  123. engine->display.early_init = nv04_display_early_init;
  124. engine->display.late_takedown = nv04_display_late_takedown;
  125. engine->display.create = nv04_display_create;
  126. engine->display.init = nv04_display_init;
  127. engine->display.destroy = nv04_display_destroy;
  128. engine->gpio.init = nouveau_stub_init;
  129. engine->gpio.takedown = nouveau_stub_takedown;
  130. engine->gpio.get = nv10_gpio_get;
  131. engine->gpio.set = nv10_gpio_set;
  132. engine->gpio.irq_enable = NULL;
  133. engine->pm.clock_get = nv04_pm_clock_get;
  134. engine->pm.clock_pre = nv04_pm_clock_pre;
  135. engine->pm.clock_set = nv04_pm_clock_set;
  136. engine->vram.init = nouveau_mem_detect;
  137. engine->vram.flags_valid = nouveau_mem_flags_valid;
  138. break;
  139. case 0x20:
  140. engine->instmem.init = nv04_instmem_init;
  141. engine->instmem.takedown = nv04_instmem_takedown;
  142. engine->instmem.suspend = nv04_instmem_suspend;
  143. engine->instmem.resume = nv04_instmem_resume;
  144. engine->instmem.get = nv04_instmem_get;
  145. engine->instmem.put = nv04_instmem_put;
  146. engine->instmem.map = nv04_instmem_map;
  147. engine->instmem.unmap = nv04_instmem_unmap;
  148. engine->instmem.flush = nv04_instmem_flush;
  149. engine->mc.init = nv04_mc_init;
  150. engine->mc.takedown = nv04_mc_takedown;
  151. engine->timer.init = nv04_timer_init;
  152. engine->timer.read = nv04_timer_read;
  153. engine->timer.takedown = nv04_timer_takedown;
  154. engine->fb.init = nv10_fb_init;
  155. engine->fb.takedown = nv10_fb_takedown;
  156. engine->fb.init_tile_region = nv10_fb_init_tile_region;
  157. engine->fb.set_tile_region = nv10_fb_set_tile_region;
  158. engine->fb.free_tile_region = nv10_fb_free_tile_region;
  159. engine->fifo.channels = 32;
  160. engine->fifo.init = nv10_fifo_init;
  161. engine->fifo.takedown = nv04_fifo_fini;
  162. engine->fifo.disable = nv04_fifo_disable;
  163. engine->fifo.enable = nv04_fifo_enable;
  164. engine->fifo.reassign = nv04_fifo_reassign;
  165. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  166. engine->fifo.channel_id = nv10_fifo_channel_id;
  167. engine->fifo.create_context = nv10_fifo_create_context;
  168. engine->fifo.destroy_context = nv04_fifo_destroy_context;
  169. engine->fifo.load_context = nv10_fifo_load_context;
  170. engine->fifo.unload_context = nv10_fifo_unload_context;
  171. engine->display.early_init = nv04_display_early_init;
  172. engine->display.late_takedown = nv04_display_late_takedown;
  173. engine->display.create = nv04_display_create;
  174. engine->display.init = nv04_display_init;
  175. engine->display.destroy = nv04_display_destroy;
  176. engine->gpio.init = nouveau_stub_init;
  177. engine->gpio.takedown = nouveau_stub_takedown;
  178. engine->gpio.get = nv10_gpio_get;
  179. engine->gpio.set = nv10_gpio_set;
  180. engine->gpio.irq_enable = NULL;
  181. engine->pm.clock_get = nv04_pm_clock_get;
  182. engine->pm.clock_pre = nv04_pm_clock_pre;
  183. engine->pm.clock_set = nv04_pm_clock_set;
  184. engine->vram.init = nouveau_mem_detect;
  185. engine->vram.flags_valid = nouveau_mem_flags_valid;
  186. break;
  187. case 0x30:
  188. engine->instmem.init = nv04_instmem_init;
  189. engine->instmem.takedown = nv04_instmem_takedown;
  190. engine->instmem.suspend = nv04_instmem_suspend;
  191. engine->instmem.resume = nv04_instmem_resume;
  192. engine->instmem.get = nv04_instmem_get;
  193. engine->instmem.put = nv04_instmem_put;
  194. engine->instmem.map = nv04_instmem_map;
  195. engine->instmem.unmap = nv04_instmem_unmap;
  196. engine->instmem.flush = nv04_instmem_flush;
  197. engine->mc.init = nv04_mc_init;
  198. engine->mc.takedown = nv04_mc_takedown;
  199. engine->timer.init = nv04_timer_init;
  200. engine->timer.read = nv04_timer_read;
  201. engine->timer.takedown = nv04_timer_takedown;
  202. engine->fb.init = nv30_fb_init;
  203. engine->fb.takedown = nv30_fb_takedown;
  204. engine->fb.init_tile_region = nv30_fb_init_tile_region;
  205. engine->fb.set_tile_region = nv10_fb_set_tile_region;
  206. engine->fb.free_tile_region = nv30_fb_free_tile_region;
  207. engine->fifo.channels = 32;
  208. engine->fifo.init = nv10_fifo_init;
  209. engine->fifo.takedown = nv04_fifo_fini;
  210. engine->fifo.disable = nv04_fifo_disable;
  211. engine->fifo.enable = nv04_fifo_enable;
  212. engine->fifo.reassign = nv04_fifo_reassign;
  213. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  214. engine->fifo.channel_id = nv10_fifo_channel_id;
  215. engine->fifo.create_context = nv10_fifo_create_context;
  216. engine->fifo.destroy_context = nv04_fifo_destroy_context;
  217. engine->fifo.load_context = nv10_fifo_load_context;
  218. engine->fifo.unload_context = nv10_fifo_unload_context;
  219. engine->display.early_init = nv04_display_early_init;
  220. engine->display.late_takedown = nv04_display_late_takedown;
  221. engine->display.create = nv04_display_create;
  222. engine->display.init = nv04_display_init;
  223. engine->display.destroy = nv04_display_destroy;
  224. engine->gpio.init = nouveau_stub_init;
  225. engine->gpio.takedown = nouveau_stub_takedown;
  226. engine->gpio.get = nv10_gpio_get;
  227. engine->gpio.set = nv10_gpio_set;
  228. engine->gpio.irq_enable = NULL;
  229. engine->pm.clock_get = nv04_pm_clock_get;
  230. engine->pm.clock_pre = nv04_pm_clock_pre;
  231. engine->pm.clock_set = nv04_pm_clock_set;
  232. engine->pm.voltage_get = nouveau_voltage_gpio_get;
  233. engine->pm.voltage_set = nouveau_voltage_gpio_set;
  234. engine->vram.init = nouveau_mem_detect;
  235. engine->vram.flags_valid = nouveau_mem_flags_valid;
  236. break;
  237. case 0x40:
  238. case 0x60:
  239. engine->instmem.init = nv04_instmem_init;
  240. engine->instmem.takedown = nv04_instmem_takedown;
  241. engine->instmem.suspend = nv04_instmem_suspend;
  242. engine->instmem.resume = nv04_instmem_resume;
  243. engine->instmem.get = nv04_instmem_get;
  244. engine->instmem.put = nv04_instmem_put;
  245. engine->instmem.map = nv04_instmem_map;
  246. engine->instmem.unmap = nv04_instmem_unmap;
  247. engine->instmem.flush = nv04_instmem_flush;
  248. engine->mc.init = nv40_mc_init;
  249. engine->mc.takedown = nv40_mc_takedown;
  250. engine->timer.init = nv04_timer_init;
  251. engine->timer.read = nv04_timer_read;
  252. engine->timer.takedown = nv04_timer_takedown;
  253. engine->fb.init = nv40_fb_init;
  254. engine->fb.takedown = nv40_fb_takedown;
  255. engine->fb.init_tile_region = nv30_fb_init_tile_region;
  256. engine->fb.set_tile_region = nv40_fb_set_tile_region;
  257. engine->fb.free_tile_region = nv30_fb_free_tile_region;
  258. engine->fifo.channels = 32;
  259. engine->fifo.init = nv40_fifo_init;
  260. engine->fifo.takedown = nv04_fifo_fini;
  261. engine->fifo.disable = nv04_fifo_disable;
  262. engine->fifo.enable = nv04_fifo_enable;
  263. engine->fifo.reassign = nv04_fifo_reassign;
  264. engine->fifo.cache_pull = nv04_fifo_cache_pull;
  265. engine->fifo.channel_id = nv10_fifo_channel_id;
  266. engine->fifo.create_context = nv40_fifo_create_context;
  267. engine->fifo.destroy_context = nv04_fifo_destroy_context;
  268. engine->fifo.load_context = nv40_fifo_load_context;
  269. engine->fifo.unload_context = nv40_fifo_unload_context;
  270. engine->display.early_init = nv04_display_early_init;
  271. engine->display.late_takedown = nv04_display_late_takedown;
  272. engine->display.create = nv04_display_create;
  273. engine->display.init = nv04_display_init;
  274. engine->display.destroy = nv04_display_destroy;
  275. engine->gpio.init = nouveau_stub_init;
  276. engine->gpio.takedown = nouveau_stub_takedown;
  277. engine->gpio.get = nv10_gpio_get;
  278. engine->gpio.set = nv10_gpio_set;
  279. engine->gpio.irq_enable = NULL;
  280. engine->pm.clock_get = nv04_pm_clock_get;
  281. engine->pm.clock_pre = nv04_pm_clock_pre;
  282. engine->pm.clock_set = nv04_pm_clock_set;
  283. engine->pm.voltage_get = nouveau_voltage_gpio_get;
  284. engine->pm.voltage_set = nouveau_voltage_gpio_set;
  285. engine->pm.temp_get = nv40_temp_get;
  286. engine->vram.init = nouveau_mem_detect;
  287. engine->vram.flags_valid = nouveau_mem_flags_valid;
  288. break;
  289. case 0x50:
  290. case 0x80: /* gotta love NVIDIA's consistency.. */
  291. case 0x90:
  292. case 0xA0:
  293. engine->instmem.init = nv50_instmem_init;
  294. engine->instmem.takedown = nv50_instmem_takedown;
  295. engine->instmem.suspend = nv50_instmem_suspend;
  296. engine->instmem.resume = nv50_instmem_resume;
  297. engine->instmem.get = nv50_instmem_get;
  298. engine->instmem.put = nv50_instmem_put;
  299. engine->instmem.map = nv50_instmem_map;
  300. engine->instmem.unmap = nv50_instmem_unmap;
  301. if (dev_priv->chipset == 0x50)
  302. engine->instmem.flush = nv50_instmem_flush;
  303. else
  304. engine->instmem.flush = nv84_instmem_flush;
  305. engine->mc.init = nv50_mc_init;
  306. engine->mc.takedown = nv50_mc_takedown;
  307. engine->timer.init = nv04_timer_init;
  308. engine->timer.read = nv04_timer_read;
  309. engine->timer.takedown = nv04_timer_takedown;
  310. engine->fb.init = nv50_fb_init;
  311. engine->fb.takedown = nv50_fb_takedown;
  312. engine->fifo.channels = 128;
  313. engine->fifo.init = nv50_fifo_init;
  314. engine->fifo.takedown = nv50_fifo_takedown;
  315. engine->fifo.disable = nv04_fifo_disable;
  316. engine->fifo.enable = nv04_fifo_enable;
  317. engine->fifo.reassign = nv04_fifo_reassign;
  318. engine->fifo.channel_id = nv50_fifo_channel_id;
  319. engine->fifo.create_context = nv50_fifo_create_context;
  320. engine->fifo.destroy_context = nv50_fifo_destroy_context;
  321. engine->fifo.load_context = nv50_fifo_load_context;
  322. engine->fifo.unload_context = nv50_fifo_unload_context;
  323. engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
  324. engine->display.early_init = nv50_display_early_init;
  325. engine->display.late_takedown = nv50_display_late_takedown;
  326. engine->display.create = nv50_display_create;
  327. engine->display.init = nv50_display_init;
  328. engine->display.destroy = nv50_display_destroy;
  329. engine->gpio.init = nv50_gpio_init;
  330. engine->gpio.takedown = nv50_gpio_fini;
  331. engine->gpio.get = nv50_gpio_get;
  332. engine->gpio.set = nv50_gpio_set;
  333. engine->gpio.irq_register = nv50_gpio_irq_register;
  334. engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
  335. engine->gpio.irq_enable = nv50_gpio_irq_enable;
  336. switch (dev_priv->chipset) {
  337. case 0x84:
  338. case 0x86:
  339. case 0x92:
  340. case 0x94:
  341. case 0x96:
  342. case 0x98:
  343. case 0xa0:
  344. case 0xaa:
  345. case 0xac:
  346. case 0x50:
  347. engine->pm.clock_get = nv50_pm_clock_get;
  348. engine->pm.clock_pre = nv50_pm_clock_pre;
  349. engine->pm.clock_set = nv50_pm_clock_set;
  350. break;
  351. default:
  352. engine->pm.clock_get = nva3_pm_clock_get;
  353. engine->pm.clock_pre = nva3_pm_clock_pre;
  354. engine->pm.clock_set = nva3_pm_clock_set;
  355. break;
  356. }
  357. engine->pm.voltage_get = nouveau_voltage_gpio_get;
  358. engine->pm.voltage_set = nouveau_voltage_gpio_set;
  359. if (dev_priv->chipset >= 0x84)
  360. engine->pm.temp_get = nv84_temp_get;
  361. else
  362. engine->pm.temp_get = nv40_temp_get;
  363. engine->vram.init = nv50_vram_init;
  364. engine->vram.get = nv50_vram_new;
  365. engine->vram.put = nv50_vram_del;
  366. engine->vram.flags_valid = nv50_vram_flags_valid;
  367. break;
  368. case 0xC0:
  369. engine->instmem.init = nvc0_instmem_init;
  370. engine->instmem.takedown = nvc0_instmem_takedown;
  371. engine->instmem.suspend = nvc0_instmem_suspend;
  372. engine->instmem.resume = nvc0_instmem_resume;
  373. engine->instmem.get = nv50_instmem_get;
  374. engine->instmem.put = nv50_instmem_put;
  375. engine->instmem.map = nv50_instmem_map;
  376. engine->instmem.unmap = nv50_instmem_unmap;
  377. engine->instmem.flush = nv84_instmem_flush;
  378. engine->mc.init = nv50_mc_init;
  379. engine->mc.takedown = nv50_mc_takedown;
  380. engine->timer.init = nv04_timer_init;
  381. engine->timer.read = nv04_timer_read;
  382. engine->timer.takedown = nv04_timer_takedown;
  383. engine->fb.init = nvc0_fb_init;
  384. engine->fb.takedown = nvc0_fb_takedown;
  385. engine->fifo.channels = 128;
  386. engine->fifo.init = nvc0_fifo_init;
  387. engine->fifo.takedown = nvc0_fifo_takedown;
  388. engine->fifo.disable = nvc0_fifo_disable;
  389. engine->fifo.enable = nvc0_fifo_enable;
  390. engine->fifo.reassign = nvc0_fifo_reassign;
  391. engine->fifo.channel_id = nvc0_fifo_channel_id;
  392. engine->fifo.create_context = nvc0_fifo_create_context;
  393. engine->fifo.destroy_context = nvc0_fifo_destroy_context;
  394. engine->fifo.load_context = nvc0_fifo_load_context;
  395. engine->fifo.unload_context = nvc0_fifo_unload_context;
  396. engine->display.early_init = nv50_display_early_init;
  397. engine->display.late_takedown = nv50_display_late_takedown;
  398. engine->display.create = nv50_display_create;
  399. engine->display.init = nv50_display_init;
  400. engine->display.destroy = nv50_display_destroy;
  401. engine->gpio.init = nv50_gpio_init;
  402. engine->gpio.takedown = nouveau_stub_takedown;
  403. engine->gpio.get = nv50_gpio_get;
  404. engine->gpio.set = nv50_gpio_set;
  405. engine->gpio.irq_register = nv50_gpio_irq_register;
  406. engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
  407. engine->gpio.irq_enable = nv50_gpio_irq_enable;
  408. engine->vram.init = nvc0_vram_init;
  409. engine->vram.get = nvc0_vram_new;
  410. engine->vram.put = nv50_vram_del;
  411. engine->vram.flags_valid = nvc0_vram_flags_valid;
  412. break;
  413. default:
  414. NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
  415. return 1;
  416. }
  417. return 0;
  418. }
  419. static unsigned int
  420. nouveau_vga_set_decode(void *priv, bool state)
  421. {
  422. struct drm_device *dev = priv;
  423. struct drm_nouveau_private *dev_priv = dev->dev_private;
  424. if (dev_priv->chipset >= 0x40)
  425. nv_wr32(dev, 0x88054, state);
  426. else
  427. nv_wr32(dev, 0x1854, state);
  428. if (state)
  429. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  430. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  431. else
  432. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  433. }
  434. static int
  435. nouveau_card_init_channel(struct drm_device *dev)
  436. {
  437. struct drm_nouveau_private *dev_priv = dev->dev_private;
  438. int ret;
  439. ret = nouveau_channel_alloc(dev, &dev_priv->channel,
  440. (struct drm_file *)-2, NvDmaFB, NvDmaTT);
  441. if (ret)
  442. return ret;
  443. mutex_unlock(&dev_priv->channel->mutex);
  444. return 0;
  445. }
  446. static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
  447. enum vga_switcheroo_state state)
  448. {
  449. struct drm_device *dev = pci_get_drvdata(pdev);
  450. pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
  451. if (state == VGA_SWITCHEROO_ON) {
  452. printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
  453. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  454. nouveau_pci_resume(pdev);
  455. drm_kms_helper_poll_enable(dev);
  456. dev->switch_power_state = DRM_SWITCH_POWER_ON;
  457. } else {
  458. printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
  459. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  460. drm_kms_helper_poll_disable(dev);
  461. nouveau_pci_suspend(pdev, pmm);
  462. dev->switch_power_state = DRM_SWITCH_POWER_OFF;
  463. }
  464. }
  465. static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
  466. {
  467. struct drm_device *dev = pci_get_drvdata(pdev);
  468. nouveau_fbcon_output_poll_changed(dev);
  469. }
  470. static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
  471. {
  472. struct drm_device *dev = pci_get_drvdata(pdev);
  473. bool can_switch;
  474. spin_lock(&dev->count_lock);
  475. can_switch = (dev->open_count == 0);
  476. spin_unlock(&dev->count_lock);
  477. return can_switch;
  478. }
  479. int
  480. nouveau_card_init(struct drm_device *dev)
  481. {
  482. struct drm_nouveau_private *dev_priv = dev->dev_private;
  483. struct nouveau_engine *engine;
  484. int ret, e = 0;
  485. vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
  486. vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
  487. nouveau_switcheroo_reprobe,
  488. nouveau_switcheroo_can_switch);
  489. /* Initialise internal driver API hooks */
  490. ret = nouveau_init_engine_ptrs(dev);
  491. if (ret)
  492. goto out;
  493. engine = &dev_priv->engine;
  494. spin_lock_init(&dev_priv->channels.lock);
  495. spin_lock_init(&dev_priv->tile.lock);
  496. spin_lock_init(&dev_priv->context_switch_lock);
  497. spin_lock_init(&dev_priv->vm_lock);
  498. /* Make the CRTCs and I2C buses accessible */
  499. ret = engine->display.early_init(dev);
  500. if (ret)
  501. goto out;
  502. /* Parse BIOS tables / Run init tables if card not POSTed */
  503. ret = nouveau_bios_init(dev);
  504. if (ret)
  505. goto out_display_early;
  506. nouveau_pm_init(dev);
  507. ret = nouveau_mem_vram_init(dev);
  508. if (ret)
  509. goto out_bios;
  510. ret = nouveau_gpuobj_init(dev);
  511. if (ret)
  512. goto out_vram;
  513. ret = engine->instmem.init(dev);
  514. if (ret)
  515. goto out_gpuobj;
  516. ret = nouveau_mem_gart_init(dev);
  517. if (ret)
  518. goto out_instmem;
  519. /* PMC */
  520. ret = engine->mc.init(dev);
  521. if (ret)
  522. goto out_gart;
  523. /* PGPIO */
  524. ret = engine->gpio.init(dev);
  525. if (ret)
  526. goto out_mc;
  527. /* PTIMER */
  528. ret = engine->timer.init(dev);
  529. if (ret)
  530. goto out_gpio;
  531. /* PFB */
  532. ret = engine->fb.init(dev);
  533. if (ret)
  534. goto out_timer;
  535. if (!nouveau_noaccel) {
  536. switch (dev_priv->card_type) {
  537. case NV_04:
  538. nv04_graph_create(dev);
  539. break;
  540. case NV_10:
  541. nv10_graph_create(dev);
  542. break;
  543. case NV_20:
  544. case NV_30:
  545. nv20_graph_create(dev);
  546. break;
  547. case NV_40:
  548. nv40_graph_create(dev);
  549. break;
  550. case NV_50:
  551. nv50_graph_create(dev);
  552. break;
  553. case NV_C0:
  554. nvc0_graph_create(dev);
  555. break;
  556. default:
  557. break;
  558. }
  559. switch (dev_priv->chipset) {
  560. case 0x84:
  561. case 0x86:
  562. case 0x92:
  563. case 0x94:
  564. case 0x96:
  565. case 0xa0:
  566. nv84_crypt_create(dev);
  567. break;
  568. }
  569. switch (dev_priv->card_type) {
  570. case NV_50:
  571. switch (dev_priv->chipset) {
  572. case 0xa3:
  573. case 0xa5:
  574. case 0xa8:
  575. case 0xaf:
  576. nva3_copy_create(dev);
  577. break;
  578. }
  579. break;
  580. case NV_C0:
  581. nvc0_copy_create(dev, 0);
  582. nvc0_copy_create(dev, 1);
  583. break;
  584. default:
  585. break;
  586. }
  587. if (dev_priv->card_type == NV_40)
  588. nv40_mpeg_create(dev);
  589. else
  590. if (dev_priv->card_type == NV_50 &&
  591. (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
  592. nv50_mpeg_create(dev);
  593. for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
  594. if (dev_priv->eng[e]) {
  595. ret = dev_priv->eng[e]->init(dev, e);
  596. if (ret)
  597. goto out_engine;
  598. }
  599. }
  600. /* PFIFO */
  601. ret = engine->fifo.init(dev);
  602. if (ret)
  603. goto out_engine;
  604. }
  605. ret = engine->display.create(dev);
  606. if (ret)
  607. goto out_fifo;
  608. ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
  609. if (ret)
  610. goto out_vblank;
  611. ret = nouveau_irq_init(dev);
  612. if (ret)
  613. goto out_vblank;
  614. /* what about PVIDEO/PCRTC/PRAMDAC etc? */
  615. if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
  616. ret = nouveau_fence_init(dev);
  617. if (ret)
  618. goto out_irq;
  619. ret = nouveau_card_init_channel(dev);
  620. if (ret)
  621. goto out_fence;
  622. }
  623. nouveau_fbcon_init(dev);
  624. drm_kms_helper_poll_init(dev);
  625. return 0;
  626. out_fence:
  627. nouveau_fence_fini(dev);
  628. out_irq:
  629. nouveau_irq_fini(dev);
  630. out_vblank:
  631. drm_vblank_cleanup(dev);
  632. engine->display.destroy(dev);
  633. out_fifo:
  634. if (!nouveau_noaccel)
  635. engine->fifo.takedown(dev);
  636. out_engine:
  637. if (!nouveau_noaccel) {
  638. for (e = e - 1; e >= 0; e--) {
  639. if (!dev_priv->eng[e])
  640. continue;
  641. dev_priv->eng[e]->fini(dev, e);
  642. dev_priv->eng[e]->destroy(dev,e );
  643. }
  644. }
  645. engine->fb.takedown(dev);
  646. out_timer:
  647. engine->timer.takedown(dev);
  648. out_gpio:
  649. engine->gpio.takedown(dev);
  650. out_mc:
  651. engine->mc.takedown(dev);
  652. out_gart:
  653. nouveau_mem_gart_fini(dev);
  654. out_instmem:
  655. engine->instmem.takedown(dev);
  656. out_gpuobj:
  657. nouveau_gpuobj_takedown(dev);
  658. out_vram:
  659. nouveau_mem_vram_fini(dev);
  660. out_bios:
  661. nouveau_pm_fini(dev);
  662. nouveau_bios_takedown(dev);
  663. out_display_early:
  664. engine->display.late_takedown(dev);
  665. out:
  666. vga_client_register(dev->pdev, NULL, NULL, NULL);
  667. return ret;
  668. }
  669. static void nouveau_card_takedown(struct drm_device *dev)
  670. {
  671. struct drm_nouveau_private *dev_priv = dev->dev_private;
  672. struct nouveau_engine *engine = &dev_priv->engine;
  673. int e;
  674. if (dev_priv->channel) {
  675. nouveau_fence_fini(dev);
  676. nouveau_channel_put_unlocked(&dev_priv->channel);
  677. }
  678. if (!nouveau_noaccel) {
  679. engine->fifo.takedown(dev);
  680. for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
  681. if (dev_priv->eng[e]) {
  682. dev_priv->eng[e]->fini(dev, e);
  683. dev_priv->eng[e]->destroy(dev,e );
  684. }
  685. }
  686. }
  687. engine->fb.takedown(dev);
  688. engine->timer.takedown(dev);
  689. engine->gpio.takedown(dev);
  690. engine->mc.takedown(dev);
  691. engine->display.late_takedown(dev);
  692. if (dev_priv->vga_ram) {
  693. nouveau_bo_unpin(dev_priv->vga_ram);
  694. nouveau_bo_ref(NULL, &dev_priv->vga_ram);
  695. }
  696. mutex_lock(&dev->struct_mutex);
  697. ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  698. ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
  699. mutex_unlock(&dev->struct_mutex);
  700. nouveau_mem_gart_fini(dev);
  701. engine->instmem.takedown(dev);
  702. nouveau_gpuobj_takedown(dev);
  703. nouveau_mem_vram_fini(dev);
  704. nouveau_irq_fini(dev);
  705. drm_vblank_cleanup(dev);
  706. nouveau_pm_fini(dev);
  707. nouveau_bios_takedown(dev);
  708. vga_client_register(dev->pdev, NULL, NULL, NULL);
  709. }
  710. /* here a client dies, release the stuff that was allocated for its
  711. * file_priv */
  712. void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
  713. {
  714. nouveau_channel_cleanup(dev, file_priv);
  715. }
  716. /* first module load, setup the mmio/fb mapping */
  717. /* KMS: we need mmio at load time, not when the first drm client opens. */
  718. int nouveau_firstopen(struct drm_device *dev)
  719. {
  720. return 0;
  721. }
  722. /* if we have an OF card, copy vbios to RAMIN */
  723. static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
  724. {
  725. #if defined(__powerpc__)
  726. int size, i;
  727. const uint32_t *bios;
  728. struct device_node *dn = pci_device_to_OF_node(dev->pdev);
  729. if (!dn) {
  730. NV_INFO(dev, "Unable to get the OF node\n");
  731. return;
  732. }
  733. bios = of_get_property(dn, "NVDA,BMP", &size);
  734. if (bios) {
  735. for (i = 0; i < size; i += 4)
  736. nv_wi32(dev, i, bios[i/4]);
  737. NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
  738. } else {
  739. NV_INFO(dev, "Unable to get the OF bios\n");
  740. }
  741. #endif
  742. }
  743. static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
  744. {
  745. struct pci_dev *pdev = dev->pdev;
  746. struct apertures_struct *aper = alloc_apertures(3);
  747. if (!aper)
  748. return NULL;
  749. aper->ranges[0].base = pci_resource_start(pdev, 1);
  750. aper->ranges[0].size = pci_resource_len(pdev, 1);
  751. aper->count = 1;
  752. if (pci_resource_len(pdev, 2)) {
  753. aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
  754. aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
  755. aper->count++;
  756. }
  757. if (pci_resource_len(pdev, 3)) {
  758. aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
  759. aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
  760. aper->count++;
  761. }
  762. return aper;
  763. }
  764. static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
  765. {
  766. struct drm_nouveau_private *dev_priv = dev->dev_private;
  767. bool primary = false;
  768. dev_priv->apertures = nouveau_get_apertures(dev);
  769. if (!dev_priv->apertures)
  770. return -ENOMEM;
  771. #ifdef CONFIG_X86
  772. primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  773. #endif
  774. remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
  775. return 0;
  776. }
  777. int nouveau_load(struct drm_device *dev, unsigned long flags)
  778. {
  779. struct drm_nouveau_private *dev_priv;
  780. uint32_t reg0;
  781. resource_size_t mmio_start_offs;
  782. int ret;
  783. dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
  784. if (!dev_priv) {
  785. ret = -ENOMEM;
  786. goto err_out;
  787. }
  788. dev->dev_private = dev_priv;
  789. dev_priv->dev = dev;
  790. dev_priv->flags = flags & NOUVEAU_FLAGS;
  791. NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
  792. dev->pci_vendor, dev->pci_device, dev->pdev->class);
  793. /* resource 0 is mmio regs */
  794. /* resource 1 is linear FB */
  795. /* resource 2 is RAMIN (mmio regs + 0x1000000) */
  796. /* resource 6 is bios */
  797. /* map the mmio regs */
  798. mmio_start_offs = pci_resource_start(dev->pdev, 0);
  799. dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
  800. if (!dev_priv->mmio) {
  801. NV_ERROR(dev, "Unable to initialize the mmio mapping. "
  802. "Please report your setup to " DRIVER_EMAIL "\n");
  803. ret = -EINVAL;
  804. goto err_priv;
  805. }
  806. NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
  807. (unsigned long long)mmio_start_offs);
  808. #ifdef __BIG_ENDIAN
  809. /* Put the card in BE mode if it's not */
  810. if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
  811. nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
  812. DRM_MEMORYBARRIER();
  813. #endif
  814. /* Time to determine the card architecture */
  815. reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
  816. dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
  817. /* We're dealing with >=NV10 */
  818. if ((reg0 & 0x0f000000) > 0) {
  819. /* Bit 27-20 contain the architecture in hex */
  820. dev_priv->chipset = (reg0 & 0xff00000) >> 20;
  821. dev_priv->stepping = (reg0 & 0xff);
  822. /* NV04 or NV05 */
  823. } else if ((reg0 & 0xff00fff0) == 0x20004000) {
  824. if (reg0 & 0x00f00000)
  825. dev_priv->chipset = 0x05;
  826. else
  827. dev_priv->chipset = 0x04;
  828. } else
  829. dev_priv->chipset = 0xff;
  830. switch (dev_priv->chipset & 0xf0) {
  831. case 0x00:
  832. case 0x10:
  833. case 0x20:
  834. case 0x30:
  835. dev_priv->card_type = dev_priv->chipset & 0xf0;
  836. break;
  837. case 0x40:
  838. case 0x60:
  839. dev_priv->card_type = NV_40;
  840. break;
  841. case 0x50:
  842. case 0x80:
  843. case 0x90:
  844. case 0xa0:
  845. dev_priv->card_type = NV_50;
  846. break;
  847. case 0xc0:
  848. dev_priv->card_type = NV_C0;
  849. break;
  850. default:
  851. NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
  852. ret = -EINVAL;
  853. goto err_mmio;
  854. }
  855. NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
  856. dev_priv->card_type, reg0);
  857. ret = nouveau_remove_conflicting_drivers(dev);
  858. if (ret)
  859. goto err_mmio;
  860. /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
  861. if (dev_priv->card_type >= NV_40) {
  862. int ramin_bar = 2;
  863. if (pci_resource_len(dev->pdev, ramin_bar) == 0)
  864. ramin_bar = 3;
  865. dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
  866. dev_priv->ramin =
  867. ioremap(pci_resource_start(dev->pdev, ramin_bar),
  868. dev_priv->ramin_size);
  869. if (!dev_priv->ramin) {
  870. NV_ERROR(dev, "Failed to PRAMIN BAR");
  871. ret = -ENOMEM;
  872. goto err_mmio;
  873. }
  874. } else {
  875. dev_priv->ramin_size = 1 * 1024 * 1024;
  876. dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
  877. dev_priv->ramin_size);
  878. if (!dev_priv->ramin) {
  879. NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
  880. ret = -ENOMEM;
  881. goto err_mmio;
  882. }
  883. }
  884. nouveau_OF_copy_vbios_to_ramin(dev);
  885. /* Special flags */
  886. if (dev->pci_device == 0x01a0)
  887. dev_priv->flags |= NV_NFORCE;
  888. else if (dev->pci_device == 0x01f0)
  889. dev_priv->flags |= NV_NFORCE2;
  890. /* For kernel modesetting, init card now and bring up fbcon */
  891. ret = nouveau_card_init(dev);
  892. if (ret)
  893. goto err_ramin;
  894. return 0;
  895. err_ramin:
  896. iounmap(dev_priv->ramin);
  897. err_mmio:
  898. iounmap(dev_priv->mmio);
  899. err_priv:
  900. kfree(dev_priv);
  901. dev->dev_private = NULL;
  902. err_out:
  903. return ret;
  904. }
  905. void nouveau_lastclose(struct drm_device *dev)
  906. {
  907. vga_switcheroo_process_delayed_switch();
  908. }
  909. int nouveau_unload(struct drm_device *dev)
  910. {
  911. struct drm_nouveau_private *dev_priv = dev->dev_private;
  912. struct nouveau_engine *engine = &dev_priv->engine;
  913. drm_kms_helper_poll_fini(dev);
  914. nouveau_fbcon_fini(dev);
  915. engine->display.destroy(dev);
  916. nouveau_card_takedown(dev);
  917. iounmap(dev_priv->mmio);
  918. iounmap(dev_priv->ramin);
  919. kfree(dev_priv);
  920. dev->dev_private = NULL;
  921. return 0;
  922. }
  923. int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
  924. struct drm_file *file_priv)
  925. {
  926. struct drm_nouveau_private *dev_priv = dev->dev_private;
  927. struct drm_nouveau_getparam *getparam = data;
  928. switch (getparam->param) {
  929. case NOUVEAU_GETPARAM_CHIPSET_ID:
  930. getparam->value = dev_priv->chipset;
  931. break;
  932. case NOUVEAU_GETPARAM_PCI_VENDOR:
  933. getparam->value = dev->pci_vendor;
  934. break;
  935. case NOUVEAU_GETPARAM_PCI_DEVICE:
  936. getparam->value = dev->pci_device;
  937. break;
  938. case NOUVEAU_GETPARAM_BUS_TYPE:
  939. if (drm_pci_device_is_agp(dev))
  940. getparam->value = NV_AGP;
  941. else if (drm_pci_device_is_pcie(dev))
  942. getparam->value = NV_PCIE;
  943. else
  944. getparam->value = NV_PCI;
  945. break;
  946. case NOUVEAU_GETPARAM_FB_SIZE:
  947. getparam->value = dev_priv->fb_available_size;
  948. break;
  949. case NOUVEAU_GETPARAM_AGP_SIZE:
  950. getparam->value = dev_priv->gart_info.aper_size;
  951. break;
  952. case NOUVEAU_GETPARAM_VM_VRAM_BASE:
  953. getparam->value = 0; /* deprecated */
  954. break;
  955. case NOUVEAU_GETPARAM_PTIMER_TIME:
  956. getparam->value = dev_priv->engine.timer.read(dev);
  957. break;
  958. case NOUVEAU_GETPARAM_HAS_BO_USAGE:
  959. getparam->value = 1;
  960. break;
  961. case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
  962. getparam->value = 1;
  963. break;
  964. case NOUVEAU_GETPARAM_GRAPH_UNITS:
  965. /* NV40 and NV50 versions are quite different, but register
  966. * address is the same. User is supposed to know the card
  967. * family anyway... */
  968. if (dev_priv->chipset >= 0x40) {
  969. getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
  970. break;
  971. }
  972. /* FALLTHRU */
  973. default:
  974. NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
  975. return -EINVAL;
  976. }
  977. return 0;
  978. }
  979. int
  980. nouveau_ioctl_setparam(struct drm_device *dev, void *data,
  981. struct drm_file *file_priv)
  982. {
  983. struct drm_nouveau_setparam *setparam = data;
  984. switch (setparam->param) {
  985. default:
  986. NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
  987. return -EINVAL;
  988. }
  989. return 0;
  990. }
  991. /* Wait until (value(reg) & mask) == val, up until timeout has hit */
  992. bool
  993. nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
  994. uint32_t reg, uint32_t mask, uint32_t val)
  995. {
  996. struct drm_nouveau_private *dev_priv = dev->dev_private;
  997. struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  998. uint64_t start = ptimer->read(dev);
  999. do {
  1000. if ((nv_rd32(dev, reg) & mask) == val)
  1001. return true;
  1002. } while (ptimer->read(dev) - start < timeout);
  1003. return false;
  1004. }
  1005. /* Wait until (value(reg) & mask) != val, up until timeout has hit */
  1006. bool
  1007. nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
  1008. uint32_t reg, uint32_t mask, uint32_t val)
  1009. {
  1010. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1011. struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  1012. uint64_t start = ptimer->read(dev);
  1013. do {
  1014. if ((nv_rd32(dev, reg) & mask) != val)
  1015. return true;
  1016. } while (ptimer->read(dev) - start < timeout);
  1017. return false;
  1018. }
  1019. /* Waits for PGRAPH to go completely idle */
  1020. bool nouveau_wait_for_idle(struct drm_device *dev)
  1021. {
  1022. struct drm_nouveau_private *dev_priv = dev->dev_private;
  1023. uint32_t mask = ~0;
  1024. if (dev_priv->card_type == NV_40)
  1025. mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
  1026. if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
  1027. NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
  1028. nv_rd32(dev, NV04_PGRAPH_STATUS));
  1029. return false;
  1030. }
  1031. return true;
  1032. }