/drivers/gpu/drm/radeon/rv770.c

https://bitbucket.org/wisechild/galaxy-nexus · C · 1411 lines · 1150 code · 156 blank · 105 comment · 166 complexity · 2775a69712dece8ef9fc593f042b295b MD5 · raw file

  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/firmware.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "radeon.h"
  33. #include "radeon_asic.h"
  34. #include "radeon_drm.h"
  35. #include "rv770d.h"
  36. #include "atom.h"
  37. #include "avivod.h"
  38. #define R700_PFP_UCODE_SIZE 848
  39. #define R700_PM4_UCODE_SIZE 1360
  40. static void rv770_gpu_init(struct radeon_device *rdev);
  41. void rv770_fini(struct radeon_device *rdev);
  42. static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  43. u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  44. {
  45. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  46. u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  47. int i;
  48. /* Lock the graphics update lock */
  49. tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  50. WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  51. /* update the scanout addresses */
  52. if (radeon_crtc->crtc_id) {
  53. WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  54. WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  55. } else {
  56. WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  57. WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  58. }
  59. WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  60. (u32)crtc_base);
  61. WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  62. (u32)crtc_base);
  63. /* Wait for update_pending to go high. */
  64. for (i = 0; i < rdev->usec_timeout; i++) {
  65. if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
  66. break;
  67. udelay(1);
  68. }
  69. DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  70. /* Unlock the lock, so double-buffering can take place inside vblank */
  71. tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  72. WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  73. /* Return current update_pending status: */
  74. return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  75. }
  76. /* get temperature in millidegrees */
  77. int rv770_get_temp(struct radeon_device *rdev)
  78. {
  79. u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  80. ASIC_T_SHIFT;
  81. int actual_temp;
  82. if (temp & 0x400)
  83. actual_temp = -256;
  84. else if (temp & 0x200)
  85. actual_temp = 255;
  86. else if (temp & 0x100) {
  87. actual_temp = temp & 0x1ff;
  88. actual_temp |= ~0x1ff;
  89. } else
  90. actual_temp = temp & 0xff;
  91. return (actual_temp * 1000) / 2;
  92. }
  93. void rv770_pm_misc(struct radeon_device *rdev)
  94. {
  95. int req_ps_idx = rdev->pm.requested_power_state_index;
  96. int req_cm_idx = rdev->pm.requested_clock_mode_index;
  97. struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  98. struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
  99. if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
  100. /* 0xff01 is a flag rather then an actual voltage */
  101. if (voltage->voltage == 0xff01)
  102. return;
  103. if (voltage->voltage != rdev->pm.current_vddc) {
  104. radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
  105. rdev->pm.current_vddc = voltage->voltage;
  106. DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
  107. }
  108. }
  109. }
  110. /*
  111. * GART
  112. */
  113. int rv770_pcie_gart_enable(struct radeon_device *rdev)
  114. {
  115. u32 tmp;
  116. int r, i;
  117. if (rdev->gart.table.vram.robj == NULL) {
  118. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  119. return -EINVAL;
  120. }
  121. r = radeon_gart_table_vram_pin(rdev);
  122. if (r)
  123. return r;
  124. radeon_gart_restore(rdev);
  125. /* Setup L2 cache */
  126. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  127. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  128. EFFECTIVE_L2_QUEUE_SIZE(7));
  129. WREG32(VM_L2_CNTL2, 0);
  130. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  131. /* Setup TLB control */
  132. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  133. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  134. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  135. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  136. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  137. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  138. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  139. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  140. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  141. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  142. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  143. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  144. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  145. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  146. WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  147. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  148. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  149. (u32)(rdev->dummy_page.addr >> 12));
  150. for (i = 1; i < 7; i++)
  151. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  152. r600_pcie_gart_tlb_flush(rdev);
  153. rdev->gart.ready = true;
  154. return 0;
  155. }
  156. void rv770_pcie_gart_disable(struct radeon_device *rdev)
  157. {
  158. u32 tmp;
  159. int i, r;
  160. /* Disable all tables */
  161. for (i = 0; i < 7; i++)
  162. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  163. /* Setup L2 cache */
  164. WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
  165. EFFECTIVE_L2_QUEUE_SIZE(7));
  166. WREG32(VM_L2_CNTL2, 0);
  167. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  168. /* Setup TLB control */
  169. tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  170. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  171. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  172. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  173. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  174. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  175. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  176. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  177. if (rdev->gart.table.vram.robj) {
  178. r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  179. if (likely(r == 0)) {
  180. radeon_bo_kunmap(rdev->gart.table.vram.robj);
  181. radeon_bo_unpin(rdev->gart.table.vram.robj);
  182. radeon_bo_unreserve(rdev->gart.table.vram.robj);
  183. }
  184. }
  185. }
  186. void rv770_pcie_gart_fini(struct radeon_device *rdev)
  187. {
  188. radeon_gart_fini(rdev);
  189. rv770_pcie_gart_disable(rdev);
  190. radeon_gart_table_vram_free(rdev);
  191. }
  192. void rv770_agp_enable(struct radeon_device *rdev)
  193. {
  194. u32 tmp;
  195. int i;
  196. /* Setup L2 cache */
  197. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  198. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  199. EFFECTIVE_L2_QUEUE_SIZE(7));
  200. WREG32(VM_L2_CNTL2, 0);
  201. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  202. /* Setup TLB control */
  203. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  204. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  205. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  206. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  207. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  208. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  209. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  210. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  211. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  212. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  213. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  214. for (i = 0; i < 7; i++)
  215. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  216. }
  217. static void rv770_mc_program(struct radeon_device *rdev)
  218. {
  219. struct rv515_mc_save save;
  220. u32 tmp;
  221. int i, j;
  222. /* Initialize HDP */
  223. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  224. WREG32((0x2c14 + j), 0x00000000);
  225. WREG32((0x2c18 + j), 0x00000000);
  226. WREG32((0x2c1c + j), 0x00000000);
  227. WREG32((0x2c20 + j), 0x00000000);
  228. WREG32((0x2c24 + j), 0x00000000);
  229. }
  230. /* r7xx hw bug. Read from HDP_DEBUG1 rather
  231. * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
  232. */
  233. tmp = RREG32(HDP_DEBUG1);
  234. rv515_mc_stop(rdev, &save);
  235. if (r600_mc_wait_for_idle(rdev)) {
  236. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  237. }
  238. /* Lockout access through VGA aperture*/
  239. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  240. /* Update configuration */
  241. if (rdev->flags & RADEON_IS_AGP) {
  242. if (rdev->mc.vram_start < rdev->mc.gtt_start) {
  243. /* VRAM before AGP */
  244. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  245. rdev->mc.vram_start >> 12);
  246. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  247. rdev->mc.gtt_end >> 12);
  248. } else {
  249. /* VRAM after AGP */
  250. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  251. rdev->mc.gtt_start >> 12);
  252. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  253. rdev->mc.vram_end >> 12);
  254. }
  255. } else {
  256. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  257. rdev->mc.vram_start >> 12);
  258. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  259. rdev->mc.vram_end >> 12);
  260. }
  261. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
  262. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  263. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  264. WREG32(MC_VM_FB_LOCATION, tmp);
  265. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  266. WREG32(HDP_NONSURFACE_INFO, (2 << 7));
  267. WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
  268. if (rdev->flags & RADEON_IS_AGP) {
  269. WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
  270. WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
  271. WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
  272. } else {
  273. WREG32(MC_VM_AGP_BASE, 0);
  274. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  275. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  276. }
  277. if (r600_mc_wait_for_idle(rdev)) {
  278. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  279. }
  280. rv515_mc_resume(rdev, &save);
  281. /* we need to own VRAM, so turn off the VGA renderer here
  282. * to stop it overwriting our objects */
  283. rv515_vga_render_disable(rdev);
  284. }
  285. /*
  286. * CP.
  287. */
  288. void r700_cp_stop(struct radeon_device *rdev)
  289. {
  290. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  291. WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
  292. WREG32(SCRATCH_UMSK, 0);
  293. }
  294. static int rv770_cp_load_microcode(struct radeon_device *rdev)
  295. {
  296. const __be32 *fw_data;
  297. int i;
  298. if (!rdev->me_fw || !rdev->pfp_fw)
  299. return -EINVAL;
  300. r700_cp_stop(rdev);
  301. WREG32(CP_RB_CNTL,
  302. #ifdef __BIG_ENDIAN
  303. BUF_SWAP_32BIT |
  304. #endif
  305. RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
  306. /* Reset cp */
  307. WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
  308. RREG32(GRBM_SOFT_RESET);
  309. mdelay(15);
  310. WREG32(GRBM_SOFT_RESET, 0);
  311. fw_data = (const __be32 *)rdev->pfp_fw->data;
  312. WREG32(CP_PFP_UCODE_ADDR, 0);
  313. for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
  314. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  315. WREG32(CP_PFP_UCODE_ADDR, 0);
  316. fw_data = (const __be32 *)rdev->me_fw->data;
  317. WREG32(CP_ME_RAM_WADDR, 0);
  318. for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
  319. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  320. WREG32(CP_PFP_UCODE_ADDR, 0);
  321. WREG32(CP_ME_RAM_WADDR, 0);
  322. WREG32(CP_ME_RAM_RADDR, 0);
  323. return 0;
  324. }
  325. void r700_cp_fini(struct radeon_device *rdev)
  326. {
  327. r700_cp_stop(rdev);
  328. radeon_ring_fini(rdev);
  329. }
  330. /*
  331. * Core functions
  332. */
  333. static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
  334. u32 num_tile_pipes,
  335. u32 num_backends,
  336. u32 backend_disable_mask)
  337. {
  338. u32 backend_map = 0;
  339. u32 enabled_backends_mask;
  340. u32 enabled_backends_count;
  341. u32 cur_pipe;
  342. u32 swizzle_pipe[R7XX_MAX_PIPES];
  343. u32 cur_backend;
  344. u32 i;
  345. bool force_no_swizzle;
  346. if (num_tile_pipes > R7XX_MAX_PIPES)
  347. num_tile_pipes = R7XX_MAX_PIPES;
  348. if (num_tile_pipes < 1)
  349. num_tile_pipes = 1;
  350. if (num_backends > R7XX_MAX_BACKENDS)
  351. num_backends = R7XX_MAX_BACKENDS;
  352. if (num_backends < 1)
  353. num_backends = 1;
  354. enabled_backends_mask = 0;
  355. enabled_backends_count = 0;
  356. for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
  357. if (((backend_disable_mask >> i) & 1) == 0) {
  358. enabled_backends_mask |= (1 << i);
  359. ++enabled_backends_count;
  360. }
  361. if (enabled_backends_count == num_backends)
  362. break;
  363. }
  364. if (enabled_backends_count == 0) {
  365. enabled_backends_mask = 1;
  366. enabled_backends_count = 1;
  367. }
  368. if (enabled_backends_count != num_backends)
  369. num_backends = enabled_backends_count;
  370. switch (rdev->family) {
  371. case CHIP_RV770:
  372. case CHIP_RV730:
  373. force_no_swizzle = false;
  374. break;
  375. case CHIP_RV710:
  376. case CHIP_RV740:
  377. default:
  378. force_no_swizzle = true;
  379. break;
  380. }
  381. memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
  382. switch (num_tile_pipes) {
  383. case 1:
  384. swizzle_pipe[0] = 0;
  385. break;
  386. case 2:
  387. swizzle_pipe[0] = 0;
  388. swizzle_pipe[1] = 1;
  389. break;
  390. case 3:
  391. if (force_no_swizzle) {
  392. swizzle_pipe[0] = 0;
  393. swizzle_pipe[1] = 1;
  394. swizzle_pipe[2] = 2;
  395. } else {
  396. swizzle_pipe[0] = 0;
  397. swizzle_pipe[1] = 2;
  398. swizzle_pipe[2] = 1;
  399. }
  400. break;
  401. case 4:
  402. if (force_no_swizzle) {
  403. swizzle_pipe[0] = 0;
  404. swizzle_pipe[1] = 1;
  405. swizzle_pipe[2] = 2;
  406. swizzle_pipe[3] = 3;
  407. } else {
  408. swizzle_pipe[0] = 0;
  409. swizzle_pipe[1] = 2;
  410. swizzle_pipe[2] = 3;
  411. swizzle_pipe[3] = 1;
  412. }
  413. break;
  414. case 5:
  415. if (force_no_swizzle) {
  416. swizzle_pipe[0] = 0;
  417. swizzle_pipe[1] = 1;
  418. swizzle_pipe[2] = 2;
  419. swizzle_pipe[3] = 3;
  420. swizzle_pipe[4] = 4;
  421. } else {
  422. swizzle_pipe[0] = 0;
  423. swizzle_pipe[1] = 2;
  424. swizzle_pipe[2] = 4;
  425. swizzle_pipe[3] = 1;
  426. swizzle_pipe[4] = 3;
  427. }
  428. break;
  429. case 6:
  430. if (force_no_swizzle) {
  431. swizzle_pipe[0] = 0;
  432. swizzle_pipe[1] = 1;
  433. swizzle_pipe[2] = 2;
  434. swizzle_pipe[3] = 3;
  435. swizzle_pipe[4] = 4;
  436. swizzle_pipe[5] = 5;
  437. } else {
  438. swizzle_pipe[0] = 0;
  439. swizzle_pipe[1] = 2;
  440. swizzle_pipe[2] = 4;
  441. swizzle_pipe[3] = 5;
  442. swizzle_pipe[4] = 3;
  443. swizzle_pipe[5] = 1;
  444. }
  445. break;
  446. case 7:
  447. if (force_no_swizzle) {
  448. swizzle_pipe[0] = 0;
  449. swizzle_pipe[1] = 1;
  450. swizzle_pipe[2] = 2;
  451. swizzle_pipe[3] = 3;
  452. swizzle_pipe[4] = 4;
  453. swizzle_pipe[5] = 5;
  454. swizzle_pipe[6] = 6;
  455. } else {
  456. swizzle_pipe[0] = 0;
  457. swizzle_pipe[1] = 2;
  458. swizzle_pipe[2] = 4;
  459. swizzle_pipe[3] = 6;
  460. swizzle_pipe[4] = 3;
  461. swizzle_pipe[5] = 1;
  462. swizzle_pipe[6] = 5;
  463. }
  464. break;
  465. case 8:
  466. if (force_no_swizzle) {
  467. swizzle_pipe[0] = 0;
  468. swizzle_pipe[1] = 1;
  469. swizzle_pipe[2] = 2;
  470. swizzle_pipe[3] = 3;
  471. swizzle_pipe[4] = 4;
  472. swizzle_pipe[5] = 5;
  473. swizzle_pipe[6] = 6;
  474. swizzle_pipe[7] = 7;
  475. } else {
  476. swizzle_pipe[0] = 0;
  477. swizzle_pipe[1] = 2;
  478. swizzle_pipe[2] = 4;
  479. swizzle_pipe[3] = 6;
  480. swizzle_pipe[4] = 3;
  481. swizzle_pipe[5] = 1;
  482. swizzle_pipe[6] = 7;
  483. swizzle_pipe[7] = 5;
  484. }
  485. break;
  486. }
  487. cur_backend = 0;
  488. for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
  489. while (((1 << cur_backend) & enabled_backends_mask) == 0)
  490. cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
  491. backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
  492. cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
  493. }
  494. return backend_map;
  495. }
  496. static void rv770_gpu_init(struct radeon_device *rdev)
  497. {
  498. int i, j, num_qd_pipes;
  499. u32 ta_aux_cntl;
  500. u32 sx_debug_1;
  501. u32 smx_dc_ctl0;
  502. u32 db_debug3;
  503. u32 num_gs_verts_per_thread;
  504. u32 vgt_gs_per_es;
  505. u32 gs_prim_buffer_depth = 0;
  506. u32 sq_ms_fifo_sizes;
  507. u32 sq_config;
  508. u32 sq_thread_resource_mgmt;
  509. u32 hdp_host_path_cntl;
  510. u32 sq_dyn_gpr_size_simd_ab_0;
  511. u32 backend_map;
  512. u32 gb_tiling_config = 0;
  513. u32 cc_rb_backend_disable = 0;
  514. u32 cc_gc_shader_pipe_config = 0;
  515. u32 mc_arb_ramcfg;
  516. u32 db_debug4;
  517. /* setup chip specs */
  518. switch (rdev->family) {
  519. case CHIP_RV770:
  520. rdev->config.rv770.max_pipes = 4;
  521. rdev->config.rv770.max_tile_pipes = 8;
  522. rdev->config.rv770.max_simds = 10;
  523. rdev->config.rv770.max_backends = 4;
  524. rdev->config.rv770.max_gprs = 256;
  525. rdev->config.rv770.max_threads = 248;
  526. rdev->config.rv770.max_stack_entries = 512;
  527. rdev->config.rv770.max_hw_contexts = 8;
  528. rdev->config.rv770.max_gs_threads = 16 * 2;
  529. rdev->config.rv770.sx_max_export_size = 128;
  530. rdev->config.rv770.sx_max_export_pos_size = 16;
  531. rdev->config.rv770.sx_max_export_smx_size = 112;
  532. rdev->config.rv770.sq_num_cf_insts = 2;
  533. rdev->config.rv770.sx_num_of_sets = 7;
  534. rdev->config.rv770.sc_prim_fifo_size = 0xF9;
  535. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  536. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  537. break;
  538. case CHIP_RV730:
  539. rdev->config.rv770.max_pipes = 2;
  540. rdev->config.rv770.max_tile_pipes = 4;
  541. rdev->config.rv770.max_simds = 8;
  542. rdev->config.rv770.max_backends = 2;
  543. rdev->config.rv770.max_gprs = 128;
  544. rdev->config.rv770.max_threads = 248;
  545. rdev->config.rv770.max_stack_entries = 256;
  546. rdev->config.rv770.max_hw_contexts = 8;
  547. rdev->config.rv770.max_gs_threads = 16 * 2;
  548. rdev->config.rv770.sx_max_export_size = 256;
  549. rdev->config.rv770.sx_max_export_pos_size = 32;
  550. rdev->config.rv770.sx_max_export_smx_size = 224;
  551. rdev->config.rv770.sq_num_cf_insts = 2;
  552. rdev->config.rv770.sx_num_of_sets = 7;
  553. rdev->config.rv770.sc_prim_fifo_size = 0xf9;
  554. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  555. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  556. if (rdev->config.rv770.sx_max_export_pos_size > 16) {
  557. rdev->config.rv770.sx_max_export_pos_size -= 16;
  558. rdev->config.rv770.sx_max_export_smx_size += 16;
  559. }
  560. break;
  561. case CHIP_RV710:
  562. rdev->config.rv770.max_pipes = 2;
  563. rdev->config.rv770.max_tile_pipes = 2;
  564. rdev->config.rv770.max_simds = 2;
  565. rdev->config.rv770.max_backends = 1;
  566. rdev->config.rv770.max_gprs = 256;
  567. rdev->config.rv770.max_threads = 192;
  568. rdev->config.rv770.max_stack_entries = 256;
  569. rdev->config.rv770.max_hw_contexts = 4;
  570. rdev->config.rv770.max_gs_threads = 8 * 2;
  571. rdev->config.rv770.sx_max_export_size = 128;
  572. rdev->config.rv770.sx_max_export_pos_size = 16;
  573. rdev->config.rv770.sx_max_export_smx_size = 112;
  574. rdev->config.rv770.sq_num_cf_insts = 1;
  575. rdev->config.rv770.sx_num_of_sets = 7;
  576. rdev->config.rv770.sc_prim_fifo_size = 0x40;
  577. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  578. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  579. break;
  580. case CHIP_RV740:
  581. rdev->config.rv770.max_pipes = 4;
  582. rdev->config.rv770.max_tile_pipes = 4;
  583. rdev->config.rv770.max_simds = 8;
  584. rdev->config.rv770.max_backends = 4;
  585. rdev->config.rv770.max_gprs = 256;
  586. rdev->config.rv770.max_threads = 248;
  587. rdev->config.rv770.max_stack_entries = 512;
  588. rdev->config.rv770.max_hw_contexts = 8;
  589. rdev->config.rv770.max_gs_threads = 16 * 2;
  590. rdev->config.rv770.sx_max_export_size = 256;
  591. rdev->config.rv770.sx_max_export_pos_size = 32;
  592. rdev->config.rv770.sx_max_export_smx_size = 224;
  593. rdev->config.rv770.sq_num_cf_insts = 2;
  594. rdev->config.rv770.sx_num_of_sets = 7;
  595. rdev->config.rv770.sc_prim_fifo_size = 0x100;
  596. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  597. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  598. if (rdev->config.rv770.sx_max_export_pos_size > 16) {
  599. rdev->config.rv770.sx_max_export_pos_size -= 16;
  600. rdev->config.rv770.sx_max_export_smx_size += 16;
  601. }
  602. break;
  603. default:
  604. break;
  605. }
  606. /* Initialize HDP */
  607. j = 0;
  608. for (i = 0; i < 32; i++) {
  609. WREG32((0x2c14 + j), 0x00000000);
  610. WREG32((0x2c18 + j), 0x00000000);
  611. WREG32((0x2c1c + j), 0x00000000);
  612. WREG32((0x2c20 + j), 0x00000000);
  613. WREG32((0x2c24 + j), 0x00000000);
  614. j += 0x18;
  615. }
  616. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  617. /* setup tiling, simd, pipe config */
  618. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  619. switch (rdev->config.rv770.max_tile_pipes) {
  620. case 1:
  621. default:
  622. gb_tiling_config |= PIPE_TILING(0);
  623. break;
  624. case 2:
  625. gb_tiling_config |= PIPE_TILING(1);
  626. break;
  627. case 4:
  628. gb_tiling_config |= PIPE_TILING(2);
  629. break;
  630. case 8:
  631. gb_tiling_config |= PIPE_TILING(3);
  632. break;
  633. }
  634. rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
  635. if (rdev->family == CHIP_RV770)
  636. gb_tiling_config |= BANK_TILING(1);
  637. else
  638. gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
  639. rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
  640. gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
  641. if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
  642. rdev->config.rv770.tiling_group_size = 512;
  643. else
  644. rdev->config.rv770.tiling_group_size = 256;
  645. if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
  646. gb_tiling_config |= ROW_TILING(3);
  647. gb_tiling_config |= SAMPLE_SPLIT(3);
  648. } else {
  649. gb_tiling_config |=
  650. ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
  651. gb_tiling_config |=
  652. SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
  653. }
  654. gb_tiling_config |= BANK_SWAPS(1);
  655. cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
  656. cc_rb_backend_disable |=
  657. BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
  658. cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
  659. cc_gc_shader_pipe_config |=
  660. INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
  661. cc_gc_shader_pipe_config |=
  662. INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
  663. if (rdev->family == CHIP_RV740)
  664. backend_map = 0x28;
  665. else
  666. backend_map = r700_get_tile_pipe_to_backend_map(rdev,
  667. rdev->config.rv770.max_tile_pipes,
  668. (R7XX_MAX_BACKENDS -
  669. r600_count_pipe_bits((cc_rb_backend_disable &
  670. R7XX_MAX_BACKENDS_MASK) >> 16)),
  671. (cc_rb_backend_disable >> 16));
  672. rdev->config.rv770.tile_config = gb_tiling_config;
  673. gb_tiling_config |= BACKEND_MAP(backend_map);
  674. WREG32(GB_TILING_CONFIG, gb_tiling_config);
  675. WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
  676. WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
  677. WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
  678. WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
  679. WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
  680. WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
  681. WREG32(CGTS_SYS_TCC_DISABLE, 0);
  682. WREG32(CGTS_TCC_DISABLE, 0);
  683. WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
  684. WREG32(CGTS_USER_TCC_DISABLE, 0);
  685. num_qd_pipes =
  686. R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
  687. WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
  688. WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
  689. /* set HW defaults for 3D engine */
  690. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
  691. ROQ_IB2_START(0x2b)));
  692. WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
  693. ta_aux_cntl = RREG32(TA_CNTL_AUX);
  694. WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
  695. sx_debug_1 = RREG32(SX_DEBUG_1);
  696. sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
  697. WREG32(SX_DEBUG_1, sx_debug_1);
  698. smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
  699. smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
  700. smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
  701. WREG32(SMX_DC_CTL0, smx_dc_ctl0);
  702. if (rdev->family != CHIP_RV740)
  703. WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
  704. GS_FLUSH_CTL(4) |
  705. ACK_FLUSH_CTL(3) |
  706. SYNC_FLUSH_CTL));
  707. db_debug3 = RREG32(DB_DEBUG3);
  708. db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
  709. switch (rdev->family) {
  710. case CHIP_RV770:
  711. case CHIP_RV740:
  712. db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
  713. break;
  714. case CHIP_RV710:
  715. case CHIP_RV730:
  716. default:
  717. db_debug3 |= DB_CLK_OFF_DELAY(2);
  718. break;
  719. }
  720. WREG32(DB_DEBUG3, db_debug3);
  721. if (rdev->family != CHIP_RV770) {
  722. db_debug4 = RREG32(DB_DEBUG4);
  723. db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
  724. WREG32(DB_DEBUG4, db_debug4);
  725. }
  726. WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
  727. POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
  728. SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
  729. WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
  730. SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
  731. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
  732. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  733. WREG32(VGT_NUM_INSTANCES, 1);
  734. WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
  735. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
  736. WREG32(CP_PERFMON_CNTL, 0);
  737. sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
  738. DONE_FIFO_HIWATER(0xe0) |
  739. ALU_UPDATE_FIFO_HIWATER(0x8));
  740. switch (rdev->family) {
  741. case CHIP_RV770:
  742. case CHIP_RV730:
  743. case CHIP_RV710:
  744. sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
  745. break;
  746. case CHIP_RV740:
  747. default:
  748. sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
  749. break;
  750. }
  751. WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
  752. /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
  753. * should be adjusted as needed by the 2D/3D drivers. This just sets default values
  754. */
  755. sq_config = RREG32(SQ_CONFIG);
  756. sq_config &= ~(PS_PRIO(3) |
  757. VS_PRIO(3) |
  758. GS_PRIO(3) |
  759. ES_PRIO(3));
  760. sq_config |= (DX9_CONSTS |
  761. VC_ENABLE |
  762. EXPORT_SRC_C |
  763. PS_PRIO(0) |
  764. VS_PRIO(1) |
  765. GS_PRIO(2) |
  766. ES_PRIO(3));
  767. if (rdev->family == CHIP_RV710)
  768. /* no vertex cache */
  769. sq_config &= ~VC_ENABLE;
  770. WREG32(SQ_CONFIG, sq_config);
  771. WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
  772. NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
  773. NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
  774. WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
  775. NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
  776. sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
  777. NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
  778. NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
  779. if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
  780. sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
  781. else
  782. sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
  783. WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
  784. WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
  785. NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
  786. WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
  787. NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
  788. sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
  789. SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
  790. SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
  791. SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
  792. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
  793. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
  794. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
  795. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
  796. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
  797. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
  798. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
  799. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
  800. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  801. FORCE_EOV_MAX_REZ_CNT(255)));
  802. if (rdev->family == CHIP_RV710)
  803. WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
  804. AUTO_INVLD_EN(ES_AND_GS_AUTO)));
  805. else
  806. WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
  807. AUTO_INVLD_EN(ES_AND_GS_AUTO)));
  808. switch (rdev->family) {
  809. case CHIP_RV770:
  810. case CHIP_RV730:
  811. case CHIP_RV740:
  812. gs_prim_buffer_depth = 384;
  813. break;
  814. case CHIP_RV710:
  815. gs_prim_buffer_depth = 128;
  816. break;
  817. default:
  818. break;
  819. }
  820. num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
  821. vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
  822. /* Max value for this is 256 */
  823. if (vgt_gs_per_es > 256)
  824. vgt_gs_per_es = 256;
  825. WREG32(VGT_ES_PER_GS, 128);
  826. WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
  827. WREG32(VGT_GS_PER_VS, 2);
  828. /* more default values. 2D/3D driver should adjust as needed */
  829. WREG32(VGT_GS_VERTEX_REUSE, 16);
  830. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  831. WREG32(VGT_STRMOUT_EN, 0);
  832. WREG32(SX_MISC, 0);
  833. WREG32(PA_SC_MODE_CNTL, 0);
  834. WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
  835. WREG32(PA_SC_AA_CONFIG, 0);
  836. WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
  837. WREG32(PA_SC_LINE_STIPPLE, 0);
  838. WREG32(SPI_INPUT_Z, 0);
  839. WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
  840. WREG32(CB_COLOR7_FRAG, 0);
  841. /* clear render buffer base addresses */
  842. WREG32(CB_COLOR0_BASE, 0);
  843. WREG32(CB_COLOR1_BASE, 0);
  844. WREG32(CB_COLOR2_BASE, 0);
  845. WREG32(CB_COLOR3_BASE, 0);
  846. WREG32(CB_COLOR4_BASE, 0);
  847. WREG32(CB_COLOR5_BASE, 0);
  848. WREG32(CB_COLOR6_BASE, 0);
  849. WREG32(CB_COLOR7_BASE, 0);
  850. WREG32(TCP_CNTL, 0);
  851. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  852. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  853. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  854. WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
  855. NUM_CLIP_SEQ(3)));
  856. }
  857. static int rv770_vram_scratch_init(struct radeon_device *rdev)
  858. {
  859. int r;
  860. u64 gpu_addr;
  861. if (rdev->vram_scratch.robj == NULL) {
  862. r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
  863. PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  864. &rdev->vram_scratch.robj);
  865. if (r) {
  866. return r;
  867. }
  868. }
  869. r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
  870. if (unlikely(r != 0))
  871. return r;
  872. r = radeon_bo_pin(rdev->vram_scratch.robj,
  873. RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
  874. if (r) {
  875. radeon_bo_unreserve(rdev->vram_scratch.robj);
  876. return r;
  877. }
  878. r = radeon_bo_kmap(rdev->vram_scratch.robj,
  879. (void **)&rdev->vram_scratch.ptr);
  880. if (r)
  881. radeon_bo_unpin(rdev->vram_scratch.robj);
  882. radeon_bo_unreserve(rdev->vram_scratch.robj);
  883. return r;
  884. }
  885. static void rv770_vram_scratch_fini(struct radeon_device *rdev)
  886. {
  887. int r;
  888. if (rdev->vram_scratch.robj == NULL) {
  889. return;
  890. }
  891. r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
  892. if (likely(r == 0)) {
  893. radeon_bo_kunmap(rdev->vram_scratch.robj);
  894. radeon_bo_unpin(rdev->vram_scratch.robj);
  895. radeon_bo_unreserve(rdev->vram_scratch.robj);
  896. }
  897. radeon_bo_unref(&rdev->vram_scratch.robj);
  898. }
  899. void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
  900. {
  901. u64 size_bf, size_af;
  902. if (mc->mc_vram_size > 0xE0000000) {
  903. /* leave room for at least 512M GTT */
  904. dev_warn(rdev->dev, "limiting VRAM\n");
  905. mc->real_vram_size = 0xE0000000;
  906. mc->mc_vram_size = 0xE0000000;
  907. }
  908. if (rdev->flags & RADEON_IS_AGP) {
  909. size_bf = mc->gtt_start;
  910. size_af = 0xFFFFFFFF - mc->gtt_end + 1;
  911. if (size_bf > size_af) {
  912. if (mc->mc_vram_size > size_bf) {
  913. dev_warn(rdev->dev, "limiting VRAM\n");
  914. mc->real_vram_size = size_bf;
  915. mc->mc_vram_size = size_bf;
  916. }
  917. mc->vram_start = mc->gtt_start - mc->mc_vram_size;
  918. } else {
  919. if (mc->mc_vram_size > size_af) {
  920. dev_warn(rdev->dev, "limiting VRAM\n");
  921. mc->real_vram_size = size_af;
  922. mc->mc_vram_size = size_af;
  923. }
  924. mc->vram_start = mc->gtt_end;
  925. }
  926. mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
  927. dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
  928. mc->mc_vram_size >> 20, mc->vram_start,
  929. mc->vram_end, mc->real_vram_size >> 20);
  930. } else {
  931. radeon_vram_location(rdev, &rdev->mc, 0);
  932. rdev->mc.gtt_base_align = 0;
  933. radeon_gtt_location(rdev, mc);
  934. }
  935. }
  936. int rv770_mc_init(struct radeon_device *rdev)
  937. {
  938. u32 tmp;
  939. int chansize, numchan;
  940. /* Get VRAM informations */
  941. rdev->mc.vram_is_ddr = true;
  942. tmp = RREG32(MC_ARB_RAMCFG);
  943. if (tmp & CHANSIZE_OVERRIDE) {
  944. chansize = 16;
  945. } else if (tmp & CHANSIZE_MASK) {
  946. chansize = 64;
  947. } else {
  948. chansize = 32;
  949. }
  950. tmp = RREG32(MC_SHARED_CHMAP);
  951. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  952. case 0:
  953. default:
  954. numchan = 1;
  955. break;
  956. case 1:
  957. numchan = 2;
  958. break;
  959. case 2:
  960. numchan = 4;
  961. break;
  962. case 3:
  963. numchan = 8;
  964. break;
  965. }
  966. rdev->mc.vram_width = numchan * chansize;
  967. /* Could aper size report 0 ? */
  968. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  969. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  970. /* Setup GPU memory space */
  971. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
  972. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
  973. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  974. r700_vram_gtt_location(rdev, &rdev->mc);
  975. radeon_update_bandwidth_info(rdev);
  976. return 0;
  977. }
  978. static int rv770_startup(struct radeon_device *rdev)
  979. {
  980. int r;
  981. /* enable pcie gen2 link */
  982. rv770_pcie_gen2_enable(rdev);
  983. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  984. r = r600_init_microcode(rdev);
  985. if (r) {
  986. DRM_ERROR("Failed to load firmware!\n");
  987. return r;
  988. }
  989. }
  990. rv770_mc_program(rdev);
  991. if (rdev->flags & RADEON_IS_AGP) {
  992. rv770_agp_enable(rdev);
  993. } else {
  994. r = rv770_pcie_gart_enable(rdev);
  995. if (r)
  996. return r;
  997. }
  998. r = rv770_vram_scratch_init(rdev);
  999. if (r)
  1000. return r;
  1001. rv770_gpu_init(rdev);
  1002. r = r600_blit_init(rdev);
  1003. if (r) {
  1004. r600_blit_fini(rdev);
  1005. rdev->asic->copy = NULL;
  1006. dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
  1007. }
  1008. /* allocate wb buffer */
  1009. r = radeon_wb_init(rdev);
  1010. if (r)
  1011. return r;
  1012. /* Enable IRQ */
  1013. r = r600_irq_init(rdev);
  1014. if (r) {
  1015. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  1016. radeon_irq_kms_fini(rdev);
  1017. return r;
  1018. }
  1019. r600_irq_set(rdev);
  1020. r = radeon_ring_init(rdev, rdev->cp.ring_size);
  1021. if (r)
  1022. return r;
  1023. r = rv770_cp_load_microcode(rdev);
  1024. if (r)
  1025. return r;
  1026. r = r600_cp_resume(rdev);
  1027. if (r)
  1028. return r;
  1029. return 0;
  1030. }
  1031. int rv770_resume(struct radeon_device *rdev)
  1032. {
  1033. int r;
  1034. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  1035. * posting will perform necessary task to bring back GPU into good
  1036. * shape.
  1037. */
  1038. /* post card */
  1039. atom_asic_init(rdev->mode_info.atom_context);
  1040. r = rv770_startup(rdev);
  1041. if (r) {
  1042. DRM_ERROR("r600 startup failed on resume\n");
  1043. return r;
  1044. }
  1045. r = r600_ib_test(rdev);
  1046. if (r) {
  1047. DRM_ERROR("radeon: failed testing IB (%d).\n", r);
  1048. return r;
  1049. }
  1050. r = r600_audio_init(rdev);
  1051. if (r) {
  1052. dev_err(rdev->dev, "radeon: audio init failed\n");
  1053. return r;
  1054. }
  1055. return r;
  1056. }
  1057. int rv770_suspend(struct radeon_device *rdev)
  1058. {
  1059. int r;
  1060. r600_audio_fini(rdev);
  1061. /* FIXME: we should wait for ring to be empty */
  1062. r700_cp_stop(rdev);
  1063. rdev->cp.ready = false;
  1064. r600_irq_suspend(rdev);
  1065. radeon_wb_disable(rdev);
  1066. rv770_pcie_gart_disable(rdev);
  1067. /* unpin shaders bo */
  1068. if (rdev->r600_blit.shader_obj) {
  1069. r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
  1070. if (likely(r == 0)) {
  1071. radeon_bo_unpin(rdev->r600_blit.shader_obj);
  1072. radeon_bo_unreserve(rdev->r600_blit.shader_obj);
  1073. }
  1074. }
  1075. return 0;
  1076. }
  1077. /* Plan is to move initialization in that function and use
  1078. * helper function so that radeon_device_init pretty much
  1079. * do nothing more than calling asic specific function. This
  1080. * should also allow to remove a bunch of callback function
  1081. * like vram_info.
  1082. */
  1083. int rv770_init(struct radeon_device *rdev)
  1084. {
  1085. int r;
  1086. /* This don't do much */
  1087. r = radeon_gem_init(rdev);
  1088. if (r)
  1089. return r;
  1090. /* Read BIOS */
  1091. if (!radeon_get_bios(rdev)) {
  1092. if (ASIC_IS_AVIVO(rdev))
  1093. return -EINVAL;
  1094. }
  1095. /* Must be an ATOMBIOS */
  1096. if (!rdev->is_atom_bios) {
  1097. dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
  1098. return -EINVAL;
  1099. }
  1100. r = radeon_atombios_init(rdev);
  1101. if (r)
  1102. return r;
  1103. /* Post card if necessary */
  1104. if (!radeon_card_posted(rdev)) {
  1105. if (!rdev->bios) {
  1106. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  1107. return -EINVAL;
  1108. }
  1109. DRM_INFO("GPU not posted. posting now...\n");
  1110. atom_asic_init(rdev->mode_info.atom_context);
  1111. }
  1112. /* Initialize scratch registers */
  1113. r600_scratch_init(rdev);
  1114. /* Initialize surface registers */
  1115. radeon_surface_init(rdev);
  1116. /* Initialize clocks */
  1117. radeon_get_clock_info(rdev->ddev);
  1118. /* Fence driver */
  1119. r = radeon_fence_driver_init(rdev);
  1120. if (r)
  1121. return r;
  1122. /* initialize AGP */
  1123. if (rdev->flags & RADEON_IS_AGP) {
  1124. r = radeon_agp_init(rdev);
  1125. if (r)
  1126. radeon_agp_disable(rdev);
  1127. }
  1128. r = rv770_mc_init(rdev);
  1129. if (r)
  1130. return r;
  1131. /* Memory manager */
  1132. r = radeon_bo_init(rdev);
  1133. if (r)
  1134. return r;
  1135. r = radeon_irq_kms_init(rdev);
  1136. if (r)
  1137. return r;
  1138. rdev->cp.ring_obj = NULL;
  1139. r600_ring_init(rdev, 1024 * 1024);
  1140. rdev->ih.ring_obj = NULL;
  1141. r600_ih_ring_init(rdev, 64 * 1024);
  1142. r = r600_pcie_gart_init(rdev);
  1143. if (r)
  1144. return r;
  1145. rdev->accel_working = true;
  1146. r = rv770_startup(rdev);
  1147. if (r) {
  1148. dev_err(rdev->dev, "disabling GPU acceleration\n");
  1149. r700_cp_fini(rdev);
  1150. r600_irq_fini(rdev);
  1151. radeon_wb_fini(rdev);
  1152. radeon_irq_kms_fini(rdev);
  1153. rv770_pcie_gart_fini(rdev);
  1154. rdev->accel_working = false;
  1155. }
  1156. if (rdev->accel_working) {
  1157. r = radeon_ib_pool_init(rdev);
  1158. if (r) {
  1159. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  1160. rdev->accel_working = false;
  1161. } else {
  1162. r = r600_ib_test(rdev);
  1163. if (r) {
  1164. dev_err(rdev->dev, "IB test failed (%d).\n", r);
  1165. rdev->accel_working = false;
  1166. }
  1167. }
  1168. }
  1169. r = r600_audio_init(rdev);
  1170. if (r) {
  1171. dev_err(rdev->dev, "radeon: audio init failed\n");
  1172. return r;
  1173. }
  1174. return 0;
  1175. }
  1176. void rv770_fini(struct radeon_device *rdev)
  1177. {
  1178. r600_blit_fini(rdev);
  1179. r700_cp_fini(rdev);
  1180. r600_irq_fini(rdev);
  1181. radeon_wb_fini(rdev);
  1182. radeon_ib_pool_fini(rdev);
  1183. radeon_irq_kms_fini(rdev);
  1184. rv770_pcie_gart_fini(rdev);
  1185. rv770_vram_scratch_fini(rdev);
  1186. radeon_gem_fini(rdev);
  1187. radeon_fence_driver_fini(rdev);
  1188. radeon_agp_fini(rdev);
  1189. radeon_bo_fini(rdev);
  1190. radeon_atombios_fini(rdev);
  1191. kfree(rdev->bios);
  1192. rdev->bios = NULL;
  1193. }
  1194. static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
  1195. {
  1196. u32 link_width_cntl, lanes, speed_cntl, tmp;
  1197. u16 link_cntl2;
  1198. if (radeon_pcie_gen2 == 0)
  1199. return;
  1200. if (rdev->flags & RADEON_IS_IGP)
  1201. return;
  1202. if (!(rdev->flags & RADEON_IS_PCIE))
  1203. return;
  1204. /* x2 cards have a special sequence */
  1205. if (ASIC_IS_X2(rdev))
  1206. return;
  1207. /* advertise upconfig capability */
  1208. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  1209. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  1210. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1211. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  1212. if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
  1213. lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
  1214. link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
  1215. LC_RECONFIG_ARC_MISSING_ESCAPE);
  1216. link_width_cntl |= lanes | LC_RECONFIG_NOW |
  1217. LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
  1218. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1219. } else {
  1220. link_width_cntl |= LC_UPCONFIGURE_DIS;
  1221. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1222. }
  1223. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  1224. if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  1225. (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  1226. tmp = RREG32(0x541c);
  1227. WREG32(0x541c, tmp | 0x8);
  1228. WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
  1229. link_cntl2 = RREG16(0x4088);
  1230. link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
  1231. link_cntl2 |= 0x2;
  1232. WREG16(0x4088, link_cntl2);
  1233. WREG32(MM_CFGREGS_CNTL, 0);
  1234. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  1235. speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
  1236. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  1237. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  1238. speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
  1239. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  1240. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  1241. speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
  1242. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  1243. speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
  1244. speed_cntl |= LC_GEN2_EN_STRAP;
  1245. WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
  1246. } else {
  1247. link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
  1248. /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
  1249. if (1)
  1250. link_width_cntl |= LC_UPCONFIGURE_DIS;
  1251. else
  1252. link_width_cntl &= ~LC_UPCONFIGURE_DIS;
  1253. WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  1254. }
  1255. }