/drivers/gpu/drm/radeon/rv770.c
C | 1411 lines | 1150 code | 156 blank | 105 comment | 166 complexity | 2775a69712dece8ef9fc593f042b295b MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/firmware.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include "drmP.h"
32#include "radeon.h"
33#include "radeon_asic.h"
34#include "radeon_drm.h"
35#include "rv770d.h"
36#include "atom.h"
37#include "avivod.h"
38
39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
41
42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45
46u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
47{
48 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
49 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
50 int i;
51
52 /* Lock the graphics update lock */
53 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
54 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
55
56 /* update the scanout addresses */
57 if (radeon_crtc->crtc_id) {
58 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
59 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
60 } else {
61 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
62 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
63 }
64 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
65 (u32)crtc_base);
66 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
67 (u32)crtc_base);
68
69 /* Wait for update_pending to go high. */
70 for (i = 0; i < rdev->usec_timeout; i++) {
71 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
72 break;
73 udelay(1);
74 }
75 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
76
77 /* Unlock the lock, so double-buffering can take place inside vblank */
78 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
79 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
80
81 /* Return current update_pending status: */
82 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
83}
84
85/* get temperature in millidegrees */
86int rv770_get_temp(struct radeon_device *rdev)
87{
88 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
89 ASIC_T_SHIFT;
90 int actual_temp;
91
92 if (temp & 0x400)
93 actual_temp = -256;
94 else if (temp & 0x200)
95 actual_temp = 255;
96 else if (temp & 0x100) {
97 actual_temp = temp & 0x1ff;
98 actual_temp |= ~0x1ff;
99 } else
100 actual_temp = temp & 0xff;
101
102 return (actual_temp * 1000) / 2;
103}
104
105void rv770_pm_misc(struct radeon_device *rdev)
106{
107 int req_ps_idx = rdev->pm.requested_power_state_index;
108 int req_cm_idx = rdev->pm.requested_clock_mode_index;
109 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
110 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
111
112 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
113 /* 0xff01 is a flag rather then an actual voltage */
114 if (voltage->voltage == 0xff01)
115 return;
116 if (voltage->voltage != rdev->pm.current_vddc) {
117 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
118 rdev->pm.current_vddc = voltage->voltage;
119 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
120 }
121 }
122}
123
124/*
125 * GART
126 */
127int rv770_pcie_gart_enable(struct radeon_device *rdev)
128{
129 u32 tmp;
130 int r, i;
131
132 if (rdev->gart.table.vram.robj == NULL) {
133 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
134 return -EINVAL;
135 }
136 r = radeon_gart_table_vram_pin(rdev);
137 if (r)
138 return r;
139 radeon_gart_restore(rdev);
140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
154 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
155 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
156 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
158 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
159 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
160 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
161 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
162 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
163 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
164 (u32)(rdev->dummy_page.addr >> 12));
165 for (i = 1; i < 7; i++)
166 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
167
168 r600_pcie_gart_tlb_flush(rdev);
169 rdev->gart.ready = true;
170 return 0;
171}
172
173void rv770_pcie_gart_disable(struct radeon_device *rdev)
174{
175 u32 tmp;
176 int i, r;
177
178 /* Disable all tables */
179 for (i = 0; i < 7; i++)
180 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
181
182 /* Setup L2 cache */
183 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
184 EFFECTIVE_L2_QUEUE_SIZE(7));
185 WREG32(VM_L2_CNTL2, 0);
186 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
187 /* Setup TLB control */
188 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
189 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
190 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
191 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
192 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
193 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
194 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
195 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
196 if (rdev->gart.table.vram.robj) {
197 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
198 if (likely(r == 0)) {
199 radeon_bo_kunmap(rdev->gart.table.vram.robj);
200 radeon_bo_unpin(rdev->gart.table.vram.robj);
201 radeon_bo_unreserve(rdev->gart.table.vram.robj);
202 }
203 }
204}
205
206void rv770_pcie_gart_fini(struct radeon_device *rdev)
207{
208 radeon_gart_fini(rdev);
209 rv770_pcie_gart_disable(rdev);
210 radeon_gart_table_vram_free(rdev);
211}
212
213
214void rv770_agp_enable(struct radeon_device *rdev)
215{
216 u32 tmp;
217 int i;
218
219 /* Setup L2 cache */
220 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
221 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
222 EFFECTIVE_L2_QUEUE_SIZE(7));
223 WREG32(VM_L2_CNTL2, 0);
224 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
225 /* Setup TLB control */
226 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
227 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
228 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
229 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
230 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
231 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
232 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
233 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
234 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
235 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
236 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
237 for (i = 0; i < 7; i++)
238 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
239}
240
241static void rv770_mc_program(struct radeon_device *rdev)
242{
243 struct rv515_mc_save save;
244 u32 tmp;
245 int i, j;
246
247 /* Initialize HDP */
248 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
249 WREG32((0x2c14 + j), 0x00000000);
250 WREG32((0x2c18 + j), 0x00000000);
251 WREG32((0x2c1c + j), 0x00000000);
252 WREG32((0x2c20 + j), 0x00000000);
253 WREG32((0x2c24 + j), 0x00000000);
254 }
255 /* r7xx hw bug. Read from HDP_DEBUG1 rather
256 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
257 */
258 tmp = RREG32(HDP_DEBUG1);
259
260 rv515_mc_stop(rdev, &save);
261 if (r600_mc_wait_for_idle(rdev)) {
262 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
263 }
264 /* Lockout access through VGA aperture*/
265 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
266 /* Update configuration */
267 if (rdev->flags & RADEON_IS_AGP) {
268 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
269 /* VRAM before AGP */
270 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
271 rdev->mc.vram_start >> 12);
272 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
273 rdev->mc.gtt_end >> 12);
274 } else {
275 /* VRAM after AGP */
276 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
277 rdev->mc.gtt_start >> 12);
278 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
279 rdev->mc.vram_end >> 12);
280 }
281 } else {
282 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
283 rdev->mc.vram_start >> 12);
284 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
285 rdev->mc.vram_end >> 12);
286 }
287 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
288 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
289 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
290 WREG32(MC_VM_FB_LOCATION, tmp);
291 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
292 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
293 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
294 if (rdev->flags & RADEON_IS_AGP) {
295 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
296 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
297 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
298 } else {
299 WREG32(MC_VM_AGP_BASE, 0);
300 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
301 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
302 }
303 if (r600_mc_wait_for_idle(rdev)) {
304 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
305 }
306 rv515_mc_resume(rdev, &save);
307 /* we need to own VRAM, so turn off the VGA renderer here
308 * to stop it overwriting our objects */
309 rv515_vga_render_disable(rdev);
310}
311
312
313/*
314 * CP.
315 */
316void r700_cp_stop(struct radeon_device *rdev)
317{
318 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
319 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
320 WREG32(SCRATCH_UMSK, 0);
321}
322
323static int rv770_cp_load_microcode(struct radeon_device *rdev)
324{
325 const __be32 *fw_data;
326 int i;
327
328 if (!rdev->me_fw || !rdev->pfp_fw)
329 return -EINVAL;
330
331 r700_cp_stop(rdev);
332 WREG32(CP_RB_CNTL,
333#ifdef __BIG_ENDIAN
334 BUF_SWAP_32BIT |
335#endif
336 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
337
338 /* Reset cp */
339 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
340 RREG32(GRBM_SOFT_RESET);
341 mdelay(15);
342 WREG32(GRBM_SOFT_RESET, 0);
343
344 fw_data = (const __be32 *)rdev->pfp_fw->data;
345 WREG32(CP_PFP_UCODE_ADDR, 0);
346 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
347 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
348 WREG32(CP_PFP_UCODE_ADDR, 0);
349
350 fw_data = (const __be32 *)rdev->me_fw->data;
351 WREG32(CP_ME_RAM_WADDR, 0);
352 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
353 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
354
355 WREG32(CP_PFP_UCODE_ADDR, 0);
356 WREG32(CP_ME_RAM_WADDR, 0);
357 WREG32(CP_ME_RAM_RADDR, 0);
358 return 0;
359}
360
361void r700_cp_fini(struct radeon_device *rdev)
362{
363 r700_cp_stop(rdev);
364 radeon_ring_fini(rdev);
365}
366
367/*
368 * Core functions
369 */
370static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
371 u32 num_tile_pipes,
372 u32 num_backends,
373 u32 backend_disable_mask)
374{
375 u32 backend_map = 0;
376 u32 enabled_backends_mask;
377 u32 enabled_backends_count;
378 u32 cur_pipe;
379 u32 swizzle_pipe[R7XX_MAX_PIPES];
380 u32 cur_backend;
381 u32 i;
382 bool force_no_swizzle;
383
384 if (num_tile_pipes > R7XX_MAX_PIPES)
385 num_tile_pipes = R7XX_MAX_PIPES;
386 if (num_tile_pipes < 1)
387 num_tile_pipes = 1;
388 if (num_backends > R7XX_MAX_BACKENDS)
389 num_backends = R7XX_MAX_BACKENDS;
390 if (num_backends < 1)
391 num_backends = 1;
392
393 enabled_backends_mask = 0;
394 enabled_backends_count = 0;
395 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
396 if (((backend_disable_mask >> i) & 1) == 0) {
397 enabled_backends_mask |= (1 << i);
398 ++enabled_backends_count;
399 }
400 if (enabled_backends_count == num_backends)
401 break;
402 }
403
404 if (enabled_backends_count == 0) {
405 enabled_backends_mask = 1;
406 enabled_backends_count = 1;
407 }
408
409 if (enabled_backends_count != num_backends)
410 num_backends = enabled_backends_count;
411
412 switch (rdev->family) {
413 case CHIP_RV770:
414 case CHIP_RV730:
415 force_no_swizzle = false;
416 break;
417 case CHIP_RV710:
418 case CHIP_RV740:
419 default:
420 force_no_swizzle = true;
421 break;
422 }
423
424 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
425 switch (num_tile_pipes) {
426 case 1:
427 swizzle_pipe[0] = 0;
428 break;
429 case 2:
430 swizzle_pipe[0] = 0;
431 swizzle_pipe[1] = 1;
432 break;
433 case 3:
434 if (force_no_swizzle) {
435 swizzle_pipe[0] = 0;
436 swizzle_pipe[1] = 1;
437 swizzle_pipe[2] = 2;
438 } else {
439 swizzle_pipe[0] = 0;
440 swizzle_pipe[1] = 2;
441 swizzle_pipe[2] = 1;
442 }
443 break;
444 case 4:
445 if (force_no_swizzle) {
446 swizzle_pipe[0] = 0;
447 swizzle_pipe[1] = 1;
448 swizzle_pipe[2] = 2;
449 swizzle_pipe[3] = 3;
450 } else {
451 swizzle_pipe[0] = 0;
452 swizzle_pipe[1] = 2;
453 swizzle_pipe[2] = 3;
454 swizzle_pipe[3] = 1;
455 }
456 break;
457 case 5:
458 if (force_no_swizzle) {
459 swizzle_pipe[0] = 0;
460 swizzle_pipe[1] = 1;
461 swizzle_pipe[2] = 2;
462 swizzle_pipe[3] = 3;
463 swizzle_pipe[4] = 4;
464 } else {
465 swizzle_pipe[0] = 0;
466 swizzle_pipe[1] = 2;
467 swizzle_pipe[2] = 4;
468 swizzle_pipe[3] = 1;
469 swizzle_pipe[4] = 3;
470 }
471 break;
472 case 6:
473 if (force_no_swizzle) {
474 swizzle_pipe[0] = 0;
475 swizzle_pipe[1] = 1;
476 swizzle_pipe[2] = 2;
477 swizzle_pipe[3] = 3;
478 swizzle_pipe[4] = 4;
479 swizzle_pipe[5] = 5;
480 } else {
481 swizzle_pipe[0] = 0;
482 swizzle_pipe[1] = 2;
483 swizzle_pipe[2] = 4;
484 swizzle_pipe[3] = 5;
485 swizzle_pipe[4] = 3;
486 swizzle_pipe[5] = 1;
487 }
488 break;
489 case 7:
490 if (force_no_swizzle) {
491 swizzle_pipe[0] = 0;
492 swizzle_pipe[1] = 1;
493 swizzle_pipe[2] = 2;
494 swizzle_pipe[3] = 3;
495 swizzle_pipe[4] = 4;
496 swizzle_pipe[5] = 5;
497 swizzle_pipe[6] = 6;
498 } else {
499 swizzle_pipe[0] = 0;
500 swizzle_pipe[1] = 2;
501 swizzle_pipe[2] = 4;
502 swizzle_pipe[3] = 6;
503 swizzle_pipe[4] = 3;
504 swizzle_pipe[5] = 1;
505 swizzle_pipe[6] = 5;
506 }
507 break;
508 case 8:
509 if (force_no_swizzle) {
510 swizzle_pipe[0] = 0;
511 swizzle_pipe[1] = 1;
512 swizzle_pipe[2] = 2;
513 swizzle_pipe[3] = 3;
514 swizzle_pipe[4] = 4;
515 swizzle_pipe[5] = 5;
516 swizzle_pipe[6] = 6;
517 swizzle_pipe[7] = 7;
518 } else {
519 swizzle_pipe[0] = 0;
520 swizzle_pipe[1] = 2;
521 swizzle_pipe[2] = 4;
522 swizzle_pipe[3] = 6;
523 swizzle_pipe[4] = 3;
524 swizzle_pipe[5] = 1;
525 swizzle_pipe[6] = 7;
526 swizzle_pipe[7] = 5;
527 }
528 break;
529 }
530
531 cur_backend = 0;
532 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
533 while (((1 << cur_backend) & enabled_backends_mask) == 0)
534 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
535
536 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
537
538 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
539 }
540
541 return backend_map;
542}
543
544static void rv770_gpu_init(struct radeon_device *rdev)
545{
546 int i, j, num_qd_pipes;
547 u32 ta_aux_cntl;
548 u32 sx_debug_1;
549 u32 smx_dc_ctl0;
550 u32 db_debug3;
551 u32 num_gs_verts_per_thread;
552 u32 vgt_gs_per_es;
553 u32 gs_prim_buffer_depth = 0;
554 u32 sq_ms_fifo_sizes;
555 u32 sq_config;
556 u32 sq_thread_resource_mgmt;
557 u32 hdp_host_path_cntl;
558 u32 sq_dyn_gpr_size_simd_ab_0;
559 u32 backend_map;
560 u32 gb_tiling_config = 0;
561 u32 cc_rb_backend_disable = 0;
562 u32 cc_gc_shader_pipe_config = 0;
563 u32 mc_arb_ramcfg;
564 u32 db_debug4;
565
566 /* setup chip specs */
567 switch (rdev->family) {
568 case CHIP_RV770:
569 rdev->config.rv770.max_pipes = 4;
570 rdev->config.rv770.max_tile_pipes = 8;
571 rdev->config.rv770.max_simds = 10;
572 rdev->config.rv770.max_backends = 4;
573 rdev->config.rv770.max_gprs = 256;
574 rdev->config.rv770.max_threads = 248;
575 rdev->config.rv770.max_stack_entries = 512;
576 rdev->config.rv770.max_hw_contexts = 8;
577 rdev->config.rv770.max_gs_threads = 16 * 2;
578 rdev->config.rv770.sx_max_export_size = 128;
579 rdev->config.rv770.sx_max_export_pos_size = 16;
580 rdev->config.rv770.sx_max_export_smx_size = 112;
581 rdev->config.rv770.sq_num_cf_insts = 2;
582
583 rdev->config.rv770.sx_num_of_sets = 7;
584 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
585 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
586 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
587 break;
588 case CHIP_RV730:
589 rdev->config.rv770.max_pipes = 2;
590 rdev->config.rv770.max_tile_pipes = 4;
591 rdev->config.rv770.max_simds = 8;
592 rdev->config.rv770.max_backends = 2;
593 rdev->config.rv770.max_gprs = 128;
594 rdev->config.rv770.max_threads = 248;
595 rdev->config.rv770.max_stack_entries = 256;
596 rdev->config.rv770.max_hw_contexts = 8;
597 rdev->config.rv770.max_gs_threads = 16 * 2;
598 rdev->config.rv770.sx_max_export_size = 256;
599 rdev->config.rv770.sx_max_export_pos_size = 32;
600 rdev->config.rv770.sx_max_export_smx_size = 224;
601 rdev->config.rv770.sq_num_cf_insts = 2;
602
603 rdev->config.rv770.sx_num_of_sets = 7;
604 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
605 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
606 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
607 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
608 rdev->config.rv770.sx_max_export_pos_size -= 16;
609 rdev->config.rv770.sx_max_export_smx_size += 16;
610 }
611 break;
612 case CHIP_RV710:
613 rdev->config.rv770.max_pipes = 2;
614 rdev->config.rv770.max_tile_pipes = 2;
615 rdev->config.rv770.max_simds = 2;
616 rdev->config.rv770.max_backends = 1;
617 rdev->config.rv770.max_gprs = 256;
618 rdev->config.rv770.max_threads = 192;
619 rdev->config.rv770.max_stack_entries = 256;
620 rdev->config.rv770.max_hw_contexts = 4;
621 rdev->config.rv770.max_gs_threads = 8 * 2;
622 rdev->config.rv770.sx_max_export_size = 128;
623 rdev->config.rv770.sx_max_export_pos_size = 16;
624 rdev->config.rv770.sx_max_export_smx_size = 112;
625 rdev->config.rv770.sq_num_cf_insts = 1;
626
627 rdev->config.rv770.sx_num_of_sets = 7;
628 rdev->config.rv770.sc_prim_fifo_size = 0x40;
629 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
630 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
631 break;
632 case CHIP_RV740:
633 rdev->config.rv770.max_pipes = 4;
634 rdev->config.rv770.max_tile_pipes = 4;
635 rdev->config.rv770.max_simds = 8;
636 rdev->config.rv770.max_backends = 4;
637 rdev->config.rv770.max_gprs = 256;
638 rdev->config.rv770.max_threads = 248;
639 rdev->config.rv770.max_stack_entries = 512;
640 rdev->config.rv770.max_hw_contexts = 8;
641 rdev->config.rv770.max_gs_threads = 16 * 2;
642 rdev->config.rv770.sx_max_export_size = 256;
643 rdev->config.rv770.sx_max_export_pos_size = 32;
644 rdev->config.rv770.sx_max_export_smx_size = 224;
645 rdev->config.rv770.sq_num_cf_insts = 2;
646
647 rdev->config.rv770.sx_num_of_sets = 7;
648 rdev->config.rv770.sc_prim_fifo_size = 0x100;
649 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
650 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
651
652 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
653 rdev->config.rv770.sx_max_export_pos_size -= 16;
654 rdev->config.rv770.sx_max_export_smx_size += 16;
655 }
656 break;
657 default:
658 break;
659 }
660
661 /* Initialize HDP */
662 j = 0;
663 for (i = 0; i < 32; i++) {
664 WREG32((0x2c14 + j), 0x00000000);
665 WREG32((0x2c18 + j), 0x00000000);
666 WREG32((0x2c1c + j), 0x00000000);
667 WREG32((0x2c20 + j), 0x00000000);
668 WREG32((0x2c24 + j), 0x00000000);
669 j += 0x18;
670 }
671
672 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
673
674 /* setup tiling, simd, pipe config */
675 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
676
677 switch (rdev->config.rv770.max_tile_pipes) {
678 case 1:
679 default:
680 gb_tiling_config |= PIPE_TILING(0);
681 break;
682 case 2:
683 gb_tiling_config |= PIPE_TILING(1);
684 break;
685 case 4:
686 gb_tiling_config |= PIPE_TILING(2);
687 break;
688 case 8:
689 gb_tiling_config |= PIPE_TILING(3);
690 break;
691 }
692 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
693
694 if (rdev->family == CHIP_RV770)
695 gb_tiling_config |= BANK_TILING(1);
696 else
697 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
698 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
699 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
700 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
701 rdev->config.rv770.tiling_group_size = 512;
702 else
703 rdev->config.rv770.tiling_group_size = 256;
704 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
705 gb_tiling_config |= ROW_TILING(3);
706 gb_tiling_config |= SAMPLE_SPLIT(3);
707 } else {
708 gb_tiling_config |=
709 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
710 gb_tiling_config |=
711 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
712 }
713
714 gb_tiling_config |= BANK_SWAPS(1);
715
716 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
717 cc_rb_backend_disable |=
718 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
719
720 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
721 cc_gc_shader_pipe_config |=
722 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
723 cc_gc_shader_pipe_config |=
724 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
725
726 if (rdev->family == CHIP_RV740)
727 backend_map = 0x28;
728 else
729 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
730 rdev->config.rv770.max_tile_pipes,
731 (R7XX_MAX_BACKENDS -
732 r600_count_pipe_bits((cc_rb_backend_disable &
733 R7XX_MAX_BACKENDS_MASK) >> 16)),
734 (cc_rb_backend_disable >> 16));
735
736 rdev->config.rv770.tile_config = gb_tiling_config;
737 gb_tiling_config |= BACKEND_MAP(backend_map);
738
739 WREG32(GB_TILING_CONFIG, gb_tiling_config);
740 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
741 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
742
743 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
744 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
745 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
746 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
747
748 WREG32(CGTS_SYS_TCC_DISABLE, 0);
749 WREG32(CGTS_TCC_DISABLE, 0);
750 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
751 WREG32(CGTS_USER_TCC_DISABLE, 0);
752
753 num_qd_pipes =
754 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
755 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
756 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
757
758 /* set HW defaults for 3D engine */
759 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
760 ROQ_IB2_START(0x2b)));
761
762 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
763
764 ta_aux_cntl = RREG32(TA_CNTL_AUX);
765 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
766
767 sx_debug_1 = RREG32(SX_DEBUG_1);
768 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
769 WREG32(SX_DEBUG_1, sx_debug_1);
770
771 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
772 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
773 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
774 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
775
776 if (rdev->family != CHIP_RV740)
777 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
778 GS_FLUSH_CTL(4) |
779 ACK_FLUSH_CTL(3) |
780 SYNC_FLUSH_CTL));
781
782 db_debug3 = RREG32(DB_DEBUG3);
783 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
784 switch (rdev->family) {
785 case CHIP_RV770:
786 case CHIP_RV740:
787 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
788 break;
789 case CHIP_RV710:
790 case CHIP_RV730:
791 default:
792 db_debug3 |= DB_CLK_OFF_DELAY(2);
793 break;
794 }
795 WREG32(DB_DEBUG3, db_debug3);
796
797 if (rdev->family != CHIP_RV770) {
798 db_debug4 = RREG32(DB_DEBUG4);
799 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
800 WREG32(DB_DEBUG4, db_debug4);
801 }
802
803 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
804 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
805 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
806
807 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
808 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
809 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
810
811 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
812
813 WREG32(VGT_NUM_INSTANCES, 1);
814
815 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
816
817 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
818
819 WREG32(CP_PERFMON_CNTL, 0);
820
821 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
822 DONE_FIFO_HIWATER(0xe0) |
823 ALU_UPDATE_FIFO_HIWATER(0x8));
824 switch (rdev->family) {
825 case CHIP_RV770:
826 case CHIP_RV730:
827 case CHIP_RV710:
828 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
829 break;
830 case CHIP_RV740:
831 default:
832 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
833 break;
834 }
835 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
836
837 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
838 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
839 */
840 sq_config = RREG32(SQ_CONFIG);
841 sq_config &= ~(PS_PRIO(3) |
842 VS_PRIO(3) |
843 GS_PRIO(3) |
844 ES_PRIO(3));
845 sq_config |= (DX9_CONSTS |
846 VC_ENABLE |
847 EXPORT_SRC_C |
848 PS_PRIO(0) |
849 VS_PRIO(1) |
850 GS_PRIO(2) |
851 ES_PRIO(3));
852 if (rdev->family == CHIP_RV710)
853 /* no vertex cache */
854 sq_config &= ~VC_ENABLE;
855
856 WREG32(SQ_CONFIG, sq_config);
857
858 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
859 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
860 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
861
862 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
863 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
864
865 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
866 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
867 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
868 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
869 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
870 else
871 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
872 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
873
874 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
875 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
876
877 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
878 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
879
880 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
881 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
882 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
883 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
884
885 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
886 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
887 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
888 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
889 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
890 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
891 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
892 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
893
894 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
895 FORCE_EOV_MAX_REZ_CNT(255)));
896
897 if (rdev->family == CHIP_RV710)
898 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
899 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
900 else
901 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
902 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
903
904 switch (rdev->family) {
905 case CHIP_RV770:
906 case CHIP_RV730:
907 case CHIP_RV740:
908 gs_prim_buffer_depth = 384;
909 break;
910 case CHIP_RV710:
911 gs_prim_buffer_depth = 128;
912 break;
913 default:
914 break;
915 }
916
917 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
918 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
919 /* Max value for this is 256 */
920 if (vgt_gs_per_es > 256)
921 vgt_gs_per_es = 256;
922
923 WREG32(VGT_ES_PER_GS, 128);
924 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
925 WREG32(VGT_GS_PER_VS, 2);
926
927 /* more default values. 2D/3D driver should adjust as needed */
928 WREG32(VGT_GS_VERTEX_REUSE, 16);
929 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
930 WREG32(VGT_STRMOUT_EN, 0);
931 WREG32(SX_MISC, 0);
932 WREG32(PA_SC_MODE_CNTL, 0);
933 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
934 WREG32(PA_SC_AA_CONFIG, 0);
935 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
936 WREG32(PA_SC_LINE_STIPPLE, 0);
937 WREG32(SPI_INPUT_Z, 0);
938 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
939 WREG32(CB_COLOR7_FRAG, 0);
940
941 /* clear render buffer base addresses */
942 WREG32(CB_COLOR0_BASE, 0);
943 WREG32(CB_COLOR1_BASE, 0);
944 WREG32(CB_COLOR2_BASE, 0);
945 WREG32(CB_COLOR3_BASE, 0);
946 WREG32(CB_COLOR4_BASE, 0);
947 WREG32(CB_COLOR5_BASE, 0);
948 WREG32(CB_COLOR6_BASE, 0);
949 WREG32(CB_COLOR7_BASE, 0);
950
951 WREG32(TCP_CNTL, 0);
952
953 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
954 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
955
956 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
957
958 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
959 NUM_CLIP_SEQ(3)));
960
961}
962
963static int rv770_vram_scratch_init(struct radeon_device *rdev)
964{
965 int r;
966 u64 gpu_addr;
967
968 if (rdev->vram_scratch.robj == NULL) {
969 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
970 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
971 &rdev->vram_scratch.robj);
972 if (r) {
973 return r;
974 }
975 }
976
977 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
978 if (unlikely(r != 0))
979 return r;
980 r = radeon_bo_pin(rdev->vram_scratch.robj,
981 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
982 if (r) {
983 radeon_bo_unreserve(rdev->vram_scratch.robj);
984 return r;
985 }
986 r = radeon_bo_kmap(rdev->vram_scratch.robj,
987 (void **)&rdev->vram_scratch.ptr);
988 if (r)
989 radeon_bo_unpin(rdev->vram_scratch.robj);
990 radeon_bo_unreserve(rdev->vram_scratch.robj);
991
992 return r;
993}
994
995static void rv770_vram_scratch_fini(struct radeon_device *rdev)
996{
997 int r;
998
999 if (rdev->vram_scratch.robj == NULL) {
1000 return;
1001 }
1002 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1003 if (likely(r == 0)) {
1004 radeon_bo_kunmap(rdev->vram_scratch.robj);
1005 radeon_bo_unpin(rdev->vram_scratch.robj);
1006 radeon_bo_unreserve(rdev->vram_scratch.robj);
1007 }
1008 radeon_bo_unref(&rdev->vram_scratch.robj);
1009}
1010
1011void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1012{
1013 u64 size_bf, size_af;
1014
1015 if (mc->mc_vram_size > 0xE0000000) {
1016 /* leave room for at least 512M GTT */
1017 dev_warn(rdev->dev, "limiting VRAM\n");
1018 mc->real_vram_size = 0xE0000000;
1019 mc->mc_vram_size = 0xE0000000;
1020 }
1021 if (rdev->flags & RADEON_IS_AGP) {
1022 size_bf = mc->gtt_start;
1023 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1024 if (size_bf > size_af) {
1025 if (mc->mc_vram_size > size_bf) {
1026 dev_warn(rdev->dev, "limiting VRAM\n");
1027 mc->real_vram_size = size_bf;
1028 mc->mc_vram_size = size_bf;
1029 }
1030 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1031 } else {
1032 if (mc->mc_vram_size > size_af) {
1033 dev_warn(rdev->dev, "limiting VRAM\n");
1034 mc->real_vram_size = size_af;
1035 mc->mc_vram_size = size_af;
1036 }
1037 mc->vram_start = mc->gtt_end;
1038 }
1039 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1040 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1041 mc->mc_vram_size >> 20, mc->vram_start,
1042 mc->vram_end, mc->real_vram_size >> 20);
1043 } else {
1044 radeon_vram_location(rdev, &rdev->mc, 0);
1045 rdev->mc.gtt_base_align = 0;
1046 radeon_gtt_location(rdev, mc);
1047 }
1048}
1049
1050int rv770_mc_init(struct radeon_device *rdev)
1051{
1052 u32 tmp;
1053 int chansize, numchan;
1054
1055 /* Get VRAM informations */
1056 rdev->mc.vram_is_ddr = true;
1057 tmp = RREG32(MC_ARB_RAMCFG);
1058 if (tmp & CHANSIZE_OVERRIDE) {
1059 chansize = 16;
1060 } else if (tmp & CHANSIZE_MASK) {
1061 chansize = 64;
1062 } else {
1063 chansize = 32;
1064 }
1065 tmp = RREG32(MC_SHARED_CHMAP);
1066 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1067 case 0:
1068 default:
1069 numchan = 1;
1070 break;
1071 case 1:
1072 numchan = 2;
1073 break;
1074 case 2:
1075 numchan = 4;
1076 break;
1077 case 3:
1078 numchan = 8;
1079 break;
1080 }
1081 rdev->mc.vram_width = numchan * chansize;
1082 /* Could aper size report 0 ? */
1083 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1084 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1085 /* Setup GPU memory space */
1086 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1087 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1088 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1089 r700_vram_gtt_location(rdev, &rdev->mc);
1090 radeon_update_bandwidth_info(rdev);
1091
1092 return 0;
1093}
1094
1095static int rv770_startup(struct radeon_device *rdev)
1096{
1097 int r;
1098
1099 /* enable pcie gen2 link */
1100 rv770_pcie_gen2_enable(rdev);
1101
1102 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1103 r = r600_init_microcode(rdev);
1104 if (r) {
1105 DRM_ERROR("Failed to load firmware!\n");
1106 return r;
1107 }
1108 }
1109
1110 rv770_mc_program(rdev);
1111 if (rdev->flags & RADEON_IS_AGP) {
1112 rv770_agp_enable(rdev);
1113 } else {
1114 r = rv770_pcie_gart_enable(rdev);
1115 if (r)
1116 return r;
1117 }
1118 r = rv770_vram_scratch_init(rdev);
1119 if (r)
1120 return r;
1121 rv770_gpu_init(rdev);
1122 r = r600_blit_init(rdev);
1123 if (r) {
1124 r600_blit_fini(rdev);
1125 rdev->asic->copy = NULL;
1126 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1127 }
1128
1129 /* allocate wb buffer */
1130 r = radeon_wb_init(rdev);
1131 if (r)
1132 return r;
1133
1134 /* Enable IRQ */
1135 r = r600_irq_init(rdev);
1136 if (r) {
1137 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1138 radeon_irq_kms_fini(rdev);
1139 return r;
1140 }
1141 r600_irq_set(rdev);
1142
1143 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1144 if (r)
1145 return r;
1146 r = rv770_cp_load_microcode(rdev);
1147 if (r)
1148 return r;
1149 r = r600_cp_resume(rdev);
1150 if (r)
1151 return r;
1152
1153 return 0;
1154}
1155
1156int rv770_resume(struct radeon_device *rdev)
1157{
1158 int r;
1159
1160 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1161 * posting will perform necessary task to bring back GPU into good
1162 * shape.
1163 */
1164 /* post card */
1165 atom_asic_init(rdev->mode_info.atom_context);
1166
1167 r = rv770_startup(rdev);
1168 if (r) {
1169 DRM_ERROR("r600 startup failed on resume\n");
1170 return r;
1171 }
1172
1173 r = r600_ib_test(rdev);
1174 if (r) {
1175 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1176 return r;
1177 }
1178
1179 r = r600_audio_init(rdev);
1180 if (r) {
1181 dev_err(rdev->dev, "radeon: audio init failed\n");
1182 return r;
1183 }
1184
1185 return r;
1186
1187}
1188
1189int rv770_suspend(struct radeon_device *rdev)
1190{
1191 int r;
1192
1193 r600_audio_fini(rdev);
1194 /* FIXME: we should wait for ring to be empty */
1195 r700_cp_stop(rdev);
1196 rdev->cp.ready = false;
1197 r600_irq_suspend(rdev);
1198 radeon_wb_disable(rdev);
1199 rv770_pcie_gart_disable(rdev);
1200 /* unpin shaders bo */
1201 if (rdev->r600_blit.shader_obj) {
1202 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1203 if (likely(r == 0)) {
1204 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1205 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1206 }
1207 }
1208 return 0;
1209}
1210
1211/* Plan is to move initialization in that function and use
1212 * helper function so that radeon_device_init pretty much
1213 * do nothing more than calling asic specific function. This
1214 * should also allow to remove a bunch of callback function
1215 * like vram_info.
1216 */
1217int rv770_init(struct radeon_device *rdev)
1218{
1219 int r;
1220
1221 /* This don't do much */
1222 r = radeon_gem_init(rdev);
1223 if (r)
1224 return r;
1225 /* Read BIOS */
1226 if (!radeon_get_bios(rdev)) {
1227 if (ASIC_IS_AVIVO(rdev))
1228 return -EINVAL;
1229 }
1230 /* Must be an ATOMBIOS */
1231 if (!rdev->is_atom_bios) {
1232 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1233 return -EINVAL;
1234 }
1235 r = radeon_atombios_init(rdev);
1236 if (r)
1237 return r;
1238 /* Post card if necessary */
1239 if (!radeon_card_posted(rdev)) {
1240 if (!rdev->bios) {
1241 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1242 return -EINVAL;
1243 }
1244 DRM_INFO("GPU not posted. posting now...\n");
1245 atom_asic_init(rdev->mode_info.atom_context);
1246 }
1247 /* Initialize scratch registers */
1248 r600_scratch_init(rdev);
1249 /* Initialize surface registers */
1250 radeon_surface_init(rdev);
1251 /* Initialize clocks */
1252 radeon_get_clock_info(rdev->ddev);
1253 /* Fence driver */
1254 r = radeon_fence_driver_init(rdev);
1255 if (r)
1256 return r;
1257 /* initialize AGP */
1258 if (rdev->flags & RADEON_IS_AGP) {
1259 r = radeon_agp_init(rdev);
1260 if (r)
1261 radeon_agp_disable(rdev);
1262 }
1263 r = rv770_mc_init(rdev);
1264 if (r)
1265 return r;
1266 /* Memory manager */
1267 r = radeon_bo_init(rdev);
1268 if (r)
1269 return r;
1270
1271 r = radeon_irq_kms_init(rdev);
1272 if (r)
1273 return r;
1274
1275 rdev->cp.ring_obj = NULL;
1276 r600_ring_init(rdev, 1024 * 1024);
1277
1278 rdev->ih.ring_obj = NULL;
1279 r600_ih_ring_init(rdev, 64 * 1024);
1280
1281 r = r600_pcie_gart_init(rdev);
1282 if (r)
1283 return r;
1284
1285 rdev->accel_working = true;
1286 r = rv770_startup(rdev);
1287 if (r) {
1288 dev_err(rdev->dev, "disabling GPU acceleration\n");
1289 r700_cp_fini(rdev);
1290 r600_irq_fini(rdev);
1291 radeon_wb_fini(rdev);
1292 radeon_irq_kms_fini(rdev);
1293 rv770_pcie_gart_fini(rdev);
1294 rdev->accel_working = false;
1295 }
1296 if (rdev->accel_working) {
1297 r = radeon_ib_pool_init(rdev);
1298 if (r) {
1299 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1300 rdev->accel_working = false;
1301 } else {
1302 r = r600_ib_test(rdev);
1303 if (r) {
1304 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1305 rdev->accel_working = false;
1306 }
1307 }
1308 }
1309
1310 r = r600_audio_init(rdev);
1311 if (r) {
1312 dev_err(rdev->dev, "radeon: audio init failed\n");
1313 return r;
1314 }
1315
1316 return 0;
1317}
1318
1319void rv770_fini(struct radeon_device *rdev)
1320{
1321 r600_blit_fini(rdev);
1322 r700_cp_fini(rdev);
1323 r600_irq_fini(rdev);
1324 radeon_wb_fini(rdev);
1325 radeon_ib_pool_fini(rdev);
1326 radeon_irq_kms_fini(rdev);
1327 rv770_pcie_gart_fini(rdev);
1328 rv770_vram_scratch_fini(rdev);
1329 radeon_gem_fini(rdev);
1330 radeon_fence_driver_fini(rdev);
1331 radeon_agp_fini(rdev);
1332 radeon_bo_fini(rdev);
1333 radeon_atombios_fini(rdev);
1334 kfree(rdev->bios);
1335 rdev->bios = NULL;
1336}
1337
1338static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1339{
1340 u32 link_width_cntl, lanes, speed_cntl, tmp;
1341 u16 link_cntl2;
1342
1343 if (radeon_pcie_gen2 == 0)
1344 return;
1345
1346 if (rdev->flags & RADEON_IS_IGP)
1347 return;
1348
1349 if (!(rdev->flags & RADEON_IS_PCIE))
1350 return;
1351
1352 /* x2 cards have a special sequence */
1353 if (ASIC_IS_X2(rdev))
1354 return;
1355
1356 /* advertise upconfig capability */
1357 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1358 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1359 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1360 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1361 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1362 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1363 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1364 LC_RECONFIG_ARC_MISSING_ESCAPE);
1365 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1366 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1367 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1368 } else {
1369 link_width_cntl |= LC_UPCONFIGURE_DIS;
1370 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1371 }
1372
1373 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1374 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1375 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1376
1377 tmp = RREG32(0x541c);
1378 WREG32(0x541c, tmp | 0x8);
1379 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1380 link_cntl2 = RREG16(0x4088);
1381 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1382 link_cntl2 |= 0x2;
1383 WREG16(0x4088, link_cntl2);
1384 WREG32(MM_CFGREGS_CNTL, 0);
1385
1386 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1387 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1388 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1389
1390 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1391 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1392 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1393
1394 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1395 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1396 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1397
1398 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1399 speed_cntl |= LC_GEN2_EN_STRAP;
1400 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1401
1402 } else {
1403 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1404 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1405 if (1)
1406 link_width_cntl |= LC_UPCONFIGURE_DIS;
1407 else
1408 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1409 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1410 }
1411}