/drivers/mmc/host/omap_hsmmc.c
C | 2493 lines | 1820 code | 401 blank | 272 comment | 336 complexity | fae7bfffea0f9a44361d44ffba8f8b2e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
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1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
30#include <linux/mmc/core.h>
31#include <linux/mmc/card.h>
32#include <linux/mmc/mmc.h>
33#include <linux/io.h>
34#include <linux/semaphore.h>
35#include <linux/gpio.h>
36#include <linux/regulator/consumer.h>
37#include <linux/pm_runtime.h>
38
39#include <plat/dma.h>
40#include <mach/hardware.h>
41#include <plat/board.h>
42#include <plat/mmc.h>
43#include <plat/cpu.h>
44#include <plat/omap-pm.h>
45
46/* OMAP HSMMC Host Controller Registers */
47#define OMAP_HSMMC_SYSCONFIG 0x0010
48#define OMAP_HSMMC_SYSSTATUS 0x0014
49#define OMAP_HSMMC_CON 0x002C
50#define OMAP_HSMMC_BLK 0x0104
51#define OMAP_HSMMC_ARG 0x0108
52#define OMAP_HSMMC_CMD 0x010C
53#define OMAP_HSMMC_RSP10 0x0110
54#define OMAP_HSMMC_RSP32 0x0114
55#define OMAP_HSMMC_RSP54 0x0118
56#define OMAP_HSMMC_RSP76 0x011C
57#define OMAP_HSMMC_DATA 0x0120
58#define OMAP_HSMMC_HCTL 0x0128
59#define OMAP_HSMMC_SYSCTL 0x012C
60#define OMAP_HSMMC_STAT 0x0130
61#define OMAP_HSMMC_IE 0x0134
62#define OMAP_HSMMC_ISE 0x0138
63#define OMAP_HSMMC_CAPA 0x0140
64
65#define VS18 (1 << 26)
66#define VS30 (1 << 25)
67#define SDVS18 (0x5 << 9)
68#define SDVS30 (0x6 << 9)
69#define SDVS33 (0x7 << 9)
70#define SDVS_MASK 0x00000E00
71#define SDVSCLR 0xFFFFF1FF
72#define SDVSDET 0x00000400
73#define AUTOIDLE 0x1
74#define SDBP (1 << 8)
75#define DTO 0xe
76#define ICE 0x1
77#define ICS 0x2
78#define CEN (1 << 2)
79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
83#define INT_EN_MASK 0x307F0033
84#define BWR_ENABLE (1 << 4)
85#define BRR_ENABLE (1 << 5)
86#define DTO_ENABLE (1 << 20)
87#define INIT_STREAM (1 << 1)
88#define DP_SELECT (1 << 21)
89#define DDIR (1 << 4)
90#define DMA_EN 0x1
91#define MSBS (1 << 5)
92#define BCE (1 << 1)
93#define FOUR_BIT (1 << 1)
94#define DW8 (1 << 5)
95#define CC 0x1
96#define TC 0x02
97#define OD 0x1
98#define ERR (1 << 15)
99#define CMD_TIMEOUT (1 << 16)
100#define DATA_TIMEOUT (1 << 20)
101#define CMD_CRC (1 << 17)
102#define DATA_CRC (1 << 21)
103#define CARD_ERR (1 << 28)
104#define STAT_CLEAR 0xFFFFFFFF
105#define INIT_STREAM_CMD 0x00000000
106#define DUAL_VOLT_OCR_BIT 7
107#define SRC (1 << 25)
108#define SRD (1 << 26)
109#define SOFTRESET (1 << 1)
110#define RESETDONE (1 << 0)
111
112/*
113 * FIXME: Most likely all the data using these _DEVID defines should come
114 * from the platform_data, or implemented in controller and slot specific
115 * functions.
116 */
117#define OMAP_MMC1_DEVID 0
118#define OMAP_MMC2_DEVID 1
119#define OMAP_MMC3_DEVID 2
120#define OMAP_MMC4_DEVID 3
121#define OMAP_MMC5_DEVID 4
122
123#define MMC_TIMEOUT_MS 20
124#define OMAP_MMC_MASTER_CLOCK 96000000
125#define DRIVER_NAME "omap_hsmmc"
126
127/* Timeouts for entering power saving states on inactivity, msec */
128#define OMAP_MMC_DISABLED_TIMEOUT 100
129#define OMAP_MMC_SLEEP_TIMEOUT 1000
130#define OMAP_MMC_OFF_TIMEOUT 8000
131
132/*
133 * One controller can have multiple slots, like on some omap boards using
134 * omap.c controller driver. Luckily this is not currently done on any known
135 * omap_hsmmc.c device.
136 */
137#define mmc_slot(host) (host->pdata->slots[host->slot_id])
138
139/*
140 * MMC Host controller read/write API's
141 */
142#define OMAP_HSMMC_READ(base, reg) \
143 __raw_readl((base) + OMAP_HSMMC_##reg)
144
145#define OMAP_HSMMC_WRITE(base, reg, val) \
146 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
147
148struct omap_hsmmc_host {
149 struct device *dev;
150 struct mmc_host *mmc;
151 struct mmc_request *mrq;
152 struct mmc_command *cmd;
153 struct mmc_data *data;
154 struct clk *fclk;
155 struct clk *iclk;
156 struct clk *dbclk;
157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
166 struct work_struct mmc_carddetect_work;
167 void __iomem *base;
168 resource_size_t mapbase;
169 spinlock_t irq_lock; /* Prevent races with irq handler */
170 unsigned int id;
171 unsigned int dma_len;
172 unsigned int dma_sg_idx;
173 unsigned int master_clock;
174 unsigned char bus_mode;
175 unsigned char power_mode;
176 u32 *buffer;
177 u32 bytesleft;
178 int suspended;
179 int irq;
180 int use_dma, dma_ch;
181 int dma_line_tx, dma_line_rx;
182 int slot_id;
183 int got_dbclk;
184 int response_busy;
185 int dpm_state;
186 int vdd;
187 int protect_card;
188 int reqs_blocked;
189 int use_reg;
190 int req_in_progress;
191
192 struct omap_mmc_platform_data *pdata;
193};
194
195static void omap_hsmmc_status_notify_cb(int card_present, void *dev_id)
196{
197 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
198 unsigned int status, oldstat;
199
200 pr_debug("%s: card_present %d\n", mmc_hostname(host->mmc),
201 card_present);
202
203 if (!mmc_slot(host).mmc_data.status) {
204 mmc_detect_change(host->mmc, 0);
205 return;
206 }
207
208 status = mmc_slot(host).mmc_data.status(mmc_dev(host->mmc));
209
210 oldstat = mmc_slot(host).mmc_data.card_present;
211 mmc_slot(host).mmc_data.card_present = status;
212 if (status ^ oldstat) {
213 pr_debug("%s: Slot status change detected (%d -> %d)\n",
214 mmc_hostname(host->mmc), oldstat, status);
215 mmc_detect_change(host->mmc, 0);
216 }
217}
218
219static int omap_hsmmc_card_detect(struct device *dev, int slot)
220{
221 struct omap_mmc_platform_data *mmc = dev->platform_data;
222
223 /* NOTE: assumes card detect signal is active-low */
224 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
225}
226
227static int omap_hsmmc_get_wp(struct device *dev, int slot)
228{
229 struct omap_mmc_platform_data *mmc = dev->platform_data;
230
231 /* NOTE: assumes write protect signal is active-high */
232 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
233}
234
235static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
236{
237 struct omap_mmc_platform_data *mmc = dev->platform_data;
238
239 /* NOTE: assumes card detect signal is active-low */
240 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
241}
242
243#ifdef CONFIG_PM
244
245static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
246{
247 struct omap_mmc_platform_data *mmc = dev->platform_data;
248
249 disable_irq(mmc->slots[0].card_detect_irq);
250 return 0;
251}
252
253static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
254{
255 struct omap_mmc_platform_data *mmc = dev->platform_data;
256
257 enable_irq(mmc->slots[0].card_detect_irq);
258 return 0;
259}
260
261#else
262
263#define omap_hsmmc_suspend_cdirq NULL
264#define omap_hsmmc_resume_cdirq NULL
265
266#endif
267
268#ifdef CONFIG_REGULATOR
269
270static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
271 int vdd)
272{
273 struct omap_hsmmc_host *host =
274 platform_get_drvdata(to_platform_device(dev));
275 int ret;
276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 if (power_on)
281 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
282 else
283 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
284
285 if (mmc_slot(host).after_set_reg)
286 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
287
288 return ret;
289}
290
291static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
292 int vdd)
293{
294 struct omap_hsmmc_host *host =
295 platform_get_drvdata(to_platform_device(dev));
296 int ret = 0;
297
298 /*
299 * If we don't see a Vcc regulator, assume it's a fixed
300 * voltage always-on regulator.
301 */
302 if (!host->vcc)
303 return 0;
304
305 if (mmc_slot(host).before_set_reg)
306 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
307
308 /*
309 * Assume Vcc regulator is used only to power the card ... OMAP
310 * VDDS is used to power the pins, optionally with a transceiver to
311 * support cards using voltages other than VDDS (1.8V nominal). When a
312 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
313 *
314 * In some cases this regulator won't support enable/disable;
315 * e.g. it's a fixed rail for a WLAN chip.
316 *
317 * In other cases vcc_aux switches interface power. Example, for
318 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
319 * chips/cards need an interface voltage rail too.
320 */
321 if (power_on) {
322 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
323 /* Enable interface voltage rail, if needed */
324 if (ret == 0 && host->vcc_aux) {
325 ret = regulator_enable(host->vcc_aux);
326 if (ret < 0)
327 ret = mmc_regulator_set_ocr(host->mmc,
328 host->vcc, 0);
329 }
330 } else {
331 /* Shut down the rail */
332 if (host->vcc_aux)
333 ret = regulator_disable(host->vcc_aux);
334 if (!ret) {
335 /* Then proceed to shut down the local regulator */
336 ret = mmc_regulator_set_ocr(host->mmc,
337 host->vcc, 0);
338 }
339 }
340
341 if (mmc_slot(host).after_set_reg)
342 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
343
344 return ret;
345}
346
347static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
348 int vdd)
349{
350 return 0;
351}
352
353static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
354 int vdd, int cardsleep)
355{
356 struct omap_hsmmc_host *host =
357 platform_get_drvdata(to_platform_device(dev));
358 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
359
360 return regulator_set_mode(host->vcc, mode);
361}
362
363static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
364 int vdd, int cardsleep)
365{
366 struct omap_hsmmc_host *host =
367 platform_get_drvdata(to_platform_device(dev));
368 int err, mode;
369
370 /*
371 * If we don't see a Vcc regulator, assume it's a fixed
372 * voltage always-on regulator.
373 */
374 if (!host->vcc)
375 return 0;
376
377 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
378
379 if (!host->vcc_aux)
380 return regulator_set_mode(host->vcc, mode);
381
382 if (cardsleep) {
383 /* VCC can be turned off if card is asleep */
384 if (sleep)
385 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
386 else
387 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
388 } else
389 err = regulator_set_mode(host->vcc, mode);
390 if (err)
391 return err;
392
393 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
394 return regulator_set_mode(host->vcc_aux, mode);
395
396 if (sleep)
397 return regulator_disable(host->vcc_aux);
398 else
399 return regulator_enable(host->vcc_aux);
400}
401
402static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
403 int vdd, int cardsleep)
404{
405 return 0;
406}
407
408static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
409{
410 struct regulator *reg;
411 int ret = 0;
412 int ocr_value = 0;
413
414 switch (host->id) {
415 case OMAP_MMC1_DEVID:
416 /* On-chip level shifting via PBIAS0/PBIAS1 */
417 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
418 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
419 break;
420 case OMAP_MMC2_DEVID:
421 case OMAP_MMC3_DEVID:
422 case OMAP_MMC5_DEVID:
423 /* Off-chip level shifting, or none */
424 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
425 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
426 break;
427 case OMAP_MMC4_DEVID:
428 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
429 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
430 default:
431 pr_err("MMC%d configuration not supported!\n", host->id);
432 return -EINVAL;
433 }
434
435 reg = regulator_get(host->dev, "vmmc");
436 if (IS_ERR(reg)) {
437 dev_dbg(host->dev, "vmmc regulator missing\n");
438 /*
439 * HACK: until fixed.c regulator is usable,
440 * we don't require a main regulator
441 * for MMC2 or MMC3
442 */
443 if (host->id == OMAP_MMC1_DEVID) {
444 ret = PTR_ERR(reg);
445 goto err;
446 }
447 } else {
448 host->vcc = reg;
449 ocr_value = mmc_regulator_get_ocrmask(reg);
450 if (!mmc_slot(host).ocr_mask) {
451 mmc_slot(host).ocr_mask = ocr_value;
452 } else {
453 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
454 pr_err("MMC%d ocrmask %x is not supported\n",
455 host->id, mmc_slot(host).ocr_mask);
456 mmc_slot(host).ocr_mask = 0;
457 return -EINVAL;
458 }
459 }
460
461 /* Allow an aux regulator */
462 reg = regulator_get(host->dev, "vmmc_aux");
463 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
464
465 /* For eMMC do not power off when not in sleep state */
466 if (mmc_slot(host).no_regulator_off_init)
467 return 0;
468 /*
469 * UGLY HACK: workaround regulator framework bugs.
470 * When the bootloader leaves a supply active, it's
471 * initialized with zero usecount ... and we can't
472 * disable it without first enabling it. Until the
473 * framework is fixed, we need a workaround like this
474 * (which is safe for MMC, but not in general).
475 */
476 if (regulator_is_enabled(host->vcc) > 0) {
477 regulator_enable(host->vcc);
478 regulator_disable(host->vcc);
479 }
480 if (host->vcc_aux) {
481 if (regulator_is_enabled(reg) > 0) {
482 regulator_enable(reg);
483 regulator_disable(reg);
484 }
485 }
486 }
487
488 return 0;
489
490err:
491 mmc_slot(host).set_power = NULL;
492 mmc_slot(host).set_sleep = NULL;
493 return ret;
494}
495
496static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
497{
498 regulator_put(host->vcc);
499 regulator_put(host->vcc_aux);
500 mmc_slot(host).set_power = NULL;
501 mmc_slot(host).set_sleep = NULL;
502}
503
504static inline int omap_hsmmc_have_reg(void)
505{
506 return 1;
507}
508
509#else
510
511static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
512{
513 return -EINVAL;
514}
515
516static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
517{
518}
519
520static inline int omap_hsmmc_have_reg(void)
521{
522 return 0;
523}
524
525#endif
526
527static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
528{
529 int ret;
530
531 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
532 if (pdata->slots[0].cover)
533 pdata->slots[0].get_cover_state =
534 omap_hsmmc_get_cover_state;
535 else
536 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
537 pdata->slots[0].card_detect_irq =
538 gpio_to_irq(pdata->slots[0].switch_pin);
539 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
540 if (ret)
541 return ret;
542 ret = gpio_direction_input(pdata->slots[0].switch_pin);
543 if (ret)
544 goto err_free_sp;
545 } else
546 pdata->slots[0].switch_pin = -EINVAL;
547
548 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
549 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
550 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
551 if (ret)
552 goto err_free_cd;
553 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
554 if (ret)
555 goto err_free_wp;
556 } else
557 pdata->slots[0].gpio_wp = -EINVAL;
558
559 return 0;
560
561err_free_wp:
562 gpio_free(pdata->slots[0].gpio_wp);
563err_free_cd:
564 if (gpio_is_valid(pdata->slots[0].switch_pin))
565err_free_sp:
566 gpio_free(pdata->slots[0].switch_pin);
567 return ret;
568}
569
570static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
571{
572 if (gpio_is_valid(pdata->slots[0].gpio_wp))
573 gpio_free(pdata->slots[0].gpio_wp);
574 if (gpio_is_valid(pdata->slots[0].switch_pin))
575 gpio_free(pdata->slots[0].switch_pin);
576}
577
578/*
579 * Stop clock to the card
580 */
581static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
582{
583 OMAP_HSMMC_WRITE(host->base, SYSCTL,
584 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
585 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
586 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
587}
588
589static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
590 struct mmc_command *cmd)
591{
592 unsigned int irq_mask;
593
594 if (host->use_dma)
595 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
596 else
597 irq_mask = INT_EN_MASK;
598
599 /* Disable timeout for erases */
600 if (cmd->opcode == MMC_ERASE)
601 irq_mask &= ~DTO_ENABLE;
602
603 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
604 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
605 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
606}
607
608static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
609{
610 OMAP_HSMMC_WRITE(host->base, ISE, 0);
611 OMAP_HSMMC_WRITE(host->base, IE, 0);
612 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
613}
614
615#ifdef CONFIG_PM
616
617/*
618 * Restore the MMC host context, if it was lost as result of a
619 * power state change.
620 */
621static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
622{
623 struct mmc_ios *ios = &host->mmc->ios;
624 u32 hctl, capa, con;
625 u16 dsor = 0;
626 unsigned long timeout;
627
628 if (!omap_pm_was_context_lost(host->dev))
629 return 1;
630
631 /* Wait for hardware reset */
632 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
633 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
634 && time_before(jiffies, timeout))
635 ;
636
637 /* Do software reset */
638 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
639 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
640 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
641 && time_before(jiffies, timeout))
642 ;
643
644 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
645 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
646
647 if (host->id == OMAP_MMC1_DEVID) {
648 if (host->power_mode != MMC_POWER_OFF &&
649 (1 << ios->vdd) <= MMC_VDD_23_24)
650 hctl = SDVS18;
651 else
652 hctl = SDVS30;
653 capa = VS30 | VS18;
654 } else {
655 hctl = SDVS18;
656 capa = VS18;
657 }
658
659 OMAP_HSMMC_WRITE(host->base, HCTL,
660 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
661
662 OMAP_HSMMC_WRITE(host->base, CAPA,
663 OMAP_HSMMC_READ(host->base, CAPA) | capa);
664
665 OMAP_HSMMC_WRITE(host->base, HCTL,
666 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
667
668 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
669 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
670 && time_before(jiffies, timeout))
671 ;
672
673 omap_hsmmc_disable_irq(host);
674
675 /* Do not initialize card-specific things if the power is off */
676 if (host->power_mode == MMC_POWER_OFF)
677 goto out;
678
679 con = OMAP_HSMMC_READ(host->base, CON);
680 switch (ios->bus_width) {
681 case MMC_BUS_WIDTH_8:
682 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
683 break;
684 case MMC_BUS_WIDTH_4:
685 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
686 OMAP_HSMMC_WRITE(host->base, HCTL,
687 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
688 break;
689 case MMC_BUS_WIDTH_1:
690 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
691 OMAP_HSMMC_WRITE(host->base, HCTL,
692 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
693 break;
694 }
695
696 if (ios->clock) {
697 dsor = host->master_clock / ios->clock;
698 if (dsor < 1)
699 dsor = 1;
700
701 if (host->master_clock / dsor > ios->clock)
702 dsor++;
703
704 if (dsor > 250)
705 dsor = 250;
706 }
707
708 OMAP_HSMMC_WRITE(host->base, SYSCTL,
709 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
710 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
711 OMAP_HSMMC_WRITE(host->base, SYSCTL,
712 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
713
714 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
715 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
716 && time_before(jiffies, timeout))
717 ;
718
719 OMAP_HSMMC_WRITE(host->base, SYSCTL,
720 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
721
722 con = OMAP_HSMMC_READ(host->base, CON);
723 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
724 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
725 else
726 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
727out:
728 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
729 return 0;
730}
731
732/*
733 * Save the MMC host context (store the number of power state changes so far).
734 */
735static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
736{
737 return;
738}
739
740#else
741
742static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
743{
744 return 0;
745}
746
747static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
748{
749}
750
751#endif
752
753/*
754 * Send init stream sequence to card
755 * before sending IDLE command
756 */
757static void send_init_stream(struct omap_hsmmc_host *host)
758{
759 int reg = 0;
760 unsigned long timeout;
761
762 if (host->protect_card)
763 return;
764
765 disable_irq(host->irq);
766
767 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
768 OMAP_HSMMC_WRITE(host->base, CON,
769 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
770 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
771
772 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
773 while ((reg != CC) && time_before(jiffies, timeout))
774 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
775
776 OMAP_HSMMC_WRITE(host->base, CON,
777 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
778
779 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
780 OMAP_HSMMC_READ(host->base, STAT);
781
782 enable_irq(host->irq);
783}
784
785static inline
786int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
787{
788 int r = 1;
789
790 if (mmc_slot(host).get_cover_state)
791 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
792 return r;
793}
794
795static ssize_t
796omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
797 char *buf)
798{
799 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
800 struct omap_hsmmc_host *host = mmc_priv(mmc);
801
802 return sprintf(buf, "%s\n",
803 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
804}
805
806static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
807
808static ssize_t
809omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
810 char *buf)
811{
812 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
813 struct omap_hsmmc_host *host = mmc_priv(mmc);
814
815 return sprintf(buf, "%s\n", mmc_slot(host).name);
816}
817
818static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
819
820/*
821 * Configure the response type and send the cmd.
822 */
823static void
824omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
825 struct mmc_data *data)
826{
827 int cmdreg = 0, resptype = 0, cmdtype = 0;
828
829 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
830 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
831 host->cmd = cmd;
832
833 omap_hsmmc_enable_irq(host, cmd);
834
835 host->response_busy = 0;
836 if (cmd->flags & MMC_RSP_PRESENT) {
837 if (cmd->flags & MMC_RSP_136)
838 resptype = 1;
839 else if (cmd->flags & MMC_RSP_BUSY) {
840 resptype = 3;
841 host->response_busy = 1;
842 } else
843 resptype = 2;
844 }
845
846 /*
847 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
848 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
849 * a val of 0x3, rest 0x0.
850 */
851 if (cmd == host->mrq->stop)
852 cmdtype = 0x3;
853
854 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
855
856 if (data) {
857 cmdreg |= DP_SELECT | MSBS | BCE;
858 if (data->flags & MMC_DATA_READ)
859 cmdreg |= DDIR;
860 else
861 cmdreg &= ~(DDIR);
862 }
863
864 if (host->use_dma)
865 cmdreg |= DMA_EN;
866
867 host->req_in_progress = 1;
868
869 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
870 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
871}
872
873static int
874omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
875{
876 if (data->flags & MMC_DATA_WRITE)
877 return DMA_TO_DEVICE;
878 else
879 return DMA_FROM_DEVICE;
880}
881
882static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
883{
884 int dma_ch;
885
886 spin_lock(&host->irq_lock);
887 host->req_in_progress = 0;
888 dma_ch = host->dma_ch;
889 spin_unlock(&host->irq_lock);
890
891 omap_hsmmc_disable_irq(host);
892 /* Do not complete the request if DMA is still in progress */
893 if (mrq->data && host->use_dma && dma_ch != -1)
894 return;
895 host->mrq = NULL;
896 mmc_request_done(host->mmc, mrq);
897}
898
899/*
900 * Notify the transfer complete to MMC core
901 */
902static void
903omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
904{
905 if (!data) {
906 struct mmc_request *mrq = host->mrq;
907
908 /* TC before CC from CMD6 - don't know why, but it happens */
909 if (host->cmd && host->cmd->opcode == 6 &&
910 host->response_busy) {
911 host->response_busy = 0;
912 return;
913 }
914
915 omap_hsmmc_request_done(host, mrq);
916 return;
917 }
918
919 host->data = NULL;
920
921 if (!data->error)
922 data->bytes_xfered += data->blocks * (data->blksz);
923 else
924 data->bytes_xfered = 0;
925
926 if (!data->stop) {
927 omap_hsmmc_request_done(host, data->mrq);
928 return;
929 }
930 omap_hsmmc_start_command(host, data->stop, NULL);
931}
932
933/*
934 * Notify the core about command completion
935 */
936static void
937omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
938{
939 host->cmd = NULL;
940
941 if (cmd->flags & MMC_RSP_PRESENT) {
942 if (cmd->flags & MMC_RSP_136) {
943 /* response type 2 */
944 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
945 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
946 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
947 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
948 } else {
949 /* response types 1, 1b, 3, 4, 5, 6 */
950 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
951 }
952 }
953 if ((host->data == NULL && !host->response_busy) || cmd->error)
954 omap_hsmmc_request_done(host, cmd->mrq);
955}
956
957/*
958 * DMA clean up for command errors
959 */
960static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
961{
962 int dma_ch;
963
964 host->data->error = errno;
965
966 spin_lock(&host->irq_lock);
967 dma_ch = host->dma_ch;
968 host->dma_ch = -1;
969 spin_unlock(&host->irq_lock);
970
971 if (host->use_dma && dma_ch != -1) {
972 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
973 host->data->sg_len,
974 omap_hsmmc_get_dma_dir(host, host->data));
975 omap_free_dma(dma_ch);
976 }
977 host->data = NULL;
978}
979
980/*
981 * Readable error output
982 */
983#ifdef CONFIG_MMC_DEBUG
984static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
985{
986 /* --- means reserved bit without definition at documentation */
987 static const char *omap_hsmmc_status_bits[] = {
988 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
989 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
990 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
991 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
992 };
993 char res[256];
994 char *buf = res;
995 int len, i;
996
997 len = sprintf(buf, "MMC IRQ 0x%x :", status);
998 buf += len;
999
1000 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1001 if (status & (1 << i)) {
1002 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1003 buf += len;
1004 }
1005
1006 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1007}
1008#endif /* CONFIG_MMC_DEBUG */
1009
1010/*
1011 * MMC controller internal state machines reset
1012 *
1013 * Used to reset command or data internal state machines, using respectively
1014 * SRC or SRD bit of SYSCTL register
1015 * Can be called from interrupt context
1016 */
1017static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1018 unsigned long bit)
1019{
1020 unsigned long i = 0;
1021 unsigned long limit = (loops_per_jiffy *
1022 msecs_to_jiffies(MMC_TIMEOUT_MS));
1023
1024 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1025 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1026
1027 /*
1028 * OMAP4 ES2 and greater has an updated reset logic.
1029 * Monitor a 0->1 transition first
1030 */
1031 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1032 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1033 && (i++ < limit))
1034 cpu_relax();
1035 }
1036 i = 0;
1037
1038 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1039 (i++ < limit))
1040 cpu_relax();
1041
1042 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1043 dev_err(mmc_dev(host->mmc),
1044 "Timeout waiting on controller reset in %s\n",
1045 __func__);
1046}
1047
1048static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1049{
1050 struct mmc_data *data;
1051 int end_cmd = 0, end_trans = 0;
1052
1053 if (!host->req_in_progress) {
1054 do {
1055 OMAP_HSMMC_WRITE(host->base, STAT, status);
1056 /* Flush posted write */
1057 status = OMAP_HSMMC_READ(host->base, STAT);
1058 } while (status & INT_EN_MASK);
1059 return;
1060 }
1061
1062 data = host->data;
1063 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1064
1065 if (status & ERR) {
1066#ifdef CONFIG_MMC_DEBUG
1067 omap_hsmmc_report_irq(host, status);
1068#endif
1069 if ((status & CMD_TIMEOUT) ||
1070 (status & CMD_CRC)) {
1071 if (host->cmd) {
1072 if (status & CMD_TIMEOUT) {
1073 omap_hsmmc_reset_controller_fsm(host,
1074 SRC);
1075 host->cmd->error = -ETIMEDOUT;
1076 } else {
1077 host->cmd->error = -EILSEQ;
1078 }
1079 end_cmd = 1;
1080 }
1081 if (host->data || host->response_busy) {
1082 if (host->data)
1083 omap_hsmmc_dma_cleanup(host,
1084 -ETIMEDOUT);
1085 host->response_busy = 0;
1086 omap_hsmmc_reset_controller_fsm(host, SRD);
1087 }
1088 }
1089 if ((status & DATA_TIMEOUT) ||
1090 (status & DATA_CRC)) {
1091 if (host->data || host->response_busy) {
1092 int err = (status & DATA_TIMEOUT) ?
1093 -ETIMEDOUT : -EILSEQ;
1094
1095 if (host->data)
1096 omap_hsmmc_dma_cleanup(host, err);
1097 else
1098 host->mrq->cmd->error = err;
1099 host->response_busy = 0;
1100 omap_hsmmc_reset_controller_fsm(host, SRD);
1101 end_trans = 1;
1102 }
1103 }
1104 if (status & CARD_ERR) {
1105 dev_dbg(mmc_dev(host->mmc),
1106 "Ignoring card err CMD%d\n", host->cmd->opcode);
1107 if (host->cmd)
1108 end_cmd = 1;
1109 if (host->data)
1110 end_trans = 1;
1111 }
1112 }
1113
1114 OMAP_HSMMC_WRITE(host->base, STAT, status);
1115
1116 if (end_cmd || ((status & CC) && host->cmd))
1117 omap_hsmmc_cmd_done(host, host->cmd);
1118 if ((end_trans || (status & TC)) && host->mrq)
1119 omap_hsmmc_xfer_done(host, data);
1120}
1121
1122/*
1123 * MMC controller IRQ handler
1124 */
1125static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1126{
1127 struct omap_hsmmc_host *host = dev_id;
1128 int status;
1129
1130 status = OMAP_HSMMC_READ(host->base, STAT);
1131 do {
1132 omap_hsmmc_do_irq(host, status);
1133 /* Flush posted write */
1134 status = OMAP_HSMMC_READ(host->base, STAT);
1135 } while (status & INT_EN_MASK);
1136
1137 return IRQ_HANDLED;
1138}
1139
1140static void set_sd_bus_power(struct omap_hsmmc_host *host)
1141{
1142 unsigned long i;
1143
1144 OMAP_HSMMC_WRITE(host->base, HCTL,
1145 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1146 for (i = 0; i < loops_per_jiffy; i++) {
1147 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1148 break;
1149 cpu_relax();
1150 }
1151}
1152
1153/*
1154 * Switch MMC interface voltage ... only relevant for MMC1.
1155 *
1156 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1157 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1158 * Some chips, like eMMC ones, use internal transceivers.
1159 */
1160static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1161{
1162 u32 reg_val = 0;
1163 int ret;
1164
1165 /* Disable the clocks */
1166 pm_runtime_put_sync(host->dev);
1167 if (host->got_dbclk)
1168 clk_disable(host->dbclk);
1169
1170 /* Turn the power off */
1171 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1172
1173 /* Turn the power ON with given VDD 1.8 or 3.0v */
1174 if (!ret)
1175 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1176 vdd);
1177 pm_runtime_get_sync(host->dev);
1178 if (host->got_dbclk)
1179 clk_enable(host->dbclk);
1180
1181 if (ret != 0)
1182 goto err;
1183
1184 OMAP_HSMMC_WRITE(host->base, HCTL,
1185 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1186 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1187
1188 /*
1189 * If a MMC dual voltage card is detected, the set_ios fn calls
1190 * this fn with VDD bit set for 1.8V. Upon card removal from the
1191 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1192 *
1193 * Cope with a bit of slop in the range ... per data sheets:
1194 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1195 * but recommended values are 1.71V to 1.89V
1196 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1197 * but recommended values are 2.7V to 3.3V
1198 *
1199 * Board setup code shouldn't permit anything very out-of-range.
1200 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1201 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1202 */
1203 if ((1 << vdd) <= MMC_VDD_23_24)
1204 reg_val |= SDVS18;
1205 else
1206 reg_val |= SDVS30;
1207
1208 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1209 set_sd_bus_power(host);
1210
1211 return 0;
1212err:
1213 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1214 return ret;
1215}
1216
1217/* Protect the card while the cover is open */
1218static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1219{
1220 if (!mmc_slot(host).get_cover_state)
1221 return;
1222
1223 host->reqs_blocked = 0;
1224 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1225 if (host->protect_card) {
1226 printk(KERN_INFO "%s: cover is closed, "
1227 "card is now accessible\n",
1228 mmc_hostname(host->mmc));
1229 host->protect_card = 0;
1230 }
1231 } else {
1232 if (!host->protect_card) {
1233 printk(KERN_INFO "%s: cover is open, "
1234 "card is now inaccessible\n",
1235 mmc_hostname(host->mmc));
1236 host->protect_card = 1;
1237 }
1238 }
1239}
1240
1241/*
1242 * Work Item to notify the core about card insertion/removal
1243 */
1244static void omap_hsmmc_detect(struct work_struct *work)
1245{
1246 struct omap_hsmmc_host *host =
1247 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1248 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1249 int carddetect;
1250
1251 if (host->suspended)
1252 return;
1253
1254 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1255
1256 if (slot->card_detect)
1257 carddetect = slot->card_detect(host->dev, host->slot_id);
1258 else {
1259 omap_hsmmc_protect_card(host);
1260 carddetect = -ENOSYS;
1261 }
1262
1263 if (carddetect)
1264 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1265 else
1266 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1267}
1268
1269/*
1270 * ISR for handling card insertion and removal
1271 */
1272static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1273{
1274 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1275
1276 if (host->suspended)
1277 return IRQ_HANDLED;
1278 schedule_work(&host->mmc_carddetect_work);
1279
1280 return IRQ_HANDLED;
1281}
1282
1283static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1284 struct mmc_data *data)
1285{
1286 int sync_dev;
1287
1288 if (data->flags & MMC_DATA_WRITE)
1289 sync_dev = host->dma_line_tx;
1290 else
1291 sync_dev = host->dma_line_rx;
1292 return sync_dev;
1293}
1294
1295static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1296 struct mmc_data *data,
1297 struct scatterlist *sgl)
1298{
1299 int blksz, nblk, dma_ch;
1300
1301 dma_ch = host->dma_ch;
1302 if (data->flags & MMC_DATA_WRITE) {
1303 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1304 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1305 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1306 sg_dma_address(sgl), 0, 0);
1307 } else {
1308 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1309 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1310 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1311 sg_dma_address(sgl), 0, 0);
1312 }
1313
1314 blksz = host->data->blksz;
1315 nblk = sg_dma_len(sgl) / blksz;
1316
1317 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1318 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1319 omap_hsmmc_get_dma_sync_dev(host, data),
1320 !(data->flags & MMC_DATA_WRITE));
1321
1322 omap_start_dma(dma_ch);
1323}
1324
1325/*
1326 * DMA call back function
1327 */
1328static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1329{
1330 struct omap_hsmmc_host *host = cb_data;
1331 struct mmc_data *data = host->mrq->data;
1332 int dma_ch, req_in_progress;
1333
1334 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1335 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1336 ch_status);
1337 return;
1338 }
1339
1340 spin_lock(&host->irq_lock);
1341 if (host->dma_ch < 0) {
1342 spin_unlock(&host->irq_lock);
1343 return;
1344 }
1345
1346 host->dma_sg_idx++;
1347 if (host->dma_sg_idx < host->dma_len) {
1348 /* Fire up the next transfer. */
1349 omap_hsmmc_config_dma_params(host, data,
1350 data->sg + host->dma_sg_idx);
1351 spin_unlock(&host->irq_lock);
1352 return;
1353 }
1354
1355 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1356 omap_hsmmc_get_dma_dir(host, data));
1357
1358 req_in_progress = host->req_in_progress;
1359 dma_ch = host->dma_ch;
1360 host->dma_ch = -1;
1361 spin_unlock(&host->irq_lock);
1362
1363 omap_free_dma(dma_ch);
1364
1365 /* If DMA has finished after TC, complete the request */
1366 if (!req_in_progress) {
1367 struct mmc_request *mrq = host->mrq;
1368
1369 host->mrq = NULL;
1370 mmc_request_done(host->mmc, mrq);
1371 }
1372}
1373
1374/*
1375 * Routine to configure and start DMA for the MMC card
1376 */
1377static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1378 struct mmc_request *req)
1379{
1380 int dma_ch = 0, ret = 0, i;
1381 struct mmc_data *data = req->data;
1382
1383 /* Sanity check: all the SG entries must be aligned by block size. */
1384 for (i = 0; i < data->sg_len; i++) {
1385 struct scatterlist *sgl;
1386
1387 sgl = data->sg + i;
1388 if (sgl->length % data->blksz)
1389 return -EINVAL;
1390 }
1391 if ((data->blksz % 4) != 0)
1392 /* REVISIT: The MMC buffer increments only when MSB is written.
1393 * Return error for blksz which is non multiple of four.
1394 */
1395 return -EINVAL;
1396
1397 BUG_ON(host->dma_ch != -1);
1398
1399 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1400 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1401 if (ret != 0) {
1402 dev_err(mmc_dev(host->mmc),
1403 "%s: omap_request_dma() failed with %d\n",
1404 mmc_hostname(host->mmc), ret);
1405 return ret;
1406 }
1407
1408 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1409 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1410 host->dma_ch = dma_ch;
1411 host->dma_sg_idx = 0;
1412
1413 omap_hsmmc_config_dma_params(host, data, data->sg);
1414
1415 return 0;
1416}
1417
1418static void set_data_timeout(struct omap_hsmmc_host *host,
1419 unsigned int timeout_ns,
1420 unsigned int timeout_clks)
1421{
1422 unsigned int timeout, cycle_ns;
1423 uint32_t reg, clkd, dto = 0;
1424
1425 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1426 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1427 if (clkd == 0)
1428 clkd = 1;
1429
1430 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1431 timeout = timeout_ns / cycle_ns;
1432 timeout += timeout_clks;
1433 if (timeout) {
1434 while ((timeout & 0x80000000) == 0) {
1435 dto += 1;
1436 timeout <<= 1;
1437 }
1438 dto = 31 - dto;
1439 timeout <<= 1;
1440 if (timeout && dto)
1441 dto += 1;
1442 if (dto >= 13)
1443 dto -= 13;
1444 else
1445 dto = 0;
1446 if (dto > 14)
1447 dto = 14;
1448 }
1449
1450 reg &= ~DTO_MASK;
1451 reg |= dto << DTO_SHIFT;
1452 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1453}
1454
1455/*
1456 * Configure block length for MMC/SD cards and initiate the transfer.
1457 */
1458static int
1459omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1460{
1461 int ret;
1462 host->data = req->data;
1463
1464 if (req->data == NULL) {
1465 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1466 /*
1467 * Set an arbitrary 100ms data timeout for commands with
1468 * busy signal.
1469 */
1470 if (req->cmd->flags & MMC_RSP_BUSY)
1471 set_data_timeout(host, 100000000U, 0);
1472 return 0;
1473 }
1474
1475 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1476 | (req->data->blocks << 16));
1477 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1478
1479 if (host->use_dma) {
1480 ret = omap_hsmmc_start_dma_transfer(host, req);
1481 if (ret != 0) {
1482 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1483 return ret;
1484 }
1485 }
1486 return 0;
1487}
1488
1489/*
1490 * Request function. for read/write operation
1491 */
1492static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1493{
1494 struct omap_hsmmc_host *host = mmc_priv(mmc);
1495 int err;
1496
1497 BUG_ON(host->req_in_progress);
1498 BUG_ON(host->dma_ch != -1);
1499 if (host->protect_card) {
1500 if (host->reqs_blocked < 3) {
1501 /*
1502 * Ensure the controller is left in a consistent
1503 * state by resetting the command and data state
1504 * machines.
1505 */
1506 omap_hsmmc_reset_controller_fsm(host, SRD);
1507 omap_hsmmc_reset_controller_fsm(host, SRC);
1508 host->reqs_blocked += 1;
1509 }
1510 req->cmd->error = -EBADF;
1511 if (req->data)
1512 req->data->error = -EBADF;
1513 req->cmd->retries = 0;
1514 mmc_request_done(mmc, req);
1515 return;
1516 } else if (host->reqs_blocked)
1517 host->reqs_blocked = 0;
1518 WARN_ON(host->mrq != NULL);
1519 host->mrq = req;
1520 err = omap_hsmmc_prepare_data(host, req);
1521 if (err) {
1522 req->cmd->error = err;
1523 if (req->data)
1524 req->data->error = err;
1525 host->mrq = NULL;
1526 mmc_request_done(mmc, req);
1527 return;
1528 }
1529
1530 omap_hsmmc_start_command(host, req->cmd, req->data);
1531}
1532
1533/* Routine to configure clock values. Exposed API to core */
1534static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1535{
1536 struct omap_hsmmc_host *host = mmc_priv(mmc);
1537 u16 dsor = 0;
1538 unsigned long regval;
1539 unsigned long timeout;
1540 u32 con;
1541 int do_send_init_stream = 0;
1542
1543 mmc_host_enable(host->mmc);
1544
1545 if (ios->power_mode != host->power_mode) {
1546 switch (ios->power_mode) {
1547 case MMC_POWER_OFF:
1548 mmc_slot(host).set_power(host->dev, host->slot_id,
1549 0, 0);
1550 host->vdd = 0;
1551 break;
1552 case MMC_POWER_UP:
1553 mmc_slot(host).set_power(host->dev, host->slot_id,
1554 1, ios->vdd);
1555 host->vdd = ios->vdd;
1556 break;
1557 case MMC_POWER_ON:
1558 do_send_init_stream = 1;
1559 break;
1560 }
1561 host->power_mode = ios->power_mode;
1562 }
1563
1564 /* FIXME: set registers based only on changes to ios */
1565
1566 con = OMAP_HSMMC_READ(host->base, CON);
1567 switch (mmc->ios.bus_width) {
1568 case MMC_BUS_WIDTH_8:
1569 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1570 break;
1571 case MMC_BUS_WIDTH_4:
1572 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1573 OMAP_HSMMC_WRITE(host->base, HCTL,
1574 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1575 break;
1576 case MMC_BUS_WIDTH_1:
1577 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1578 OMAP_HSMMC_WRITE(host->base, HCTL,
1579 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1580 break;
1581 }
1582
1583 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1584 /* Only MMC1 can interface at 3V without some flavor
1585 * of external transceiver; but they all handle 1.8V.
1586 */
1587 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1588 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1589 /*
1590 * The mmc_select_voltage fn of the core does
1591 * not seem to set the power_mode to
1592 * MMC_POWER_UP upon recalculating the voltage.
1593 * vdd 1.8v.
1594 */
1595 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1596 dev_dbg(mmc_dev(host->mmc),
1597 "Switch operation failed\n");
1598 }
1599 }
1600
1601 if (ios->clock) {
1602 dsor = host->master_clock / ios->clock;
1603 if (dsor < 1)
1604 dsor = 1;
1605
1606 if (host->master_clock / dsor > ios->clock)
1607 dsor++;
1608
1609 if (dsor > 250)
1610 dsor = 250;
1611 }
1612 omap_hsmmc_stop_clock(host);
1613 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1614 regval = regval & ~(CLKD_MASK);
1615 regval = regval | (dsor << 6) | (DTO << 16);
1616 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1617 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1618 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1619
1620 /* Wait till the ICS bit is set */
1621 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1622 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1623 && time_before(jiffies, timeout))
1624 msleep(1);
1625
1626 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1627 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1628
1629 if (do_send_init_stream)
1630 send_init_stream(host);
1631
1632 con = OMAP_HSMMC_READ(host->base, CON);
1633 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1634 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1635 else
1636 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1637
1638 if (host->power_mode == MMC_POWER_OFF)
1639 mmc_host_disable(host->mmc);
1640 else
1641 mmc_host_lazy_disable(host->mmc);
1642}
1643
1644static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1645{
1646 struct omap_hsmmc_host *host = mmc_priv(mmc);
1647
1648 if (!mmc_slot(host).card_detect)
1649 return -ENOSYS;
1650 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1651}
1652
1653static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1654{
1655 struct omap_hsmmc_host *host = mmc_priv(mmc);
1656
1657 if (!mmc_slot(host).get_ro)
1658 return -ENOSYS;
1659 return mmc_slot(host).get_ro(host->dev, 0);
1660}
1661
1662static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1663{
1664 struct omap_hsmmc_host *host = mmc_priv(mmc);
1665
1666 if (mmc_slot(host).init_card)
1667 mmc_slot(host).init_card(card);
1668}
1669
1670static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1671{
1672 u32 hctl, capa, value;
1673
1674 /* Only MMC1 supports 3.0V */
1675 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1676 hctl = SDVS30;
1677 capa = VS30 | VS18;
1678 } else {
1679 hctl = SDVS18;
1680 capa = VS18;
1681 }
1682
1683 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1684 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1685
1686 value = OMAP_HSMMC_READ(host->base, CAPA);
1687 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1688
1689 /* Set the controller to AUTO IDLE mode */
1690 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1691 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1692
1693 /* Set SD bus power bit */
1694 set_sd_bus_power(host);
1695}
1696
1697/*
1698 * Dynamic power saving handling, FSM:
1699 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1700 * ^___________| | |
1701 * |______________________|______________________|
1702 *
1703 * ENABLED: mmc host is fully functional
1704 * DISABLED: fclk is off
1705 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1706 * REGSLEEP: fclk is off, voltage regulator is asleep
1707 * OFF: fclk is off, voltage regulator is off
1708 *
1709 * Transition handlers return the timeout for the next state transition
1710 * or negative error.
1711 */
1712
1713enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1714
1715/* Handler for [ENABLED -> DISABLED] transition */
1716static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1717{
1718 pm_runtime_put_sync(host->dev);
1719
1720 host->dpm_state = DISABLED;
1721
1722 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1723
1724 if (host->power_mode == MMC_POWER_OFF)
1725 return 0;
1726
1727 return OMAP_MMC_SLEEP_TIMEOUT;
1728}
1729
1730/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1731static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1732{
1733 int err, new_state;
1734
1735 if (!mmc_try_claim_host(host->mmc))
1736 return 0;
1737
1738 pm_runtime_get_sync(host->dev);
1739
1740 if (mmc_card_can_sleep(host->mmc)) {
1741 err = mmc_card_sleep(host->mmc);
1742 if (err < 0) {
1743 pm_runtime_put_sync(host->dev);
1744 mmc_release_host(host->mmc);
1745 return err;
1746 }
1747 new_state = CARDSLEEP;
1748 } else {
1749 new_state = REGSLEEP;
1750 }
1751 if (mmc_slot(host).set_sleep)
1752 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1753 new_state == CARDSLEEP);
1754 /* FIXME: turn off bus power and perhaps interrupts too */
1755 pm_runtime_put_sync(host->dev);
1756 host->dpm_state = new_state;
1757
1758 mmc_release_host(host->mmc);
1759
1760 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1761 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1762
1763 if (mmc_slot(host).no_off)
1764 return 0;
1765
1766 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1767 mmc_slot(host).card_detect ||
1768 (mmc_slot(host).get_cover_state &&
1769 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1770 return OMAP_MMC_OFF_TIMEOUT;
1771
1772 return 0;
1773}
1774
1775/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1776static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1777{
1778 if (!mmc_try_claim_host(host->mmc))
1779 return 0;
1780
1781 if (mmc_slot(host).no_off)
1782 return 0;
1783
1784 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1785 mmc_slot(host).card_detect ||
1786 (mmc_slot(host).get_cover_state &&
1787 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1788 mmc_release_host(host->mmc);
1789 return 0;
1790 }
1791
1792 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1793 host->vdd = 0;
1794 host->power_mode = MMC_POWER_OFF;
1795
1796 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1797 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1798
1799 host->dpm_state = OFF;
1800
1801 mmc_release_host(host->mmc);
1802
1803 return 0;
1804}
1805
1806/* Handler for [DISABLED -> ENABLED] transition */
1807static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1808{
1809 pm_runtime_get_sync(host->dev);
1810
1811 host->dpm_state = ENABLED;
1812
1813 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1814
1815 return 0;
1816}
1817
1818/* Handler for [SLEEP -> ENABLED] transition */
1819static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1820{
1821 if (!mmc_try_claim_host(host->mmc))
1822 return 0;
1823
1824 pm_runtime_get_sync(host->dev);
1825
1826 if (mmc_slot(host).set_sleep)
1827 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1828 host->vdd, host->dpm_state == CARDSLEEP);
1829 if (mmc_card_can_sleep(host->mmc))
1830 mmc_card_awake(host->mmc);
1831
1832 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1833 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1834
1835 host->dpm_state = ENABLED;
1836
1837 mmc_release_host(host->mmc);
1838
1839 return 0;
1840}
1841
1842/* Handler for [OFF -> ENABLED] transition */
1843static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1844{
1845 pm_runtime_get_sync(host->dev);
1846
1847 omap_hsmmc_conf_bus_power(host);
1848 mmc_power_restore_host(host->mmc);
1849
1850 host->dpm_state = ENABLED;
1851
1852 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1853
1854 return 0;
1855}
1856
1857/*
1858 * Bring MMC host to ENABLED from any other PM state.
1859 */
1860static int omap_hsmmc_enable(struct mmc_host *mmc)
1861{
1862 struct omap_hsmmc_host *host = mmc_priv(mmc);
1863
1864 switch (host->dpm_state) {
1865 case DISABLED:
1866 return omap_hsmmc_disabled_to_enabled(host);
1867 case CARDSLEEP:
1868 case REGSLEEP:
1869 return omap_hsmmc_sleep_to_enabled(host);
1870 case OFF:
1871 return omap_hsmmc_off_to_enabled(host);
1872 default:
1873 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1874 return -EINVAL;
1875 }
1876}
1877
1878/*
1879 * Bring MMC host in PM state (one level deeper).
1880 */
1881static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1882{
1883 struct omap_hsmmc_host *host = mmc_priv(mmc);
1884
1885 switch (host->dpm_state) {
1886 case ENABLED: {
1887 int delay;
1888
1889 delay = omap_hsmmc_enabled_to_disabled(host);
1890 if (lazy || delay < 0)
1891 return delay;
1892 return 0;
1893 }
1894 case DISABLED:
1895 return omap_hsmmc_disabled_to_sleep(host);
1896 case CARDSLEEP:
1897 case REGSLEEP:
1898 return omap_hsmmc_sleep_to_off(host);
1899 default:
1900 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1901 return -EINVAL;
1902 }
1903}
1904
1905static int omap_hsmmc_enable_simple(struct mmc_host *mmc)
1906{
1907 struct omap_hsmmc_host *host = mmc_priv(mmc);
1908
1909 pm_runtime_get_sync(host->dev);
1910
1911 dev_dbg(mmc_dev(host->mmc), "enabled\n");
1912 return 0;
1913}
1914
1915static int omap_hsmmc_disable_simple(struct mmc_host *mmc, int lazy)
1916{
1917 struct omap_hsmmc_host *host = mmc_priv(mmc);
1918
1919 pm_runtime_put_sync(host->dev);
1920
1921 dev_dbg(mmc_dev(host->mmc), "idle\n");
1922 return 0;
1923}
1924
1925static const struct mmc_host_ops omap_hsmmc_ops = {
1926 .enable = omap_hsmmc_enable_simple,
1927 .disable = omap_hsmmc_disable_simple,
1928 .request = omap_hsmmc_request,
1929 .set_ios = omap_hsmmc_set_ios,
1930 .get_cd = omap_hsmmc_get_cd,
1931 .get_ro = omap_hsmmc_get_ro,
1932 .init_card = omap_hsmmc_init_card,
1933 /* NYET -- enable_sdio_irq */
1934};
1935
1936static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1937 .enable = omap_hsmmc_enable,
1938 .disable = omap_hsmmc_disable,
1939 .request = omap_hsmmc_request,
1940 .set_ios = omap_hsmmc_set_ios,
1941 .get_cd = omap_hsmmc_get_cd,
1942 .get_ro = omap_hsmmc_get_ro,
1943 .init_card = omap_hsmmc_init_card,
1944 /* NYET -- enable_sdio_irq */
1945};
1946
1947#ifdef CONFIG_DEBUG_FS
1948
1949static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1950{
1951 struct mmc_host *mmc = s->private;
1952 struct omap_hsmmc_host *host = mmc_priv(mmc);
1953
1954
1955 seq_printf(s, "mmc%d:\n"
1956 " enabled:\t%d\n"
1957 " dpm_state:\t%d\n"
1958 " nesting_cnt:\t%d\n"
1959 " ct",
1960 mmc->index, mmc->enabled ? 1 : 0,
1961 host->dpm_state, mmc->nesting_cnt);
1962
1963 if (host->suspended || host->dpm_state == OFF) {
1964 seq_printf(s, "host suspended, can't read registers\n");
1965 return 0;
1966 }
1967
1968 pm_runtime_get_sync(host->dev);
1969
1970 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1971 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1972 seq_printf(s, "CON:\t\t0x%08x\n",
1973 OMAP_HSMMC_READ(host->base, CON));
1974 seq_printf(s, "HCTL:\t\t0x%08x\n",
1975 OMAP_HSMMC_READ(host->base, HCTL));
1976 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1977 OMAP_HSMMC_READ(host->base, SYSCTL));
1978 seq_printf(s, "IE:\t\t0x%08x\n",
1979 OMAP_HSMMC_READ(host->base, IE));
1980 seq_printf(s, "ISE:\t\t0x%08x\n",
1981 OMAP_HSMMC_READ(host->base, ISE));
1982 seq_printf(s, "CAPA:\t\t0x%08x\n",
1983 OMAP_HSMMC_READ(host->base, CAPA));
1984
1985 pm_runtime_put_sync(host->dev);
1986
1987 return 0;
1988}
1989
1990static int omap_hsmmc_regs_open(struct inode *inode, st…Large files files are truncated, but you can click here to view the full file