/drivers/mfd/omap-usb-host.c

https://bitbucket.org/wisechild/galaxy-nexus · C · 904 lines · 685 code · 155 blank · 64 comment · 94 complexity · 42afdfe37450f54836656fbbe9114427 MD5 · raw file

  1. /**
  2. * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
  5. * Author: Keshava Munegowda <keshava_mgowda@ti.com>
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 of
  9. * the License as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/slab.h>
  22. #include <linux/delay.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/clk.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/spinlock.h>
  27. #include <linux/gpio.h>
  28. #include <plat/usb.h>
  29. #include <linux/pm_runtime.h>
  30. #define USBHS_DRIVER_NAME "usbhs_omap"
  31. #define OMAP_EHCI_DEVICE "ehci-omap"
  32. #define OMAP_OHCI_DEVICE "ohci-omap3"
  33. /* OMAP USBHOST Register addresses */
  34. /* TLL Register Set */
  35. #define OMAP_USBTLL_REVISION (0x00)
  36. #define OMAP_USBTLL_SYSCONFIG (0x10)
  37. #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
  38. #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
  39. #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
  40. #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
  41. #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
  42. #define OMAP_USBTLL_SYSSTATUS (0x14)
  43. #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
  44. #define OMAP_USBTLL_IRQSTATUS (0x18)
  45. #define OMAP_USBTLL_IRQENABLE (0x1C)
  46. #define OMAP_TLL_SHARED_CONF (0x30)
  47. #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
  48. #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
  49. #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
  50. #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
  51. #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
  52. #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
  53. #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
  54. #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
  55. #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
  56. #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
  57. #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
  58. #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
  59. #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
  60. #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
  61. #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
  62. #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
  63. #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
  64. #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
  65. #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
  66. #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
  67. #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
  68. #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
  69. #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
  70. #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
  71. #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
  72. #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
  73. #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
  74. #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
  75. #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
  76. #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
  77. #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
  78. #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
  79. #define OMAP_TLL_CHANNEL_COUNT 3
  80. #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
  81. #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
  82. #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
  83. /* UHH Register Set */
  84. #define OMAP_UHH_REVISION (0x00)
  85. #define OMAP_UHH_SYSCONFIG (0x10)
  86. #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
  87. #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
  88. #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
  89. #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
  90. #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
  91. #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
  92. #define OMAP_UHH_SYSSTATUS (0x14)
  93. #define OMAP_UHH_HOSTCONFIG (0x40)
  94. #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
  95. #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
  96. #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
  97. #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
  98. #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
  99. #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
  100. #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
  101. #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
  102. #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
  103. #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
  104. #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
  105. #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
  106. /* OMAP4-specific defines */
  107. #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
  108. #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
  109. #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
  110. #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
  111. #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
  112. #define OMAP4_P1_MODE_CLEAR (3 << 16)
  113. #define OMAP4_P1_MODE_TLL (1 << 16)
  114. #define OMAP4_P1_MODE_HSIC (3 << 16)
  115. #define OMAP4_P2_MODE_CLEAR (3 << 18)
  116. #define OMAP4_P2_MODE_TLL (1 << 18)
  117. #define OMAP4_P2_MODE_HSIC (3 << 18)
  118. #define OMAP_REV2_TLL_CHANNEL_COUNT 2
  119. #define OMAP_UHH_DEBUG_CSR (0x44)
  120. /* Values of UHH_REVISION - Note: these are not given in the TRM */
  121. #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
  122. #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
  123. #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
  124. #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
  125. #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
  126. #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
  127. #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
  128. struct usbhs_hcd_omap {
  129. struct clk *xclk60mhsp1_ck;
  130. struct clk *xclk60mhsp2_ck;
  131. struct clk *utmi_p1_fck;
  132. struct clk *usbhost_p1_fck;
  133. struct clk *usbtll_p1_fck;
  134. struct clk *utmi_p2_fck;
  135. struct clk *usbhost_p2_fck;
  136. struct clk *usbtll_p2_fck;
  137. struct clk *init_60m_fclk;
  138. void __iomem *uhh_base;
  139. void __iomem *tll_base;
  140. struct usbhs_omap_platform_data platdata;
  141. u32 usbhs_rev;
  142. spinlock_t lock;
  143. };
  144. /*-------------------------------------------------------------------------*/
  145. const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
  146. static u64 usbhs_dmamask = ~(u32)0;
  147. /*-------------------------------------------------------------------------*/
  148. static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
  149. {
  150. __raw_writel(val, base + reg);
  151. }
  152. static inline u32 usbhs_read(void __iomem *base, u32 reg)
  153. {
  154. return __raw_readl(base + reg);
  155. }
  156. static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
  157. {
  158. __raw_writeb(val, base + reg);
  159. }
  160. static inline u8 usbhs_readb(void __iomem *base, u8 reg)
  161. {
  162. return __raw_readb(base + reg);
  163. }
  164. /*-------------------------------------------------------------------------*/
  165. static struct platform_device *omap_usbhs_alloc_child(const char *name,
  166. struct resource *res, int num_resources, void *pdata,
  167. size_t pdata_size, struct device *dev)
  168. {
  169. struct platform_device *child;
  170. int ret;
  171. child = platform_device_alloc(name, 0);
  172. if (!child) {
  173. dev_err(dev, "platform_device_alloc %s failed\n", name);
  174. goto err_end;
  175. }
  176. ret = platform_device_add_resources(child, res, num_resources);
  177. if (ret) {
  178. dev_err(dev, "platform_device_add_resources failed\n");
  179. goto err_alloc;
  180. }
  181. ret = platform_device_add_data(child, pdata, pdata_size);
  182. if (ret) {
  183. dev_err(dev, "platform_device_add_data failed\n");
  184. goto err_alloc;
  185. }
  186. child->dev.dma_mask = &usbhs_dmamask;
  187. child->dev.coherent_dma_mask = 0xffffffff;
  188. child->dev.parent = dev;
  189. ret = platform_device_add(child);
  190. if (ret) {
  191. dev_err(dev, "platform_device_add failed\n");
  192. goto err_alloc;
  193. }
  194. return child;
  195. err_alloc:
  196. platform_device_put(child);
  197. err_end:
  198. return NULL;
  199. }
  200. static int omap_usbhs_alloc_children(struct platform_device *pdev)
  201. {
  202. struct device *dev = &pdev->dev;
  203. struct usbhs_hcd_omap *omap;
  204. struct ehci_hcd_omap_platform_data *ehci_data;
  205. struct ohci_hcd_omap_platform_data *ohci_data;
  206. struct platform_device *ehci;
  207. struct platform_device *ohci;
  208. struct resource *res;
  209. struct resource resources[2];
  210. int ret;
  211. omap = platform_get_drvdata(pdev);
  212. ehci_data = omap->platdata.ehci_data;
  213. ohci_data = omap->platdata.ohci_data;
  214. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
  215. if (!res) {
  216. dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
  217. ret = -ENODEV;
  218. goto err_end;
  219. }
  220. resources[0] = *res;
  221. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
  222. if (!res) {
  223. dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
  224. ret = -ENODEV;
  225. goto err_end;
  226. }
  227. resources[1] = *res;
  228. ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
  229. sizeof(*ehci_data), dev);
  230. if (!ehci) {
  231. dev_err(dev, "omap_usbhs_alloc_child failed\n");
  232. ret = -ENOMEM;
  233. goto err_end;
  234. }
  235. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
  236. if (!res) {
  237. dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
  238. ret = -ENODEV;
  239. goto err_ehci;
  240. }
  241. resources[0] = *res;
  242. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
  243. if (!res) {
  244. dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
  245. ret = -ENODEV;
  246. goto err_ehci;
  247. }
  248. resources[1] = *res;
  249. ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
  250. sizeof(*ohci_data), dev);
  251. if (!ohci) {
  252. dev_err(dev, "omap_usbhs_alloc_child failed\n");
  253. ret = -ENOMEM;
  254. goto err_ehci;
  255. }
  256. return 0;
  257. err_ehci:
  258. platform_device_unregister(ehci);
  259. err_end:
  260. return ret;
  261. }
  262. static void omap_usbhs_init(struct device *dev);
  263. /**
  264. * usbhs_omap_probe - initialize TI-based HCDs
  265. *
  266. * Allocates basic resources for this USB host controller.
  267. */
  268. static int __devinit usbhs_omap_probe(struct platform_device *pdev)
  269. {
  270. struct device *dev = &pdev->dev;
  271. struct usbhs_omap_platform_data *pdata = dev->platform_data;
  272. struct usbhs_hcd_omap *omap;
  273. struct resource *res;
  274. int ret = 0;
  275. int i;
  276. if (!pdata) {
  277. dev_err(dev, "Missing platform data\n");
  278. ret = -ENOMEM;
  279. goto end_probe;
  280. }
  281. omap = kzalloc(sizeof(*omap), GFP_KERNEL);
  282. if (!omap) {
  283. dev_err(dev, "Memory allocation failed\n");
  284. ret = -ENOMEM;
  285. goto end_probe;
  286. }
  287. spin_lock_init(&omap->lock);
  288. for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
  289. omap->platdata.port_mode[i] = pdata->port_mode[i];
  290. omap->platdata.ehci_data = pdata->ehci_data;
  291. omap->platdata.ohci_data = pdata->ohci_data;
  292. pm_runtime_enable(dev);
  293. omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
  294. if (IS_ERR(omap->utmi_p1_fck)) {
  295. ret = PTR_ERR(omap->utmi_p1_fck);
  296. dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
  297. goto err_end;
  298. }
  299. omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
  300. if (IS_ERR(omap->xclk60mhsp1_ck)) {
  301. ret = PTR_ERR(omap->xclk60mhsp1_ck);
  302. dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
  303. goto err_utmi_p1_fck;
  304. }
  305. omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
  306. if (IS_ERR(omap->utmi_p2_fck)) {
  307. ret = PTR_ERR(omap->utmi_p2_fck);
  308. dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
  309. goto err_xclk60mhsp1_ck;
  310. }
  311. omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
  312. if (IS_ERR(omap->xclk60mhsp2_ck)) {
  313. ret = PTR_ERR(omap->xclk60mhsp2_ck);
  314. dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
  315. goto err_utmi_p2_fck;
  316. }
  317. omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
  318. if (IS_ERR(omap->usbhost_p1_fck)) {
  319. ret = PTR_ERR(omap->usbhost_p1_fck);
  320. dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
  321. goto err_xclk60mhsp2_ck;
  322. }
  323. omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
  324. if (IS_ERR(omap->usbtll_p1_fck)) {
  325. ret = PTR_ERR(omap->usbtll_p1_fck);
  326. dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
  327. goto err_usbhost_p1_fck;
  328. }
  329. omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
  330. if (IS_ERR(omap->usbhost_p2_fck)) {
  331. ret = PTR_ERR(omap->usbhost_p2_fck);
  332. dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
  333. goto err_usbtll_p1_fck;
  334. }
  335. omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
  336. if (IS_ERR(omap->usbtll_p2_fck)) {
  337. ret = PTR_ERR(omap->usbtll_p2_fck);
  338. dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
  339. goto err_usbhost_p2_fck;
  340. }
  341. omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
  342. if (IS_ERR(omap->init_60m_fclk)) {
  343. ret = PTR_ERR(omap->init_60m_fclk);
  344. dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
  345. goto err_usbtll_p2_fck;
  346. }
  347. if (is_ehci_phy_mode(pdata->port_mode[0])) {
  348. /* for OMAP3 , the clk set paretn fails */
  349. ret = clk_set_parent(omap->utmi_p1_fck,
  350. omap->xclk60mhsp1_ck);
  351. if (ret != 0)
  352. dev_err(dev, "xclk60mhsp1_ck set parent"
  353. "failed error:%d\n", ret);
  354. } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
  355. ret = clk_set_parent(omap->utmi_p1_fck,
  356. omap->init_60m_fclk);
  357. if (ret != 0)
  358. dev_err(dev, "init_60m_fclk set parent"
  359. "failed error:%d\n", ret);
  360. }
  361. if (is_ehci_phy_mode(pdata->port_mode[1])) {
  362. ret = clk_set_parent(omap->utmi_p2_fck,
  363. omap->xclk60mhsp2_ck);
  364. if (ret != 0)
  365. dev_err(dev, "xclk60mhsp2_ck set parent"
  366. "failed error:%d\n", ret);
  367. } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
  368. ret = clk_set_parent(omap->utmi_p2_fck,
  369. omap->init_60m_fclk);
  370. if (ret != 0)
  371. dev_err(dev, "init_60m_fclk set parent"
  372. "failed error:%d\n", ret);
  373. }
  374. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
  375. if (!res) {
  376. dev_err(dev, "UHH EHCI get resource failed\n");
  377. ret = -ENODEV;
  378. goto err_init_60m_fclk;
  379. }
  380. omap->uhh_base = ioremap(res->start, resource_size(res));
  381. if (!omap->uhh_base) {
  382. dev_err(dev, "UHH ioremap failed\n");
  383. ret = -ENOMEM;
  384. goto err_init_60m_fclk;
  385. }
  386. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
  387. if (!res) {
  388. dev_err(dev, "UHH EHCI get resource failed\n");
  389. ret = -ENODEV;
  390. goto err_tll;
  391. }
  392. omap->tll_base = ioremap(res->start, resource_size(res));
  393. if (!omap->tll_base) {
  394. dev_err(dev, "TLL ioremap failed\n");
  395. ret = -ENOMEM;
  396. goto err_tll;
  397. }
  398. platform_set_drvdata(pdev, omap);
  399. ret = omap_usbhs_alloc_children(pdev);
  400. if (ret) {
  401. dev_err(dev, "omap_usbhs_alloc_children failed\n");
  402. goto err_alloc;
  403. }
  404. omap_usbhs_init(dev);
  405. goto end_probe;
  406. err_alloc:
  407. iounmap(omap->tll_base);
  408. err_tll:
  409. iounmap(omap->uhh_base);
  410. err_init_60m_fclk:
  411. clk_put(omap->init_60m_fclk);
  412. err_usbtll_p2_fck:
  413. clk_put(omap->usbtll_p2_fck);
  414. err_usbhost_p2_fck:
  415. clk_put(omap->usbhost_p2_fck);
  416. err_usbtll_p1_fck:
  417. clk_put(omap->usbtll_p1_fck);
  418. err_usbhost_p1_fck:
  419. clk_put(omap->usbhost_p1_fck);
  420. err_xclk60mhsp2_ck:
  421. clk_put(omap->xclk60mhsp2_ck);
  422. err_utmi_p2_fck:
  423. clk_put(omap->utmi_p2_fck);
  424. err_xclk60mhsp1_ck:
  425. clk_put(omap->xclk60mhsp1_ck);
  426. err_utmi_p1_fck:
  427. clk_put(omap->utmi_p1_fck);
  428. err_end:
  429. pm_runtime_disable(dev);
  430. kfree(omap);
  431. end_probe:
  432. return ret;
  433. }
  434. static void omap_usbhs_deinit(struct device *dev);
  435. /**
  436. * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
  437. * @pdev: USB Host Controller being removed
  438. *
  439. * Reverses the effect of usbhs_omap_probe().
  440. */
  441. static int __devexit usbhs_omap_remove(struct platform_device *pdev)
  442. {
  443. struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
  444. omap_usbhs_deinit(&pdev->dev);
  445. iounmap(omap->tll_base);
  446. iounmap(omap->uhh_base);
  447. clk_put(omap->init_60m_fclk);
  448. clk_put(omap->usbtll_p2_fck);
  449. clk_put(omap->usbhost_p2_fck);
  450. clk_put(omap->usbtll_p1_fck);
  451. clk_put(omap->usbhost_p1_fck);
  452. clk_put(omap->xclk60mhsp2_ck);
  453. clk_put(omap->utmi_p2_fck);
  454. clk_put(omap->xclk60mhsp1_ck);
  455. clk_put(omap->utmi_p1_fck);
  456. pm_runtime_disable(&pdev->dev);
  457. kfree(omap);
  458. return 0;
  459. }
  460. static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
  461. {
  462. switch (pmode) {
  463. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
  464. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
  465. case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
  466. case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
  467. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
  468. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
  469. case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
  470. case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
  471. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
  472. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
  473. return true;
  474. default:
  475. return false;
  476. }
  477. }
  478. /*
  479. * convert the port-mode enum to a value we can use in the FSLSMODE
  480. * field of USBTLL_CHANNEL_CONF
  481. */
  482. static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
  483. {
  484. switch (mode) {
  485. case OMAP_USBHS_PORT_MODE_UNUSED:
  486. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
  487. return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
  488. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
  489. return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
  490. case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
  491. return OMAP_TLL_FSLSMODE_3PIN_PHY;
  492. case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
  493. return OMAP_TLL_FSLSMODE_4PIN_PHY;
  494. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
  495. return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
  496. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
  497. return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
  498. case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
  499. return OMAP_TLL_FSLSMODE_3PIN_TLL;
  500. case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
  501. return OMAP_TLL_FSLSMODE_4PIN_TLL;
  502. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
  503. return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
  504. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
  505. return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
  506. default:
  507. pr_warning("Invalid port mode, using default\n");
  508. return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
  509. }
  510. }
  511. static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
  512. {
  513. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  514. struct usbhs_omap_platform_data *pdata = dev->platform_data;
  515. unsigned reg;
  516. int i;
  517. /* Program Common TLL register */
  518. reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
  519. reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
  520. | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
  521. reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
  522. reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
  523. usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
  524. /* Enable channels now */
  525. for (i = 0; i < tll_channel_count; i++) {
  526. reg = usbhs_read(omap->tll_base,
  527. OMAP_TLL_CHANNEL_CONF(i));
  528. if (is_ohci_port(pdata->port_mode[i])) {
  529. reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
  530. << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
  531. reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
  532. } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
  533. /* Disable AutoIdle, BitStuffing and use SDR Mode */
  534. reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
  535. | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
  536. | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
  537. } else
  538. continue;
  539. reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
  540. usbhs_write(omap->tll_base,
  541. OMAP_TLL_CHANNEL_CONF(i), reg);
  542. usbhs_writeb(omap->tll_base,
  543. OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
  544. }
  545. }
  546. static int usbhs_runtime_resume(struct device *dev)
  547. {
  548. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  549. struct usbhs_omap_platform_data *pdata = &omap->platdata;
  550. dev_dbg(dev, "usbhs_runtime_resume\n");
  551. if (!pdata) {
  552. dev_dbg(dev, "missing platform_data\n");
  553. return -ENODEV;
  554. }
  555. if (is_omap_usbhs_rev2(omap)) {
  556. if (is_ehci_tll_mode(pdata->port_mode[0])) {
  557. clk_enable(omap->usbhost_p1_fck);
  558. clk_enable(omap->usbtll_p1_fck);
  559. }
  560. if (is_ehci_tll_mode(pdata->port_mode[1])) {
  561. clk_enable(omap->usbhost_p2_fck);
  562. clk_enable(omap->usbtll_p2_fck);
  563. }
  564. clk_enable(omap->utmi_p1_fck);
  565. clk_enable(omap->utmi_p2_fck);
  566. }
  567. return 0;
  568. }
  569. static int usbhs_runtime_suspend(struct device *dev)
  570. {
  571. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  572. struct usbhs_omap_platform_data *pdata = &omap->platdata;
  573. dev_dbg(dev, "usbhs_runtime_suspend\n");
  574. if (!pdata) {
  575. dev_dbg(dev, "missing platform_data\n");
  576. return -ENODEV;
  577. }
  578. if (is_omap_usbhs_rev2(omap)) {
  579. if (is_ehci_tll_mode(pdata->port_mode[0])) {
  580. clk_disable(omap->usbhost_p1_fck);
  581. clk_disable(omap->usbtll_p1_fck);
  582. }
  583. if (is_ehci_tll_mode(pdata->port_mode[1])) {
  584. clk_disable(omap->usbhost_p2_fck);
  585. clk_disable(omap->usbtll_p2_fck);
  586. }
  587. clk_disable(omap->utmi_p2_fck);
  588. clk_disable(omap->utmi_p1_fck);
  589. }
  590. return 0;
  591. }
  592. static void omap_usbhs_init(struct device *dev)
  593. {
  594. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  595. struct usbhs_omap_platform_data *pdata = &omap->platdata;
  596. unsigned long flags = 0;
  597. unsigned reg;
  598. dev_dbg(dev, "starting TI HSUSB Controller\n");
  599. pm_runtime_get_sync(dev);
  600. spin_lock_irqsave(&omap->lock, flags);
  601. if (pdata->ehci_data->phy_reset) {
  602. if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
  603. gpio_request(pdata->ehci_data->reset_gpio_port[0],
  604. "USB1 PHY reset");
  605. gpio_direction_output
  606. (pdata->ehci_data->reset_gpio_port[0], 0);
  607. }
  608. if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) {
  609. gpio_request(pdata->ehci_data->reset_gpio_port[1],
  610. "USB2 PHY reset");
  611. gpio_direction_output
  612. (pdata->ehci_data->reset_gpio_port[1], 0);
  613. }
  614. /* Hold the PHY in RESET for enough time till DIR is high */
  615. udelay(10);
  616. }
  617. omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
  618. dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
  619. /*
  620. * Really enable the port clocks
  621. * first call of pm_runtime_get_sync does not enable these
  622. * port clocks; because omap->usbhs_rev was not available
  623. * This omap->usbhs_rev is available now!
  624. */
  625. usbhs_runtime_resume(dev);
  626. reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
  627. /* setup ULPI bypass and burst configurations */
  628. reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
  629. | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
  630. | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN
  631. | OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN);
  632. if (is_omap_usbhs_rev1(omap)) {
  633. if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
  634. reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
  635. if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
  636. reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
  637. if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
  638. reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
  639. /* Bypass the TLL module for PHY mode operation */
  640. if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
  641. dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
  642. if (is_ehci_phy_mode(pdata->port_mode[0]) ||
  643. is_ehci_phy_mode(pdata->port_mode[1]) ||
  644. is_ehci_phy_mode(pdata->port_mode[2]))
  645. reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
  646. else
  647. reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
  648. } else {
  649. dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
  650. if (is_ehci_phy_mode(pdata->port_mode[0]))
  651. reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
  652. else
  653. reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
  654. if (is_ehci_phy_mode(pdata->port_mode[1]))
  655. reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
  656. else
  657. reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
  658. if (is_ehci_phy_mode(pdata->port_mode[2]))
  659. reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
  660. else
  661. reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
  662. }
  663. } else if (is_omap_usbhs_rev2(omap)) {
  664. /* Clear port mode fields for PHY mode*/
  665. reg &= ~OMAP4_P1_MODE_CLEAR;
  666. reg &= ~OMAP4_P2_MODE_CLEAR;
  667. if (is_ehci_tll_mode(pdata->port_mode[0]) ||
  668. (is_ohci_port(pdata->port_mode[0])))
  669. reg |= OMAP4_P1_MODE_TLL;
  670. else if (is_ehci_hsic_mode(pdata->port_mode[0]))
  671. reg |= OMAP4_P1_MODE_HSIC;
  672. if (is_ehci_tll_mode(pdata->port_mode[1]) ||
  673. (is_ohci_port(pdata->port_mode[1])))
  674. reg |= OMAP4_P2_MODE_TLL;
  675. else if (is_ehci_hsic_mode(pdata->port_mode[1]))
  676. reg |= OMAP4_P2_MODE_HSIC;
  677. }
  678. usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
  679. dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
  680. if (is_ehci_tll_mode(pdata->port_mode[0]) ||
  681. is_ehci_tll_mode(pdata->port_mode[1]) ||
  682. is_ehci_tll_mode(pdata->port_mode[2]) ||
  683. (is_ohci_port(pdata->port_mode[0])) ||
  684. (is_ohci_port(pdata->port_mode[1])) ||
  685. (is_ohci_port(pdata->port_mode[2]))) {
  686. /* Enable UTMI mode for required TLL channels */
  687. if (is_omap_usbhs_rev2(omap))
  688. usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
  689. else
  690. usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
  691. }
  692. if (pdata->ehci_data->phy_reset) {
  693. /* Hold the PHY in RESET for enough time till
  694. * PHY is settled and ready
  695. */
  696. udelay(10);
  697. if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
  698. gpio_set_value
  699. (pdata->ehci_data->reset_gpio_port[0], 1);
  700. if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
  701. gpio_set_value
  702. (pdata->ehci_data->reset_gpio_port[1], 1);
  703. }
  704. spin_unlock_irqrestore(&omap->lock, flags);
  705. pm_runtime_put_sync(dev);
  706. }
  707. static void omap_usbhs_deinit(struct device *dev)
  708. {
  709. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  710. struct usbhs_omap_platform_data *pdata = &omap->platdata;
  711. dev_dbg(dev, "stopping TI HSUSB Controller\n");
  712. if (pdata->ehci_data->phy_reset) {
  713. if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
  714. gpio_free(pdata->ehci_data->reset_gpio_port[0]);
  715. if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
  716. gpio_free(pdata->ehci_data->reset_gpio_port[1]);
  717. }
  718. }
  719. static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
  720. .runtime_suspend = usbhs_runtime_suspend,
  721. .runtime_resume = usbhs_runtime_resume,
  722. };
  723. static struct platform_driver usbhs_omap_driver = {
  724. .driver = {
  725. .name = (char *)usbhs_driver_name,
  726. .owner = THIS_MODULE,
  727. .pm = &usbhsomap_dev_pm_ops,
  728. },
  729. .remove = __exit_p(usbhs_omap_remove),
  730. };
  731. MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
  732. MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
  733. MODULE_LICENSE("GPL v2");
  734. MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
  735. static int __init omap_usbhs_drvinit(void)
  736. {
  737. return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
  738. }
  739. /*
  740. * init before ehci and ohci drivers;
  741. * The usbhs core driver should be initialized much before
  742. * the omap ehci and ohci probe functions are called.
  743. */
  744. fs_initcall(omap_usbhs_drvinit);
  745. static void __exit omap_usbhs_drvexit(void)
  746. {
  747. platform_driver_unregister(&usbhs_omap_driver);
  748. }
  749. module_exit(omap_usbhs_drvexit);