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/drivers/mfd/omap-usb-host.c

https://bitbucket.org/wisechild/galaxy-nexus
C | 904 lines | 685 code | 155 blank | 64 comment | 94 complexity | 42afdfe37450f54836656fbbe9114427 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/**
  2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
  3 *
  4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
  5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
  6 *
  7 * This program is free software: you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License version 2  of
  9 * the License as published by the Free Software Foundation.
 10 *
 11 * This program is distributed in the hope that it will be useful,
 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14 * GNU General Public License for more details.
 15 *
 16 * You should have received a copy of the GNU General Public License
 17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 18 */
 19#include <linux/kernel.h>
 20#include <linux/types.h>
 21#include <linux/slab.h>
 22#include <linux/delay.h>
 23#include <linux/platform_device.h>
 24#include <linux/clk.h>
 25#include <linux/dma-mapping.h>
 26#include <linux/spinlock.h>
 27#include <linux/gpio.h>
 28#include <plat/usb.h>
 29#include <linux/pm_runtime.h>
 30
 31#define USBHS_DRIVER_NAME	"usbhs_omap"
 32#define OMAP_EHCI_DEVICE	"ehci-omap"
 33#define OMAP_OHCI_DEVICE	"ohci-omap3"
 34
 35/* OMAP USBHOST Register addresses  */
 36
 37/* TLL Register Set */
 38#define	OMAP_USBTLL_REVISION				(0x00)
 39#define	OMAP_USBTLL_SYSCONFIG				(0x10)
 40#define	OMAP_USBTLL_SYSCONFIG_CACTIVITY			(1 << 8)
 41#define	OMAP_USBTLL_SYSCONFIG_SIDLEMODE			(1 << 3)
 42#define	OMAP_USBTLL_SYSCONFIG_ENAWAKEUP			(1 << 2)
 43#define	OMAP_USBTLL_SYSCONFIG_SOFTRESET			(1 << 1)
 44#define	OMAP_USBTLL_SYSCONFIG_AUTOIDLE			(1 << 0)
 45
 46#define	OMAP_USBTLL_SYSSTATUS				(0x14)
 47#define	OMAP_USBTLL_SYSSTATUS_RESETDONE			(1 << 0)
 48
 49#define	OMAP_USBTLL_IRQSTATUS				(0x18)
 50#define	OMAP_USBTLL_IRQENABLE				(0x1C)
 51
 52#define	OMAP_TLL_SHARED_CONF				(0x30)
 53#define	OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN		(1 << 6)
 54#define	OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN		(1 << 5)
 55#define	OMAP_TLL_SHARED_CONF_USB_DIVRATION		(1 << 2)
 56#define	OMAP_TLL_SHARED_CONF_FCLK_REQ			(1 << 1)
 57#define	OMAP_TLL_SHARED_CONF_FCLK_IS_ON			(1 << 0)
 58
 59#define	OMAP_TLL_CHANNEL_CONF(num)			(0x040 + 0x004 * num)
 60#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT		24
 61#define	OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF		(1 << 11)
 62#define	OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE		(1 << 10)
 63#define	OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE		(1 << 9)
 64#define	OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE		(1 << 8)
 65#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS		(1 << 1)
 66#define	OMAP_TLL_CHANNEL_CONF_CHANEN			(1 << 0)
 67
 68#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0		0x0
 69#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM		0x1
 70#define OMAP_TLL_FSLSMODE_3PIN_PHY			0x2
 71#define OMAP_TLL_FSLSMODE_4PIN_PHY			0x3
 72#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0		0x4
 73#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM		0x5
 74#define OMAP_TLL_FSLSMODE_3PIN_TLL			0x6
 75#define OMAP_TLL_FSLSMODE_4PIN_TLL			0x7
 76#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0		0xA
 77#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM		0xB
 78
 79#define	OMAP_TLL_ULPI_FUNCTION_CTRL(num)		(0x804 + 0x100 * num)
 80#define	OMAP_TLL_ULPI_INTERFACE_CTRL(num)		(0x807 + 0x100 * num)
 81#define	OMAP_TLL_ULPI_OTG_CTRL(num)			(0x80A + 0x100 * num)
 82#define	OMAP_TLL_ULPI_INT_EN_RISE(num)			(0x80D + 0x100 * num)
 83#define	OMAP_TLL_ULPI_INT_EN_FALL(num)			(0x810 + 0x100 * num)
 84#define	OMAP_TLL_ULPI_INT_STATUS(num)			(0x813 + 0x100 * num)
 85#define	OMAP_TLL_ULPI_INT_LATCH(num)			(0x814 + 0x100 * num)
 86#define	OMAP_TLL_ULPI_DEBUG(num)			(0x815 + 0x100 * num)
 87#define	OMAP_TLL_ULPI_SCRATCH_REGISTER(num)		(0x816 + 0x100 * num)
 88
 89#define OMAP_TLL_CHANNEL_COUNT				3
 90#define OMAP_TLL_CHANNEL_1_EN_MASK			(1 << 0)
 91#define OMAP_TLL_CHANNEL_2_EN_MASK			(1 << 1)
 92#define OMAP_TLL_CHANNEL_3_EN_MASK			(1 << 2)
 93
 94/* UHH Register Set */
 95#define	OMAP_UHH_REVISION				(0x00)
 96#define	OMAP_UHH_SYSCONFIG				(0x10)
 97#define	OMAP_UHH_SYSCONFIG_MIDLEMODE			(1 << 12)
 98#define	OMAP_UHH_SYSCONFIG_CACTIVITY			(1 << 8)
 99#define	OMAP_UHH_SYSCONFIG_SIDLEMODE			(1 << 3)
100#define	OMAP_UHH_SYSCONFIG_ENAWAKEUP			(1 << 2)
101#define	OMAP_UHH_SYSCONFIG_SOFTRESET			(1 << 1)
102#define	OMAP_UHH_SYSCONFIG_AUTOIDLE			(1 << 0)
103
104#define	OMAP_UHH_SYSSTATUS				(0x14)
105#define	OMAP_UHH_HOSTCONFIG				(0x40)
106#define	OMAP_UHH_HOSTCONFIG_ULPI_BYPASS			(1 << 0)
107#define	OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS		(1 << 0)
108#define	OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS		(1 << 11)
109#define	OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS		(1 << 12)
110#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN		(1 << 2)
111#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN		(1 << 3)
112#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN		(1 << 4)
113#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN		(1 << 5)
114#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS		(1 << 8)
115#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS		(1 << 9)
116#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS		(1 << 10)
117#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK		(1 << 31)
118
119/* OMAP4-specific defines */
120#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR		(3 << 2)
121#define OMAP4_UHH_SYSCONFIG_NOIDLE			(1 << 2)
122#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR		(3 << 4)
123#define OMAP4_UHH_SYSCONFIG_NOSTDBY			(1 << 4)
124#define OMAP4_UHH_SYSCONFIG_SOFTRESET			(1 << 0)
125
126#define OMAP4_P1_MODE_CLEAR				(3 << 16)
127#define OMAP4_P1_MODE_TLL				(1 << 16)
128#define OMAP4_P1_MODE_HSIC				(3 << 16)
129#define OMAP4_P2_MODE_CLEAR				(3 << 18)
130#define OMAP4_P2_MODE_TLL				(1 << 18)
131#define OMAP4_P2_MODE_HSIC				(3 << 18)
132
133#define OMAP_REV2_TLL_CHANNEL_COUNT			2
134
135#define	OMAP_UHH_DEBUG_CSR				(0x44)
136
137/* Values of UHH_REVISION - Note: these are not given in the TRM */
138#define OMAP_USBHS_REV1		0x00000010	/* OMAP3 */
139#define OMAP_USBHS_REV2		0x50700100	/* OMAP4 */
140
141#define is_omap_usbhs_rev1(x)	(x->usbhs_rev == OMAP_USBHS_REV1)
142#define is_omap_usbhs_rev2(x)	(x->usbhs_rev == OMAP_USBHS_REV2)
143
144#define is_ehci_phy_mode(x)	(x == OMAP_EHCI_PORT_MODE_PHY)
145#define is_ehci_tll_mode(x)	(x == OMAP_EHCI_PORT_MODE_TLL)
146#define is_ehci_hsic_mode(x)	(x == OMAP_EHCI_PORT_MODE_HSIC)
147
148
149struct usbhs_hcd_omap {
150	struct clk			*xclk60mhsp1_ck;
151	struct clk			*xclk60mhsp2_ck;
152	struct clk			*utmi_p1_fck;
153	struct clk			*usbhost_p1_fck;
154	struct clk			*usbtll_p1_fck;
155	struct clk			*utmi_p2_fck;
156	struct clk			*usbhost_p2_fck;
157	struct clk			*usbtll_p2_fck;
158	struct clk			*init_60m_fclk;
159
160	void __iomem			*uhh_base;
161	void __iomem			*tll_base;
162
163	struct usbhs_omap_platform_data	platdata;
164
165	u32				usbhs_rev;
166	spinlock_t			lock;
167};
168/*-------------------------------------------------------------------------*/
169
170const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
171static u64 usbhs_dmamask = ~(u32)0;
172
173/*-------------------------------------------------------------------------*/
174
175static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
176{
177	__raw_writel(val, base + reg);
178}
179
180static inline u32 usbhs_read(void __iomem *base, u32 reg)
181{
182	return __raw_readl(base + reg);
183}
184
185static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
186{
187	__raw_writeb(val, base + reg);
188}
189
190static inline u8 usbhs_readb(void __iomem *base, u8 reg)
191{
192	return __raw_readb(base + reg);
193}
194
195/*-------------------------------------------------------------------------*/
196
197static struct platform_device *omap_usbhs_alloc_child(const char *name,
198			struct resource	*res, int num_resources, void *pdata,
199			size_t pdata_size, struct device *dev)
200{
201	struct platform_device	*child;
202	int			ret;
203
204	child = platform_device_alloc(name, 0);
205
206	if (!child) {
207		dev_err(dev, "platform_device_alloc %s failed\n", name);
208		goto err_end;
209	}
210
211	ret = platform_device_add_resources(child, res, num_resources);
212	if (ret) {
213		dev_err(dev, "platform_device_add_resources failed\n");
214		goto err_alloc;
215	}
216
217	ret = platform_device_add_data(child, pdata, pdata_size);
218	if (ret) {
219		dev_err(dev, "platform_device_add_data failed\n");
220		goto err_alloc;
221	}
222
223	child->dev.dma_mask		= &usbhs_dmamask;
224	child->dev.coherent_dma_mask	= 0xffffffff;
225	child->dev.parent		= dev;
226
227	ret = platform_device_add(child);
228	if (ret) {
229		dev_err(dev, "platform_device_add failed\n");
230		goto err_alloc;
231	}
232
233	return child;
234
235err_alloc:
236	platform_device_put(child);
237
238err_end:
239	return NULL;
240}
241
242static int omap_usbhs_alloc_children(struct platform_device *pdev)
243{
244	struct device				*dev = &pdev->dev;
245	struct usbhs_hcd_omap			*omap;
246	struct ehci_hcd_omap_platform_data	*ehci_data;
247	struct ohci_hcd_omap_platform_data	*ohci_data;
248	struct platform_device			*ehci;
249	struct platform_device			*ohci;
250	struct resource				*res;
251	struct resource				resources[2];
252	int					ret;
253
254	omap = platform_get_drvdata(pdev);
255	ehci_data = omap->platdata.ehci_data;
256	ohci_data = omap->platdata.ohci_data;
257
258	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
259	if (!res) {
260		dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
261		ret = -ENODEV;
262		goto err_end;
263	}
264	resources[0] = *res;
265
266	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
267	if (!res) {
268		dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
269		ret = -ENODEV;
270		goto err_end;
271	}
272	resources[1] = *res;
273
274	ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
275		sizeof(*ehci_data), dev);
276
277	if (!ehci) {
278		dev_err(dev, "omap_usbhs_alloc_child failed\n");
279		ret = -ENOMEM;
280		goto err_end;
281	}
282
283	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
284	if (!res) {
285		dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
286		ret = -ENODEV;
287		goto err_ehci;
288	}
289	resources[0] = *res;
290
291	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
292	if (!res) {
293		dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
294		ret = -ENODEV;
295		goto err_ehci;
296	}
297	resources[1] = *res;
298
299	ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
300		sizeof(*ohci_data), dev);
301	if (!ohci) {
302		dev_err(dev, "omap_usbhs_alloc_child failed\n");
303		ret = -ENOMEM;
304		goto err_ehci;
305	}
306
307	return 0;
308
309err_ehci:
310	platform_device_unregister(ehci);
311
312err_end:
313	return ret;
314}
315
316static void omap_usbhs_init(struct device *dev);
317/**
318 * usbhs_omap_probe - initialize TI-based HCDs
319 *
320 * Allocates basic resources for this USB host controller.
321 */
322static int __devinit usbhs_omap_probe(struct platform_device *pdev)
323{
324	struct device			*dev =  &pdev->dev;
325	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
326	struct usbhs_hcd_omap		*omap;
327	struct resource			*res;
328	int				ret = 0;
329	int				i;
330
331	if (!pdata) {
332		dev_err(dev, "Missing platform data\n");
333		ret = -ENOMEM;
334		goto end_probe;
335	}
336
337	omap = kzalloc(sizeof(*omap), GFP_KERNEL);
338	if (!omap) {
339		dev_err(dev, "Memory allocation failed\n");
340		ret = -ENOMEM;
341		goto end_probe;
342	}
343
344	spin_lock_init(&omap->lock);
345
346	for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
347		omap->platdata.port_mode[i] = pdata->port_mode[i];
348
349	omap->platdata.ehci_data = pdata->ehci_data;
350	omap->platdata.ohci_data = pdata->ohci_data;
351
352	pm_runtime_enable(dev);
353
354	omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
355	if (IS_ERR(omap->utmi_p1_fck)) {
356		ret = PTR_ERR(omap->utmi_p1_fck);
357		dev_err(dev, "utmi_p1_gfclk failed error:%d\n",	ret);
358		goto err_end;
359	}
360
361	omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
362	if (IS_ERR(omap->xclk60mhsp1_ck)) {
363		ret = PTR_ERR(omap->xclk60mhsp1_ck);
364		dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
365		goto err_utmi_p1_fck;
366	}
367
368	omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
369	if (IS_ERR(omap->utmi_p2_fck)) {
370		ret = PTR_ERR(omap->utmi_p2_fck);
371		dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
372		goto err_xclk60mhsp1_ck;
373	}
374
375	omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
376	if (IS_ERR(omap->xclk60mhsp2_ck)) {
377		ret = PTR_ERR(omap->xclk60mhsp2_ck);
378		dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
379		goto err_utmi_p2_fck;
380	}
381
382	omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
383	if (IS_ERR(omap->usbhost_p1_fck)) {
384		ret = PTR_ERR(omap->usbhost_p1_fck);
385		dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
386		goto err_xclk60mhsp2_ck;
387	}
388
389	omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
390	if (IS_ERR(omap->usbtll_p1_fck)) {
391		ret = PTR_ERR(omap->usbtll_p1_fck);
392		dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
393		goto err_usbhost_p1_fck;
394	}
395
396	omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
397	if (IS_ERR(omap->usbhost_p2_fck)) {
398		ret = PTR_ERR(omap->usbhost_p2_fck);
399		dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
400		goto err_usbtll_p1_fck;
401	}
402
403	omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
404	if (IS_ERR(omap->usbtll_p2_fck)) {
405		ret = PTR_ERR(omap->usbtll_p2_fck);
406		dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
407		goto err_usbhost_p2_fck;
408	}
409
410	omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
411	if (IS_ERR(omap->init_60m_fclk)) {
412		ret = PTR_ERR(omap->init_60m_fclk);
413		dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
414		goto err_usbtll_p2_fck;
415	}
416
417	if (is_ehci_phy_mode(pdata->port_mode[0])) {
418		/* for OMAP3 , the clk set paretn fails */
419		ret = clk_set_parent(omap->utmi_p1_fck,
420					omap->xclk60mhsp1_ck);
421		if (ret != 0)
422			dev_err(dev, "xclk60mhsp1_ck set parent"
423				"failed error:%d\n", ret);
424	} else if (is_ehci_tll_mode(pdata->port_mode[0])) {
425		ret = clk_set_parent(omap->utmi_p1_fck,
426					omap->init_60m_fclk);
427		if (ret != 0)
428			dev_err(dev, "init_60m_fclk set parent"
429				"failed error:%d\n", ret);
430	}
431
432	if (is_ehci_phy_mode(pdata->port_mode[1])) {
433		ret = clk_set_parent(omap->utmi_p2_fck,
434					omap->xclk60mhsp2_ck);
435		if (ret != 0)
436			dev_err(dev, "xclk60mhsp2_ck set parent"
437					"failed error:%d\n", ret);
438	} else if (is_ehci_tll_mode(pdata->port_mode[1])) {
439		ret = clk_set_parent(omap->utmi_p2_fck,
440						omap->init_60m_fclk);
441		if (ret != 0)
442			dev_err(dev, "init_60m_fclk set parent"
443				"failed error:%d\n", ret);
444	}
445
446	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
447	if (!res) {
448		dev_err(dev, "UHH EHCI get resource failed\n");
449		ret = -ENODEV;
450		goto err_init_60m_fclk;
451	}
452
453	omap->uhh_base = ioremap(res->start, resource_size(res));
454	if (!omap->uhh_base) {
455		dev_err(dev, "UHH ioremap failed\n");
456		ret = -ENOMEM;
457		goto err_init_60m_fclk;
458	}
459
460	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
461	if (!res) {
462		dev_err(dev, "UHH EHCI get resource failed\n");
463		ret = -ENODEV;
464		goto err_tll;
465	}
466
467	omap->tll_base = ioremap(res->start, resource_size(res));
468	if (!omap->tll_base) {
469		dev_err(dev, "TLL ioremap failed\n");
470		ret = -ENOMEM;
471		goto err_tll;
472	}
473
474	platform_set_drvdata(pdev, omap);
475
476	ret = omap_usbhs_alloc_children(pdev);
477	if (ret) {
478		dev_err(dev, "omap_usbhs_alloc_children failed\n");
479		goto err_alloc;
480	}
481
482	omap_usbhs_init(dev);
483
484	goto end_probe;
485
486err_alloc:
487	iounmap(omap->tll_base);
488
489err_tll:
490	iounmap(omap->uhh_base);
491
492err_init_60m_fclk:
493	clk_put(omap->init_60m_fclk);
494
495err_usbtll_p2_fck:
496	clk_put(omap->usbtll_p2_fck);
497
498err_usbhost_p2_fck:
499	clk_put(omap->usbhost_p2_fck);
500
501err_usbtll_p1_fck:
502	clk_put(omap->usbtll_p1_fck);
503
504err_usbhost_p1_fck:
505	clk_put(omap->usbhost_p1_fck);
506
507err_xclk60mhsp2_ck:
508	clk_put(omap->xclk60mhsp2_ck);
509
510err_utmi_p2_fck:
511	clk_put(omap->utmi_p2_fck);
512
513err_xclk60mhsp1_ck:
514	clk_put(omap->xclk60mhsp1_ck);
515
516err_utmi_p1_fck:
517	clk_put(omap->utmi_p1_fck);
518
519err_end:
520	pm_runtime_disable(dev);
521	kfree(omap);
522
523end_probe:
524	return ret;
525}
526
527static void omap_usbhs_deinit(struct device *dev);
528/**
529 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
530 * @pdev: USB Host Controller being removed
531 *
532 * Reverses the effect of usbhs_omap_probe().
533 */
534static int __devexit usbhs_omap_remove(struct platform_device *pdev)
535{
536	struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
537
538	omap_usbhs_deinit(&pdev->dev);
539	iounmap(omap->tll_base);
540	iounmap(omap->uhh_base);
541	clk_put(omap->init_60m_fclk);
542	clk_put(omap->usbtll_p2_fck);
543	clk_put(omap->usbhost_p2_fck);
544	clk_put(omap->usbtll_p1_fck);
545	clk_put(omap->usbhost_p1_fck);
546	clk_put(omap->xclk60mhsp2_ck);
547	clk_put(omap->utmi_p2_fck);
548	clk_put(omap->xclk60mhsp1_ck);
549	clk_put(omap->utmi_p1_fck);
550	pm_runtime_disable(&pdev->dev);
551	kfree(omap);
552
553	return 0;
554}
555
556static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
557{
558	switch (pmode) {
559	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
560	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
561	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
562	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
563	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
564	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
565	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
566	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
567	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
568	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
569		return true;
570
571	default:
572		return false;
573	}
574}
575
576/*
577 * convert the port-mode enum to a value we can use in the FSLSMODE
578 * field of USBTLL_CHANNEL_CONF
579 */
580static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
581{
582	switch (mode) {
583	case OMAP_USBHS_PORT_MODE_UNUSED:
584	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
585		return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
586
587	case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
588		return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
589
590	case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
591		return OMAP_TLL_FSLSMODE_3PIN_PHY;
592
593	case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
594		return OMAP_TLL_FSLSMODE_4PIN_PHY;
595
596	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
597		return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
598
599	case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
600		return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
601
602	case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
603		return OMAP_TLL_FSLSMODE_3PIN_TLL;
604
605	case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
606		return OMAP_TLL_FSLSMODE_4PIN_TLL;
607
608	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
609		return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
610
611	case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
612		return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
613	default:
614		pr_warning("Invalid port mode, using default\n");
615		return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
616	}
617}
618
619static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
620{
621	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
622	struct usbhs_omap_platform_data	*pdata = dev->platform_data;
623	unsigned			reg;
624	int				i;
625
626	/* Program Common TLL register */
627	reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
628	reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
629		| OMAP_TLL_SHARED_CONF_USB_DIVRATION);
630	reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
631	reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
632
633	usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
634
635	/* Enable channels now */
636	for (i = 0; i < tll_channel_count; i++) {
637		reg = usbhs_read(omap->tll_base,
638				OMAP_TLL_CHANNEL_CONF(i));
639
640		if (is_ohci_port(pdata->port_mode[i])) {
641			reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
642				<< OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
643			reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
644		} else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
645
646			/* Disable AutoIdle, BitStuffing and use SDR Mode */
647			reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
648				| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
649				| OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
650
651		} else
652			continue;
653
654		reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
655		usbhs_write(omap->tll_base,
656				OMAP_TLL_CHANNEL_CONF(i), reg);
657
658		usbhs_writeb(omap->tll_base,
659				OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
660	}
661}
662
663static int usbhs_runtime_resume(struct device *dev)
664{
665	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
666	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
667
668	dev_dbg(dev, "usbhs_runtime_resume\n");
669
670	if (!pdata) {
671		dev_dbg(dev, "missing platform_data\n");
672		return  -ENODEV;
673	}
674
675	if (is_omap_usbhs_rev2(omap)) {
676		if (is_ehci_tll_mode(pdata->port_mode[0])) {
677			clk_enable(omap->usbhost_p1_fck);
678			clk_enable(omap->usbtll_p1_fck);
679		}
680		if (is_ehci_tll_mode(pdata->port_mode[1])) {
681			clk_enable(omap->usbhost_p2_fck);
682			clk_enable(omap->usbtll_p2_fck);
683		}
684		clk_enable(omap->utmi_p1_fck);
685		clk_enable(omap->utmi_p2_fck);
686	}
687	return 0;
688}
689
690static int usbhs_runtime_suspend(struct device *dev)
691{
692	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
693	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
694
695	dev_dbg(dev, "usbhs_runtime_suspend\n");
696
697	if (!pdata) {
698		dev_dbg(dev, "missing platform_data\n");
699		return  -ENODEV;
700	}
701
702	if (is_omap_usbhs_rev2(omap)) {
703		if (is_ehci_tll_mode(pdata->port_mode[0])) {
704			clk_disable(omap->usbhost_p1_fck);
705			clk_disable(omap->usbtll_p1_fck);
706		}
707		if (is_ehci_tll_mode(pdata->port_mode[1])) {
708			clk_disable(omap->usbhost_p2_fck);
709			clk_disable(omap->usbtll_p2_fck);
710		}
711		clk_disable(omap->utmi_p2_fck);
712		clk_disable(omap->utmi_p1_fck);
713	}
714	return 0;
715}
716
717static void omap_usbhs_init(struct device *dev)
718{
719	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
720	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
721	unsigned long			flags = 0;
722	unsigned			reg;
723
724	dev_dbg(dev, "starting TI HSUSB Controller\n");
725
726	pm_runtime_get_sync(dev);
727
728	spin_lock_irqsave(&omap->lock, flags);
729
730	if (pdata->ehci_data->phy_reset) {
731		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
732			gpio_request(pdata->ehci_data->reset_gpio_port[0],
733						"USB1 PHY reset");
734			gpio_direction_output
735				(pdata->ehci_data->reset_gpio_port[0], 0);
736		}
737
738		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) {
739			gpio_request(pdata->ehci_data->reset_gpio_port[1],
740						"USB2 PHY reset");
741			gpio_direction_output
742				(pdata->ehci_data->reset_gpio_port[1], 0);
743		}
744
745		/* Hold the PHY in RESET for enough time till DIR is high */
746		udelay(10);
747	}
748
749	omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
750	dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
751
752	/*
753	 * Really enable the port clocks
754	 * first call of pm_runtime_get_sync does not enable these
755	 * port clocks; because omap->usbhs_rev was not available
756	 * This omap->usbhs_rev is available now!
757	 */
758	usbhs_runtime_resume(dev);
759
760	reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
761	/* setup ULPI bypass and burst configurations */
762	reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
763			| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
764			| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN
765			| OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN);
766
767	if (is_omap_usbhs_rev1(omap)) {
768		if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
769			reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
770		if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
771			reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
772		if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
773			reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
774
775		/* Bypass the TLL module for PHY mode operation */
776		if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
777			dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
778			if (is_ehci_phy_mode(pdata->port_mode[0]) ||
779				is_ehci_phy_mode(pdata->port_mode[1]) ||
780					is_ehci_phy_mode(pdata->port_mode[2]))
781				reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
782			else
783				reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
784		} else {
785			dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
786			if (is_ehci_phy_mode(pdata->port_mode[0]))
787				reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
788			else
789				reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
790			if (is_ehci_phy_mode(pdata->port_mode[1]))
791				reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
792			else
793				reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
794			if (is_ehci_phy_mode(pdata->port_mode[2]))
795				reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
796			else
797				reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
798		}
799	} else if (is_omap_usbhs_rev2(omap)) {
800		/* Clear port mode fields for PHY mode*/
801		reg &= ~OMAP4_P1_MODE_CLEAR;
802		reg &= ~OMAP4_P2_MODE_CLEAR;
803
804		if (is_ehci_tll_mode(pdata->port_mode[0]) ||
805			(is_ohci_port(pdata->port_mode[0])))
806			reg |= OMAP4_P1_MODE_TLL;
807		else if (is_ehci_hsic_mode(pdata->port_mode[0]))
808			reg |= OMAP4_P1_MODE_HSIC;
809
810		if (is_ehci_tll_mode(pdata->port_mode[1]) ||
811			(is_ohci_port(pdata->port_mode[1])))
812			reg |= OMAP4_P2_MODE_TLL;
813		else if (is_ehci_hsic_mode(pdata->port_mode[1]))
814			reg |= OMAP4_P2_MODE_HSIC;
815	}
816
817	usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
818	dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
819
820	if (is_ehci_tll_mode(pdata->port_mode[0]) ||
821		is_ehci_tll_mode(pdata->port_mode[1]) ||
822		is_ehci_tll_mode(pdata->port_mode[2]) ||
823		(is_ohci_port(pdata->port_mode[0])) ||
824		(is_ohci_port(pdata->port_mode[1])) ||
825		(is_ohci_port(pdata->port_mode[2]))) {
826
827		/* Enable UTMI mode for required TLL channels */
828		if (is_omap_usbhs_rev2(omap))
829			usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
830		else
831			usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
832	}
833
834	if (pdata->ehci_data->phy_reset) {
835		/* Hold the PHY in RESET for enough time till
836		 * PHY is settled and ready
837		 */
838		udelay(10);
839
840		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
841			gpio_set_value
842				(pdata->ehci_data->reset_gpio_port[0], 1);
843
844		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
845			gpio_set_value
846				(pdata->ehci_data->reset_gpio_port[1], 1);
847	}
848
849	spin_unlock_irqrestore(&omap->lock, flags);
850	pm_runtime_put_sync(dev);
851}
852
853static void omap_usbhs_deinit(struct device *dev)
854{
855	struct usbhs_hcd_omap		*omap = dev_get_drvdata(dev);
856	struct usbhs_omap_platform_data	*pdata = &omap->platdata;
857
858	dev_dbg(dev, "stopping TI HSUSB Controller\n");
859
860	if (pdata->ehci_data->phy_reset) {
861		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
862			gpio_free(pdata->ehci_data->reset_gpio_port[0]);
863
864		if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
865			gpio_free(pdata->ehci_data->reset_gpio_port[1]);
866	}
867}
868
869static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
870	.runtime_suspend	= usbhs_runtime_suspend,
871	.runtime_resume		= usbhs_runtime_resume,
872};
873
874static struct platform_driver usbhs_omap_driver = {
875	.driver = {
876		.name		= (char *)usbhs_driver_name,
877		.owner		= THIS_MODULE,
878		.pm		= &usbhsomap_dev_pm_ops,
879	},
880	.remove		= __exit_p(usbhs_omap_remove),
881};
882
883MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
884MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
885MODULE_LICENSE("GPL v2");
886MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
887
888static int __init omap_usbhs_drvinit(void)
889{
890	return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
891}
892
893/*
894 * init before ehci and ohci drivers;
895 * The usbhs core driver should be initialized much before
896 * the omap ehci and ohci probe functions are called.
897 */
898fs_initcall(omap_usbhs_drvinit);
899
900static void __exit omap_usbhs_drvexit(void)
901{
902	platform_driver_unregister(&usbhs_omap_driver);
903}
904module_exit(omap_usbhs_drvexit);