/xbmc/utils/fastmemcpy.c

http://github.com/xbmc/xbmc · C · 396 lines · 248 code · 27 blank · 121 comment · 24 complexity · 4cd5f6073047ac3d31465e9533caa331 MD5 · raw file

  1. /*
  2. * fastmemcpy.h : fast memcpy routines
  3. *****************************************************************************
  4. * $Id: fastmemcpy.h 13905 2006-01-12 23:10:04Z dionoea $
  5. *
  6. * Authors: various Linux kernel hackers
  7. * various MPlayer hackers
  8. * Nick Kurshev <nickols_k@mail.ru>
  9. *
  10. * Copyright (C) 2011-2013 Team XBMC
  11. * http://xbmc.org
  12. *
  13. * This Program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2, or (at your option)
  16. * any later version.
  17. *
  18. * This Program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with XBMC; see the file COPYING. If not, see
  25. * <http://www.gnu.org/licenses/>.
  26. *
  27. */
  28. #if !defined(TARGET_WINDOWS) && !defined(__ppc__) && !defined(__powerpc__) && !defined(__arm__)
  29. #define HAVE_MMX2
  30. #define HAVE_SSE
  31. /*
  32. aclib - advanced C library ;)
  33. This file contains functions which improve and expand standard C-library
  34. */
  35. #include <stddef.h>
  36. #define BLOCK_SIZE 4096
  37. #define CONFUSION_FACTOR 0
  38. /*Feel free to fine-tune the above 2, it might be possible to get some speedup with them :)*/
  39. /*#define STATISTICS*/
  40. #ifndef HAVE_SSE2
  41. /*
  42. P3 processor has only one SSE decoder so can execute only 1 sse insn per
  43. cpu clock, but it has 3 mmx decoders (include load/store unit)
  44. and executes 3 mmx insns per cpu clock.
  45. P4 processor has some chances, but after reading:
  46. http://www.emulators.com/pentium4.htm
  47. I have doubts. Anyway SSE2 version of this code can be written better.
  48. */
  49. #undef HAVE_SSE
  50. #endif
  51. /*
  52. This part of code was taken by me from Linux-2.4.3 and slightly modified
  53. for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned
  54. blocks but mplayer uses weakly ordered data and original sources can not
  55. speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
  56. >From IA-32 Intel Architecture Software Developer's Manual Volume 1,
  57. Order Number 245470:
  58. "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
  59. Data referenced by a program can be temporal (data will be used again) or
  60. non-temporal (data will be referenced once and not reused in the immediate
  61. future). To make efficient use of the processor's caches, it is generally
  62. desirable to cache temporal data and not cache non-temporal data. Overloading
  63. the processor's caches with non-temporal data is sometimes referred to as
  64. "polluting the caches".
  65. The non-temporal data is written to memory with Write-Combining semantics.
  66. The PREFETCHh instructions permits a program to load data into the processor
  67. at a suggested cache level, so that it is closer to the processors load and
  68. store unit when it is needed. If the data is already present in a level of
  69. the cache hierarchy that is closer to the processor, the PREFETCHh instruction
  70. will not result in any data movement.
  71. But we should you PREFETCHNTA: Non-temporal data fetch data into location
  72. close to the processor, minimizing cache pollution.
  73. The MOVNTQ (store quadword using non-temporal hint) instruction stores
  74. packed integer data from an MMX register to memory, using a non-temporal hint.
  75. The MOVNTPS (store packed single-precision floating-point values using
  76. non-temporal hint) instruction stores packed floating-point data from an
  77. XMM register to memory, using a non-temporal hint.
  78. The SFENCE (Store Fence) instruction controls write ordering by creating a
  79. fence for memory store operations. This instruction guarantees that the results
  80. of every store instruction that precedes the store fence in program order is
  81. globally visible before any store instruction that follows the fence. The
  82. SFENCE instruction provides an efficient way of ensuring ordering between
  83. procedures that produce weakly-ordered data and procedures that consume that
  84. data.
  85. If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
  86. */
  87. /* 3dnow memcpy support from kernel 2.4.2 */
  88. /* by Pontscho/fresh!mindworkz */
  89. #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX )
  90. #undef HAVE_MMX1
  91. #if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE)
  92. /* means: mmx v.1. Note: Since we added alignment of destinition it speedups
  93. of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus
  94. standard (non MMX-optimized) version.
  95. Note: on K6-2+ it speedups memory copying upto 25% and
  96. on K7 and P3 about 500% (5 times). */
  97. #define HAVE_MMX1
  98. #endif
  99. #undef HAVE_K6_2PLUS
  100. #if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
  101. #define HAVE_K6_2PLUS
  102. #endif
  103. /* for small memory blocks (<256 bytes) this version is faster */
  104. #define small_memcpy(to,from,n)\
  105. {\
  106. register unsigned long int dummy;\
  107. __asm__ __volatile__(\
  108. "rep; movsb"\
  109. :"=&D"(to), "=&S"(from), "=&c"(dummy)\
  110. /* It's most portable way to notify compiler */\
  111. /* that edi, esi and ecx are clobbered in asm block. */\
  112. /* Thanks to A'rpi for hint!!! */\
  113. :"0" (to), "1" (from),"2" (n)\
  114. : "memory");\
  115. }
  116. #ifdef HAVE_SSE
  117. #define MMREG_SIZE 16
  118. #else
  119. #define MMREG_SIZE 64 /*8*/
  120. #endif
  121. /* Small defines (for readability only) ;) */
  122. #ifdef HAVE_K6_2PLUS
  123. #define PREFETCH "prefetch"
  124. /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */
  125. #define EMMS "femms"
  126. #else
  127. #define PREFETCH "prefetchnta"
  128. #define EMMS "emms"
  129. #endif
  130. #ifdef HAVE_MMX2
  131. #define MOVNTQ "movntq"
  132. #else
  133. #define MOVNTQ "movq"
  134. #endif
  135. #ifdef HAVE_MMX1
  136. #define MIN_LEN 0x800 /* 2K blocks */
  137. #else
  138. #define MIN_LEN 0x40 /* 64-byte blocks */
  139. #endif
  140. void * fast_memcpy(void * to, const void * from, size_t len)
  141. {
  142. void *retval;
  143. size_t i;
  144. retval = to;
  145. #ifdef STATISTICS
  146. {
  147. static int freq[33];
  148. static int t=0;
  149. int i;
  150. for(i=0; len>(1<<i); i++);
  151. freq[i]++;
  152. t++;
  153. if(1024*1024*1024 % t == 0)
  154. for(i=0; i<32; i++)
  155. printf("freq < %8d %4d\n", 1<<i, freq[i]);
  156. }
  157. #endif
  158. #ifndef HAVE_MMX1
  159. /* PREFETCH has effect even for MOVSB instruction ;) */
  160. __asm__ __volatile__ (
  161. PREFETCH" (%0)\n"
  162. PREFETCH" 64(%0)\n"
  163. PREFETCH" 128(%0)\n"
  164. PREFETCH" 192(%0)\n"
  165. PREFETCH" 256(%0)\n"
  166. : : "r" (from) );
  167. #endif
  168. if(len >= MIN_LEN)
  169. {
  170. register unsigned long int delta;
  171. /* Align destinition to MMREG_SIZE -boundary */
  172. delta = ((unsigned long int)to)&(MMREG_SIZE-1);
  173. if(delta)
  174. {
  175. delta=MMREG_SIZE-delta;
  176. len -= delta;
  177. small_memcpy(to, from, delta);
  178. }
  179. i = len >> 6; /* len/64 */
  180. len&=63;
  181. /*
  182. This algorithm is top effective when the code consequently
  183. reads and writes blocks which have size of cache line.
  184. Size of cache line is processor-dependent.
  185. It will, however, be a minimum of 32 bytes on any processors.
  186. It would be better to have a number of instructions which
  187. perform reading and writing to be multiple to a number of
  188. processor's decoders, but it's not always possible.
  189. */
  190. #ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
  191. if(((unsigned long)from) & 15)
  192. /* if SRC is misaligned */
  193. for(; i>0; i--)
  194. {
  195. __asm__ __volatile__ (
  196. PREFETCH" 320(%0)\n"
  197. "movups (%0), %%xmm0\n"
  198. "movups 16(%0), %%xmm1\n"
  199. "movups 32(%0), %%xmm2\n"
  200. "movups 48(%0), %%xmm3\n"
  201. "movntps %%xmm0, (%1)\n"
  202. "movntps %%xmm1, 16(%1)\n"
  203. "movntps %%xmm2, 32(%1)\n"
  204. "movntps %%xmm3, 48(%1)\n"
  205. :: "r" (from), "r" (to) : "memory");
  206. ((const unsigned char *)from)+=64;
  207. ((unsigned char *)to)+=64;
  208. }
  209. else
  210. /*
  211. Only if SRC is aligned on 16-byte boundary.
  212. It allows to use movaps instead of movups, which required data
  213. to be aligned or a general-protection exception (#GP) is generated.
  214. */
  215. for(; i>0; i--)
  216. {
  217. __asm__ __volatile__ (
  218. PREFETCH" 320(%0)\n"
  219. "movaps (%0), %%xmm0\n"
  220. "movaps 16(%0), %%xmm1\n"
  221. "movaps 32(%0), %%xmm2\n"
  222. "movaps 48(%0), %%xmm3\n"
  223. "movntps %%xmm0, (%1)\n"
  224. "movntps %%xmm1, 16(%1)\n"
  225. "movntps %%xmm2, 32(%1)\n"
  226. "movntps %%xmm3, 48(%1)\n"
  227. :: "r" (from), "r" (to) : "memory");
  228. ((const unsigned char *)from)+=64;
  229. ((unsigned char *)to)+=64;
  230. }
  231. #else
  232. /* Align destination at BLOCK_SIZE boundary */
  233. for(; ((ptrdiff_t)to & (BLOCK_SIZE-1)) && i>0; i--)
  234. {
  235. __asm__ __volatile__ (
  236. #ifndef HAVE_MMX1
  237. PREFETCH" 320(%0)\n"
  238. #endif
  239. "movq (%0), %%mm0\n"
  240. "movq 8(%0), %%mm1\n"
  241. "movq 16(%0), %%mm2\n"
  242. "movq 24(%0), %%mm3\n"
  243. "movq 32(%0), %%mm4\n"
  244. "movq 40(%0), %%mm5\n"
  245. "movq 48(%0), %%mm6\n"
  246. "movq 56(%0), %%mm7\n"
  247. MOVNTQ" %%mm0, (%1)\n"
  248. MOVNTQ" %%mm1, 8(%1)\n"
  249. MOVNTQ" %%mm2, 16(%1)\n"
  250. MOVNTQ" %%mm3, 24(%1)\n"
  251. MOVNTQ" %%mm4, 32(%1)\n"
  252. MOVNTQ" %%mm5, 40(%1)\n"
  253. MOVNTQ" %%mm6, 48(%1)\n"
  254. MOVNTQ" %%mm7, 56(%1)\n"
  255. :: "r" (from), "r" (to) : "memory");
  256. from = (const void *) (((const unsigned char *)from)+64);
  257. to = (void *) (((unsigned char *)to)+64);
  258. }
  259. /* printf(" %p %p\n", (ptrdiff_t)from&1023, (ptrdiff_t)to&1023); */
  260. /* Pure Assembly cuz gcc is a bit unpredictable ;) */
  261. # if 0
  262. if(i>=BLOCK_SIZE/64)
  263. asm volatile(
  264. "xorl %%eax, %%eax \n\t"
  265. ".balign 16 \n\t"
  266. "1: \n\t"
  267. "movl (%0, %%eax), %%ebx \n\t"
  268. "movl 32(%0, %%eax), %%ebx \n\t"
  269. "movl 64(%0, %%eax), %%ebx \n\t"
  270. "movl 96(%0, %%eax), %%ebx \n\t"
  271. "addl $128, %%eax \n\t"
  272. "cmpl %3, %%eax \n\t"
  273. " jb 1b \n\t"
  274. "xorl %%eax, %%eax \n\t"
  275. ".balign 16 \n\t"
  276. "2: \n\t"
  277. "movq (%0, %%eax), %%mm0\n"
  278. "movq 8(%0, %%eax), %%mm1\n"
  279. "movq 16(%0, %%eax), %%mm2\n"
  280. "movq 24(%0, %%eax), %%mm3\n"
  281. "movq 32(%0, %%eax), %%mm4\n"
  282. "movq 40(%0, %%eax), %%mm5\n"
  283. "movq 48(%0, %%eax), %%mm6\n"
  284. "movq 56(%0, %%eax), %%mm7\n"
  285. MOVNTQ" %%mm0, (%1, %%eax)\n"
  286. MOVNTQ" %%mm1, 8(%1, %%eax)\n"
  287. MOVNTQ" %%mm2, 16(%1, %%eax)\n"
  288. MOVNTQ" %%mm3, 24(%1, %%eax)\n"
  289. MOVNTQ" %%mm4, 32(%1, %%eax)\n"
  290. MOVNTQ" %%mm5, 40(%1, %%eax)\n"
  291. MOVNTQ" %%mm6, 48(%1, %%eax)\n"
  292. MOVNTQ" %%mm7, 56(%1, %%eax)\n"
  293. "addl $64, %%eax \n\t"
  294. "cmpl %3, %%eax \n\t"
  295. "jb 2b \n\t"
  296. #if CONFUSION_FACTOR > 0
  297. /* a few percent speedup on out of order executing CPUs */
  298. "movl %5, %%eax \n\t"
  299. "2: \n\t"
  300. "movl (%0), %%ebx \n\t"
  301. "movl (%0), %%ebx \n\t"
  302. "movl (%0), %%ebx \n\t"
  303. "movl (%0), %%ebx \n\t"
  304. "decl %%eax \n\t"
  305. " jnz 2b \n\t"
  306. #endif
  307. "xorl %%eax, %%eax \n\t"
  308. "addl %3, %0 \n\t"
  309. "addl %3, %1 \n\t"
  310. "subl %4, %2 \n\t"
  311. "cmpl %4, %2 \n\t"
  312. " jae 1b \n\t"
  313. : "+r" (from), "+r" (to), "+r" (i)
  314. : "r" (BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" (CONFUSION_FACTOR)
  315. : "%eax", "%ebx"
  316. );
  317. #endif
  318. for(; i>0; i--)
  319. {
  320. __asm__ __volatile__ (
  321. #ifndef HAVE_MMX1
  322. PREFETCH" 320(%0)\n"
  323. #endif
  324. "movq (%0), %%mm0\n"
  325. "movq 8(%0), %%mm1\n"
  326. "movq 16(%0), %%mm2\n"
  327. "movq 24(%0), %%mm3\n"
  328. "movq 32(%0), %%mm4\n"
  329. "movq 40(%0), %%mm5\n"
  330. "movq 48(%0), %%mm6\n"
  331. "movq 56(%0), %%mm7\n"
  332. MOVNTQ" %%mm0, (%1)\n"
  333. MOVNTQ" %%mm1, 8(%1)\n"
  334. MOVNTQ" %%mm2, 16(%1)\n"
  335. MOVNTQ" %%mm3, 24(%1)\n"
  336. MOVNTQ" %%mm4, 32(%1)\n"
  337. MOVNTQ" %%mm5, 40(%1)\n"
  338. MOVNTQ" %%mm6, 48(%1)\n"
  339. MOVNTQ" %%mm7, 56(%1)\n"
  340. :: "r" (from), "r" (to) : "memory");
  341. from = (const void *) (((const unsigned char *)from)+64);
  342. to = (void *) (((unsigned char *)to)+64);
  343. }
  344. #endif /* Have SSE */
  345. #ifdef HAVE_MMX2
  346. /* since movntq is weakly-ordered, a "sfence"
  347. * is needed to become ordered again. */
  348. __asm__ __volatile__ ("sfence":::"memory");
  349. #endif
  350. #ifndef HAVE_SSE
  351. /* enables to use FPU */
  352. __asm__ __volatile__ (EMMS:::"memory");
  353. #endif
  354. }
  355. /*
  356. * Now do the tail of the block
  357. */
  358. if(len) small_memcpy(to, from, len);
  359. return retval;
  360. }
  361. #endif /* #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX ) */
  362. #endif