/marchid.md

https://github.com/riscv/riscv-isa-manual · Markdown · 38 lines · 35 code · 3 blank · 0 comment · 0 complexity · c2bda7d6661a606dd66bdb8af2a0aeea MD5 · raw file 

    

  1. Open-Source RISC-V Architecture IDs
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  2. ========================================
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  3. 

  4. Every RISC-V hart provides an marchid CSR that encodes its base
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  5. microarchitecture.  Any hart may report an architecture ID of 0, indicating
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  6. unspecified origin.  Commercial implementations (those with nonzero mvendorid)
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  7. may encode any value in marchid with the most-significant bit set, with the
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  8. low-order bits formatted in a vendor-specific manner.  Open-source
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  9. implementations (which may or may not have a nonzero mvendorid) have the
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  10. most-significant bit clear, with a globally unique pattern in the low-order
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  11. bits.
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  12. 

  13. This document contains the canonical list of open-source RISC-V implementations
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  14. and their architecture IDs.  Open-source project maintainers may make pull
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  15. requests against this repository to request the allocation of an architecture
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  16. ID.
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  17. 

  18. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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  19. Project Name  | Maintainers                     | Point of Contact                                            | Architecture ID   | Project URL                                         
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  20. ------------- | ------------------------------- | ----------------------------------------------------------- | ----------------- | --------------------------------------------------- 
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  21. Rocket        | SiFive, UC Berkeley             | [Andrew Waterman](mailto:andrew@sifive.com), SiFive         | 1                 | https://github.com/freechipsproject/rocket-chip     
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  22. BOOM          | UC Berkeley                     | [Christopher Celio](mailto:celio@berkeley.edu)              | 2                 | https://github.com/ucb-bar/riscv-boom               
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  23. CVA6          | OpenHW Group                    | [Florian Zaruba](mailto:florian@openhwgroup.org), OpenHW Group | 3                 | https://github.com/openhwgroup/cva6             
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  24. CV32E40P      | OpenHW Group                    | [Davide Schiavone](mailto:davide@openhwgroup.org), OpenHW Group | 4                 | https://github.com/openhwgroup/cv32e40p
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  25. Spike         | SiFive, UC Berkeley             | [Andrew Waterman](mailto:andrew@sifive.com), SiFive         | 5                 | https://github.com/riscv/riscv-isa-sim              
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  26. E-Class       | IIT Madras                      | [Neel Gala](mailto:neelgala@gmail.com)                      | 6                 | https://gitlab.com/shaktiproject/cores/e-class
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  27. ORCA          | VectorBlox                      | [Joel Vandergriendt](mailto:joel@vectorblox.com)            | 7                 | https://github.com/vectorblox/orca
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  28. SCR1          | Syntacore                       | [Dmitri Pavlov](mailto:dmitri.pavlov@syntacore.com), Syntacore| 8               | https://github.com/syntacore/scr1
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  29. YARVI         | Tommy Thorn's Priceless Services| [Tommy Thorn](mailto:tommy-github2@thorn.ws)                | 9                 | https://github.com/tommythorn/yarvi
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  30. RVBS          | Alexandre Joannou, University of Cambridge| [Alexandre Joannou](mailto:aj443@cl.cam.ac.uk)    | 10                | https://github.com/CTSRD-CHERI/RVBS
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  31. SweRV EH1     | Western Digital Corporation     | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com)                 | 11                | https://github.com/chipsalliance/Cores-SweRV
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  32. MSCC          | Rongcui Dong                    | [Rongcui Dong](mailto:rongcuid@outlook.com)                | 12 | https://github.com/rongcuid/MSCC
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  33. BlackParrot   | The World                       | [Michael B. Taylor](mailto:prof.taylor@gmail.com), U. Washington | 13 |  https://github.com/black-parrot 
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  34. BaseJump Manycore   | U. Washington             | [Michael B. Taylor](mailto:prof.taylor@gmail.com), U. Washington | 14 |  https://github.com/bespoke-silicon-group/bsg_manycore 
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  35. C-Class       | IIT Madras                      | [Neel Gala](mailto:neelgala@gmail.com)                      | 15                 | https://gitlab.com/shaktiproject/cores/c-class
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  36. SweRV EL2     | Western Digital Corporation     | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com)                 | 16                | https://github.com/chipsalliance/Cores-SweRV-EL2
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  37. SweRV EH2     | Western Digital Corporation     | [Thomas Wicki](mailto:Thomas.Wicki@wdc.com)                 | 17                | https://github.com/chipsalliance/Cores-SweRV-EH2
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  38. SERV          | Olof Kindgren Enterprises       | [Olof Kindgren](mailto:olof.kindgren@gmail.com)             | 18                | https://github.com/olofk/serv
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