/include/linux/spi/spi.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35 · C++ Header · 779 lines · 252 code · 89 blank · 438 comment · 9 complexity · ce0fdeca51c1ad89502dfc230376db09 MD5 · raw file

  1. /*
  2. * Copyright (C) 2005 David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #ifndef __LINUX_SPI_H
  19. #define __LINUX_SPI_H
  20. #include <linux/device.h>
  21. #include <linux/mod_devicetable.h>
  22. #include <linux/slab.h>
  23. /*
  24. * INTERFACES between SPI master-side drivers and SPI infrastructure.
  25. * (There's no SPI slave support for Linux yet...)
  26. */
  27. extern struct bus_type spi_bus_type;
  28. /**
  29. * struct spi_device - Master side proxy for an SPI slave device
  30. * @dev: Driver model representation of the device.
  31. * @master: SPI controller used with the device.
  32. * @max_speed_hz: Maximum clock rate to be used with this chip
  33. * (on this board); may be changed by the device's driver.
  34. * The spi_transfer.speed_hz can override this for each transfer.
  35. * @chip_select: Chipselect, distinguishing chips handled by @master.
  36. * @mode: The spi mode defines how data is clocked out and in.
  37. * This may be changed by the device's driver.
  38. * The "active low" default for chipselect mode can be overridden
  39. * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
  40. * each word in a transfer (by specifying SPI_LSB_FIRST).
  41. * @bits_per_word: Data transfers involve one or more words; word sizes
  42. * like eight or 12 bits are common. In-memory wordsizes are
  43. * powers of two bytes (e.g. 20 bit samples use 32 bits).
  44. * This may be changed by the device's driver, or left at the
  45. * default (0) indicating protocol words are eight bit bytes.
  46. * The spi_transfer.bits_per_word can override this for each transfer.
  47. * @irq: Negative, or the number passed to request_irq() to receive
  48. * interrupts from this device.
  49. * @controller_state: Controller's runtime state
  50. * @controller_data: Board-specific definitions for controller, such as
  51. * FIFO initialization parameters; from board_info.controller_data
  52. * @modalias: Name of the driver to use with this device, or an alias
  53. * for that name. This appears in the sysfs "modalias" attribute
  54. * for driver coldplugging, and in uevents used for hotplugging
  55. *
  56. * A @spi_device is used to interchange data between an SPI slave
  57. * (usually a discrete chip) and CPU memory.
  58. *
  59. * In @dev, the platform_data is used to hold information about this
  60. * device that's meaningful to the device's protocol driver, but not
  61. * to its controller. One example might be an identifier for a chip
  62. * variant with slightly different functionality; another might be
  63. * information about how this particular board wires the chip's pins.
  64. */
  65. struct spi_device {
  66. struct device dev;
  67. struct spi_master *master;
  68. u32 max_speed_hz;
  69. u8 chip_select;
  70. u8 mode;
  71. #define SPI_CPHA 0x01 /* clock phase */
  72. #define SPI_CPOL 0x02 /* clock polarity */
  73. #define SPI_MODE_0 (0|0) /* (original MicroWire) */
  74. #define SPI_MODE_1 (0|SPI_CPHA)
  75. #define SPI_MODE_2 (SPI_CPOL|0)
  76. #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
  77. #define SPI_CS_HIGH 0x04 /* chipselect active high? */
  78. #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
  79. #define SPI_3WIRE 0x10 /* SI/SO signals shared */
  80. #define SPI_LOOP 0x20 /* loopback mode */
  81. #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
  82. #define SPI_READY 0x80 /* slave pulls low to pause */
  83. u8 bits_per_word;
  84. int irq;
  85. void *controller_state;
  86. void *controller_data;
  87. char modalias[SPI_NAME_SIZE];
  88. /*
  89. * likely need more hooks for more protocol options affecting how
  90. * the controller talks to each chip, like:
  91. * - memory packing (12 bit samples into low bits, others zeroed)
  92. * - priority
  93. * - drop chipselect after each word
  94. * - chipselect delays
  95. * - ...
  96. */
  97. };
  98. static inline struct spi_device *to_spi_device(struct device *dev)
  99. {
  100. return dev ? container_of(dev, struct spi_device, dev) : NULL;
  101. }
  102. /* most drivers won't need to care about device refcounting */
  103. static inline struct spi_device *spi_dev_get(struct spi_device *spi)
  104. {
  105. return (spi && get_device(&spi->dev)) ? spi : NULL;
  106. }
  107. static inline void spi_dev_put(struct spi_device *spi)
  108. {
  109. if (spi)
  110. put_device(&spi->dev);
  111. }
  112. /* ctldata is for the bus_master driver's runtime state */
  113. static inline void *spi_get_ctldata(struct spi_device *spi)
  114. {
  115. return spi->controller_state;
  116. }
  117. static inline void spi_set_ctldata(struct spi_device *spi, void *state)
  118. {
  119. spi->controller_state = state;
  120. }
  121. /* device driver data */
  122. static inline void spi_set_drvdata(struct spi_device *spi, void *data)
  123. {
  124. dev_set_drvdata(&spi->dev, data);
  125. }
  126. static inline void *spi_get_drvdata(struct spi_device *spi)
  127. {
  128. return dev_get_drvdata(&spi->dev);
  129. }
  130. struct spi_message;
  131. /**
  132. * struct spi_driver - Host side "protocol" driver
  133. * @id_table: List of SPI devices supported by this driver
  134. * @probe: Binds this driver to the spi device. Drivers can verify
  135. * that the device is actually present, and may need to configure
  136. * characteristics (such as bits_per_word) which weren't needed for
  137. * the initial configuration done during system setup.
  138. * @remove: Unbinds this driver from the spi device
  139. * @shutdown: Standard shutdown callback used during system state
  140. * transitions such as powerdown/halt and kexec
  141. * @suspend: Standard suspend callback used during system state transitions
  142. * @resume: Standard resume callback used during system state transitions
  143. * @driver: SPI device drivers should initialize the name and owner
  144. * field of this structure.
  145. *
  146. * This represents the kind of device driver that uses SPI messages to
  147. * interact with the hardware at the other end of a SPI link. It's called
  148. * a "protocol" driver because it works through messages rather than talking
  149. * directly to SPI hardware (which is what the underlying SPI controller
  150. * driver does to pass those messages). These protocols are defined in the
  151. * specification for the device(s) supported by the driver.
  152. *
  153. * As a rule, those device protocols represent the lowest level interface
  154. * supported by a driver, and it will support upper level interfaces too.
  155. * Examples of such upper levels include frameworks like MTD, networking,
  156. * MMC, RTC, filesystem character device nodes, and hardware monitoring.
  157. */
  158. struct spi_driver {
  159. const struct spi_device_id *id_table;
  160. int (*probe)(struct spi_device *spi);
  161. int (*remove)(struct spi_device *spi);
  162. void (*shutdown)(struct spi_device *spi);
  163. int (*suspend)(struct spi_device *spi, pm_message_t mesg);
  164. int (*resume)(struct spi_device *spi);
  165. struct device_driver driver;
  166. };
  167. static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
  168. {
  169. return drv ? container_of(drv, struct spi_driver, driver) : NULL;
  170. }
  171. extern int spi_register_driver(struct spi_driver *sdrv);
  172. /**
  173. * spi_unregister_driver - reverse effect of spi_register_driver
  174. * @sdrv: the driver to unregister
  175. * Context: can sleep
  176. */
  177. static inline void spi_unregister_driver(struct spi_driver *sdrv)
  178. {
  179. if (sdrv)
  180. driver_unregister(&sdrv->driver);
  181. }
  182. /**
  183. * struct spi_master - interface to SPI master controller
  184. * @dev: device interface to this driver
  185. * @bus_num: board-specific (and often SOC-specific) identifier for a
  186. * given SPI controller.
  187. * @num_chipselect: chipselects are used to distinguish individual
  188. * SPI slaves, and are numbered from zero to num_chipselects.
  189. * each slave has a chipselect signal, but it's common that not
  190. * every chipselect is connected to a slave.
  191. * @dma_alignment: SPI controller constraint on DMA buffers alignment.
  192. * @mode_bits: flags understood by this controller driver
  193. * @flags: other constraints relevant to this driver
  194. * @setup: updates the device mode and clocking records used by a
  195. * device's SPI controller; protocol code may call this. This
  196. * must fail if an unrecognized or unsupported mode is requested.
  197. * It's always safe to call this unless transfers are pending on
  198. * the device whose settings are being modified.
  199. * @transfer: adds a message to the controller's transfer queue.
  200. * @cleanup: frees controller-specific state
  201. *
  202. * Each SPI master controller can communicate with one or more @spi_device
  203. * children. These make a small bus, sharing MOSI, MISO and SCK signals
  204. * but not chip select signals. Each device may be configured to use a
  205. * different clock rate, since those shared signals are ignored unless
  206. * the chip is selected.
  207. *
  208. * The driver for an SPI controller manages access to those devices through
  209. * a queue of spi_message transactions, copying data between CPU memory and
  210. * an SPI slave device. For each such message it queues, it calls the
  211. * message's completion function when the transaction completes.
  212. */
  213. struct spi_master {
  214. struct device dev;
  215. /* other than negative (== assign one dynamically), bus_num is fully
  216. * board-specific. usually that simplifies to being SOC-specific.
  217. * example: one SOC has three SPI controllers, numbered 0..2,
  218. * and one board's schematics might show it using SPI-2. software
  219. * would normally use bus_num=2 for that controller.
  220. */
  221. s16 bus_num;
  222. /* chipselects will be integral to many controllers; some others
  223. * might use board-specific GPIOs.
  224. */
  225. u16 num_chipselect;
  226. /* some SPI controllers pose alignment requirements on DMAable
  227. * buffers; let protocol drivers know about these requirements.
  228. */
  229. u16 dma_alignment;
  230. /* spi_device.mode flags understood by this controller driver */
  231. u16 mode_bits;
  232. /* other constraints relevant to this driver */
  233. u16 flags;
  234. #define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */
  235. #define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */
  236. #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */
  237. /* Setup mode and clock, etc (spi driver may call many times).
  238. *
  239. * IMPORTANT: this may be called when transfers to another
  240. * device are active. DO NOT UPDATE SHARED REGISTERS in ways
  241. * which could break those transfers.
  242. */
  243. int (*setup)(struct spi_device *spi);
  244. /* bidirectional bulk transfers
  245. *
  246. * + The transfer() method may not sleep; its main role is
  247. * just to add the message to the queue.
  248. * + For now there's no remove-from-queue operation, or
  249. * any other request management
  250. * + To a given spi_device, message queueing is pure fifo
  251. *
  252. * + The master's main job is to process its message queue,
  253. * selecting a chip then transferring data
  254. * + If there are multiple spi_device children, the i/o queue
  255. * arbitration algorithm is unspecified (round robin, fifo,
  256. * priority, reservations, preemption, etc)
  257. *
  258. * + Chipselect stays active during the entire message
  259. * (unless modified by spi_transfer.cs_change != 0).
  260. * + The message transfers use clock and SPI mode parameters
  261. * previously established by setup() for this device
  262. */
  263. int (*transfer)(struct spi_device *spi,
  264. struct spi_message *mesg);
  265. /* called on release() to free memory provided by spi_master */
  266. void (*cleanup)(struct spi_device *spi);
  267. };
  268. static inline void *spi_master_get_devdata(struct spi_master *master)
  269. {
  270. return dev_get_drvdata(&master->dev);
  271. }
  272. static inline void spi_master_set_devdata(struct spi_master *master, void *data)
  273. {
  274. dev_set_drvdata(&master->dev, data);
  275. }
  276. static inline struct spi_master *spi_master_get(struct spi_master *master)
  277. {
  278. if (!master || !get_device(&master->dev))
  279. return NULL;
  280. return master;
  281. }
  282. static inline void spi_master_put(struct spi_master *master)
  283. {
  284. if (master)
  285. put_device(&master->dev);
  286. }
  287. /* the spi driver core manages memory for the spi_master classdev */
  288. extern struct spi_master *
  289. spi_alloc_master(struct device *host, unsigned size);
  290. extern int spi_register_master(struct spi_master *master);
  291. extern void spi_unregister_master(struct spi_master *master);
  292. extern struct spi_master *spi_busnum_to_master(u16 busnum);
  293. /*---------------------------------------------------------------------------*/
  294. /*
  295. * I/O INTERFACE between SPI controller and protocol drivers
  296. *
  297. * Protocol drivers use a queue of spi_messages, each transferring data
  298. * between the controller and memory buffers.
  299. *
  300. * The spi_messages themselves consist of a series of read+write transfer
  301. * segments. Those segments always read the same number of bits as they
  302. * write; but one or the other is easily ignored by passing a null buffer
  303. * pointer. (This is unlike most types of I/O API, because SPI hardware
  304. * is full duplex.)
  305. *
  306. * NOTE: Allocation of spi_transfer and spi_message memory is entirely
  307. * up to the protocol driver, which guarantees the integrity of both (as
  308. * well as the data buffers) for as long as the message is queued.
  309. */
  310. /**
  311. * struct spi_transfer - a read/write buffer pair
  312. * @tx_buf: data to be written (dma-safe memory), or NULL
  313. * @rx_buf: data to be read (dma-safe memory), or NULL
  314. * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
  315. * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
  316. * @len: size of rx and tx buffers (in bytes)
  317. * @speed_hz: Select a speed other than the device default for this
  318. * transfer. If 0 the default (from @spi_device) is used.
  319. * @bits_per_word: select a bits_per_word other than the device default
  320. * for this transfer. If 0 the default (from @spi_device) is used.
  321. * @cs_change: affects chipselect after this transfer completes
  322. * @delay_usecs: microseconds to delay after this transfer before
  323. * (optionally) changing the chipselect status, then starting
  324. * the next transfer or completing this @spi_message.
  325. * @transfer_list: transfers are sequenced through @spi_message.transfers
  326. *
  327. * SPI transfers always write the same number of bytes as they read.
  328. * Protocol drivers should always provide @rx_buf and/or @tx_buf.
  329. * In some cases, they may also want to provide DMA addresses for
  330. * the data being transferred; that may reduce overhead, when the
  331. * underlying driver uses dma.
  332. *
  333. * If the transmit buffer is null, zeroes will be shifted out
  334. * while filling @rx_buf. If the receive buffer is null, the data
  335. * shifted in will be discarded. Only "len" bytes shift out (or in).
  336. * It's an error to try to shift out a partial word. (For example, by
  337. * shifting out three bytes with word size of sixteen or twenty bits;
  338. * the former uses two bytes per word, the latter uses four bytes.)
  339. *
  340. * In-memory data values are always in native CPU byte order, translated
  341. * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
  342. * for example when bits_per_word is sixteen, buffers are 2N bytes long
  343. * (@len = 2N) and hold N sixteen bit words in CPU byte order.
  344. *
  345. * When the word size of the SPI transfer is not a power-of-two multiple
  346. * of eight bits, those in-memory words include extra bits. In-memory
  347. * words are always seen by protocol drivers as right-justified, so the
  348. * undefined (rx) or unused (tx) bits are always the most significant bits.
  349. *
  350. * All SPI transfers start with the relevant chipselect active. Normally
  351. * it stays selected until after the last transfer in a message. Drivers
  352. * can affect the chipselect signal using cs_change.
  353. *
  354. * (i) If the transfer isn't the last one in the message, this flag is
  355. * used to make the chipselect briefly go inactive in the middle of the
  356. * message. Toggling chipselect in this way may be needed to terminate
  357. * a chip command, letting a single spi_message perform all of group of
  358. * chip transactions together.
  359. *
  360. * (ii) When the transfer is the last one in the message, the chip may
  361. * stay selected until the next transfer. On multi-device SPI busses
  362. * with nothing blocking messages going to other devices, this is just
  363. * a performance hint; starting a message to another device deselects
  364. * this one. But in other cases, this can be used to ensure correctness.
  365. * Some devices need protocol transactions to be built from a series of
  366. * spi_message submissions, where the content of one message is determined
  367. * by the results of previous messages and where the whole transaction
  368. * ends when the chipselect goes intactive.
  369. *
  370. * The code that submits an spi_message (and its spi_transfers)
  371. * to the lower layers is responsible for managing its memory.
  372. * Zero-initialize every field you don't set up explicitly, to
  373. * insulate against future API updates. After you submit a message
  374. * and its transfers, ignore them until its completion callback.
  375. */
  376. struct spi_transfer {
  377. /* it's ok if tx_buf == rx_buf (right?)
  378. * for MicroWire, one buffer must be null
  379. * buffers must work with dma_*map_single() calls, unless
  380. * spi_message.is_dma_mapped reports a pre-existing mapping
  381. */
  382. const void *tx_buf;
  383. void *rx_buf;
  384. unsigned len;
  385. dma_addr_t tx_dma;
  386. dma_addr_t rx_dma;
  387. unsigned cs_change:1;
  388. u8 bits_per_word;
  389. u16 delay_usecs;
  390. u32 speed_hz;
  391. struct list_head transfer_list;
  392. };
  393. /**
  394. * struct spi_message - one multi-segment SPI transaction
  395. * @transfers: list of transfer segments in this transaction
  396. * @spi: SPI device to which the transaction is queued
  397. * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
  398. * addresses for each transfer buffer
  399. * @complete: called to report transaction completions
  400. * @context: the argument to complete() when it's called
  401. * @actual_length: the total number of bytes that were transferred in all
  402. * successful segments
  403. * @status: zero for success, else negative errno
  404. * @queue: for use by whichever driver currently owns the message
  405. * @state: for use by whichever driver currently owns the message
  406. *
  407. * A @spi_message is used to execute an atomic sequence of data transfers,
  408. * each represented by a struct spi_transfer. The sequence is "atomic"
  409. * in the sense that no other spi_message may use that SPI bus until that
  410. * sequence completes. On some systems, many such sequences can execute as
  411. * as single programmed DMA transfer. On all systems, these messages are
  412. * queued, and might complete after transactions to other devices. Messages
  413. * sent to a given spi_device are alway executed in FIFO order.
  414. *
  415. * The code that submits an spi_message (and its spi_transfers)
  416. * to the lower layers is responsible for managing its memory.
  417. * Zero-initialize every field you don't set up explicitly, to
  418. * insulate against future API updates. After you submit a message
  419. * and its transfers, ignore them until its completion callback.
  420. */
  421. struct spi_message {
  422. struct list_head transfers;
  423. struct spi_device *spi;
  424. unsigned is_dma_mapped:1;
  425. /* REVISIT: we might want a flag affecting the behavior of the
  426. * last transfer ... allowing things like "read 16 bit length L"
  427. * immediately followed by "read L bytes". Basically imposing
  428. * a specific message scheduling algorithm.
  429. *
  430. * Some controller drivers (message-at-a-time queue processing)
  431. * could provide that as their default scheduling algorithm. But
  432. * others (with multi-message pipelines) could need a flag to
  433. * tell them about such special cases.
  434. */
  435. /* completion is reported through a callback */
  436. void (*complete)(void *context);
  437. void *context;
  438. unsigned actual_length;
  439. int status;
  440. /* for optional use by whatever driver currently owns the
  441. * spi_message ... between calls to spi_async and then later
  442. * complete(), that's the spi_master controller driver.
  443. */
  444. struct list_head queue;
  445. void *state;
  446. };
  447. static inline void spi_message_init(struct spi_message *m)
  448. {
  449. memset(m, 0, sizeof *m);
  450. INIT_LIST_HEAD(&m->transfers);
  451. }
  452. static inline void
  453. spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
  454. {
  455. list_add_tail(&t->transfer_list, &m->transfers);
  456. }
  457. static inline void
  458. spi_transfer_del(struct spi_transfer *t)
  459. {
  460. list_del(&t->transfer_list);
  461. }
  462. /* It's fine to embed message and transaction structures in other data
  463. * structures so long as you don't free them while they're in use.
  464. */
  465. static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
  466. {
  467. struct spi_message *m;
  468. m = kzalloc(sizeof(struct spi_message)
  469. + ntrans * sizeof(struct spi_transfer),
  470. flags);
  471. if (m) {
  472. int i;
  473. struct spi_transfer *t = (struct spi_transfer *)(m + 1);
  474. INIT_LIST_HEAD(&m->transfers);
  475. for (i = 0; i < ntrans; i++, t++)
  476. spi_message_add_tail(t, m);
  477. }
  478. return m;
  479. }
  480. static inline void spi_message_free(struct spi_message *m)
  481. {
  482. kfree(m);
  483. }
  484. extern int spi_setup(struct spi_device *spi);
  485. extern int spi_async(struct spi_device *spi, struct spi_message *message);
  486. /*---------------------------------------------------------------------------*/
  487. /* All these synchronous SPI transfer routines are utilities layered
  488. * over the core async transfer primitive. Here, "synchronous" means
  489. * they will sleep uninterruptibly until the async transfer completes.
  490. */
  491. extern int spi_sync(struct spi_device *spi, struct spi_message *message);
  492. /**
  493. * spi_write - SPI synchronous write
  494. * @spi: device to which data will be written
  495. * @buf: data buffer
  496. * @len: data buffer size
  497. * Context: can sleep
  498. *
  499. * This writes the buffer and returns zero or a negative error code.
  500. * Callable only from contexts that can sleep.
  501. */
  502. static inline int
  503. spi_write(struct spi_device *spi, const u8 *buf, size_t len)
  504. {
  505. struct spi_transfer t = {
  506. .tx_buf = buf,
  507. .len = len,
  508. };
  509. struct spi_message m;
  510. spi_message_init(&m);
  511. spi_message_add_tail(&t, &m);
  512. return spi_sync(spi, &m);
  513. }
  514. /**
  515. * spi_read - SPI synchronous read
  516. * @spi: device from which data will be read
  517. * @buf: data buffer
  518. * @len: data buffer size
  519. * Context: can sleep
  520. *
  521. * This reads the buffer and returns zero or a negative error code.
  522. * Callable only from contexts that can sleep.
  523. */
  524. static inline int
  525. spi_read(struct spi_device *spi, u8 *buf, size_t len)
  526. {
  527. struct spi_transfer t = {
  528. .rx_buf = buf,
  529. .len = len,
  530. };
  531. struct spi_message m;
  532. spi_message_init(&m);
  533. spi_message_add_tail(&t, &m);
  534. return spi_sync(spi, &m);
  535. }
  536. /* this copies txbuf and rxbuf data; for small transfers only! */
  537. extern int spi_write_then_read(struct spi_device *spi,
  538. const u8 *txbuf, unsigned n_tx,
  539. u8 *rxbuf, unsigned n_rx);
  540. /**
  541. * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
  542. * @spi: device with which data will be exchanged
  543. * @cmd: command to be written before data is read back
  544. * Context: can sleep
  545. *
  546. * This returns the (unsigned) eight bit number returned by the
  547. * device, or else a negative error code. Callable only from
  548. * contexts that can sleep.
  549. */
  550. static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
  551. {
  552. ssize_t status;
  553. u8 result;
  554. status = spi_write_then_read(spi, &cmd, 1, &result, 1);
  555. /* return negative errno or unsigned value */
  556. return (status < 0) ? status : result;
  557. }
  558. /**
  559. * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
  560. * @spi: device with which data will be exchanged
  561. * @cmd: command to be written before data is read back
  562. * Context: can sleep
  563. *
  564. * This returns the (unsigned) sixteen bit number returned by the
  565. * device, or else a negative error code. Callable only from
  566. * contexts that can sleep.
  567. *
  568. * The number is returned in wire-order, which is at least sometimes
  569. * big-endian.
  570. */
  571. static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
  572. {
  573. ssize_t status;
  574. u16 result;
  575. status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2);
  576. /* return negative errno or unsigned value */
  577. return (status < 0) ? status : result;
  578. }
  579. /*---------------------------------------------------------------------------*/
  580. /*
  581. * INTERFACE between board init code and SPI infrastructure.
  582. *
  583. * No SPI driver ever sees these SPI device table segments, but
  584. * it's how the SPI core (or adapters that get hotplugged) grows
  585. * the driver model tree.
  586. *
  587. * As a rule, SPI devices can't be probed. Instead, board init code
  588. * provides a table listing the devices which are present, with enough
  589. * information to bind and set up the device's driver. There's basic
  590. * support for nonstatic configurations too; enough to handle adding
  591. * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
  592. */
  593. /**
  594. * struct spi_board_info - board-specific template for a SPI device
  595. * @modalias: Initializes spi_device.modalias; identifies the driver.
  596. * @platform_data: Initializes spi_device.platform_data; the particular
  597. * data stored there is driver-specific.
  598. * @controller_data: Initializes spi_device.controller_data; some
  599. * controllers need hints about hardware setup, e.g. for DMA.
  600. * @irq: Initializes spi_device.irq; depends on how the board is wired.
  601. * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
  602. * from the chip datasheet and board-specific signal quality issues.
  603. * @bus_num: Identifies which spi_master parents the spi_device; unused
  604. * by spi_new_device(), and otherwise depends on board wiring.
  605. * @chip_select: Initializes spi_device.chip_select; depends on how
  606. * the board is wired.
  607. * @mode: Initializes spi_device.mode; based on the chip datasheet, board
  608. * wiring (some devices support both 3WIRE and standard modes), and
  609. * possibly presence of an inverter in the chipselect path.
  610. *
  611. * When adding new SPI devices to the device tree, these structures serve
  612. * as a partial device template. They hold information which can't always
  613. * be determined by drivers. Information that probe() can establish (such
  614. * as the default transfer wordsize) is not included here.
  615. *
  616. * These structures are used in two places. Their primary role is to
  617. * be stored in tables of board-specific device descriptors, which are
  618. * declared early in board initialization and then used (much later) to
  619. * populate a controller's device tree after the that controller's driver
  620. * initializes. A secondary (and atypical) role is as a parameter to
  621. * spi_new_device() call, which happens after those controller drivers
  622. * are active in some dynamic board configuration models.
  623. */
  624. struct spi_board_info {
  625. /* the device name and module name are coupled, like platform_bus;
  626. * "modalias" is normally the driver name.
  627. *
  628. * platform_data goes to spi_device.dev.platform_data,
  629. * controller_data goes to spi_device.controller_data,
  630. * irq is copied too
  631. */
  632. char modalias[SPI_NAME_SIZE];
  633. const void *platform_data;
  634. void *controller_data;
  635. int irq;
  636. /* slower signaling on noisy or low voltage boards */
  637. u32 max_speed_hz;
  638. /* bus_num is board specific and matches the bus_num of some
  639. * spi_master that will probably be registered later.
  640. *
  641. * chip_select reflects how this chip is wired to that master;
  642. * it's less than num_chipselect.
  643. */
  644. u16 bus_num;
  645. u16 chip_select;
  646. /* mode becomes spi_device.mode, and is essential for chips
  647. * where the default of SPI_CS_HIGH = 0 is wrong.
  648. */
  649. u8 mode;
  650. /* ... may need additional spi_device chip config data here.
  651. * avoid stuff protocol drivers can set; but include stuff
  652. * needed to behave without being bound to a driver:
  653. * - quirks like clock rate mattering when not selected
  654. */
  655. };
  656. #ifdef CONFIG_SPI
  657. extern int
  658. spi_register_board_info(struct spi_board_info const *info, unsigned n);
  659. #else
  660. /* board init code may ignore whether SPI is configured or not */
  661. static inline int
  662. spi_register_board_info(struct spi_board_info const *info, unsigned n)
  663. { return 0; }
  664. #endif
  665. /* If you're hotplugging an adapter with devices (parport, usb, etc)
  666. * use spi_new_device() to describe each device. You can also call
  667. * spi_unregister_device() to start making that device vanish, but
  668. * normally that would be handled by spi_unregister_master().
  669. *
  670. * You can also use spi_alloc_device() and spi_add_device() to use a two
  671. * stage registration sequence for each spi_device. This gives the caller
  672. * some more control over the spi_device structure before it is registered,
  673. * but requires that caller to initialize fields that would otherwise
  674. * be defined using the board info.
  675. */
  676. extern struct spi_device *
  677. spi_alloc_device(struct spi_master *master);
  678. extern int
  679. spi_add_device(struct spi_device *spi);
  680. extern struct spi_device *
  681. spi_new_device(struct spi_master *, struct spi_board_info *);
  682. static inline void
  683. spi_unregister_device(struct spi_device *spi)
  684. {
  685. if (spi)
  686. device_unregister(&spi->dev);
  687. }
  688. extern const struct spi_device_id *
  689. spi_get_device_id(const struct spi_device *sdev);
  690. #endif /* __LINUX_SPI_H */