/include/linux/spi/dw_spi.h
C++ Header | 217 lines | 170 code | 29 blank | 18 comment | 2 complexity | f7e58532194a8175c00b1a696af67a64 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1#ifndef DW_SPI_HEADER_H 2#define DW_SPI_HEADER_H 3#include <linux/io.h> 4 5/* Bit fields in CTRLR0 */ 6#define SPI_DFS_OFFSET 0 7 8#define SPI_FRF_OFFSET 4 9#define SPI_FRF_SPI 0x0 10#define SPI_FRF_SSP 0x1 11#define SPI_FRF_MICROWIRE 0x2 12#define SPI_FRF_RESV 0x3 13 14#define SPI_MODE_OFFSET 6 15#define SPI_SCPH_OFFSET 6 16#define SPI_SCOL_OFFSET 7 17#define SPI_TMOD_OFFSET 8 18#define SPI_TMOD_TR 0x0 /* xmit & recv */ 19#define SPI_TMOD_TO 0x1 /* xmit only */ 20#define SPI_TMOD_RO 0x2 /* recv only */ 21#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 22 23#define SPI_SLVOE_OFFSET 10 24#define SPI_SRL_OFFSET 11 25#define SPI_CFS_OFFSET 12 26 27/* Bit fields in SR, 7 bits */ 28#define SR_MASK 0x7f /* cover 7 bits */ 29#define SR_BUSY (1 << 0) 30#define SR_TF_NOT_FULL (1 << 1) 31#define SR_TF_EMPT (1 << 2) 32#define SR_RF_NOT_EMPT (1 << 3) 33#define SR_RF_FULL (1 << 4) 34#define SR_TX_ERR (1 << 5) 35#define SR_DCOL (1 << 6) 36 37/* Bit fields in ISR, IMR, RISR, 7 bits */ 38#define SPI_INT_TXEI (1 << 0) 39#define SPI_INT_TXOI (1 << 1) 40#define SPI_INT_RXUI (1 << 2) 41#define SPI_INT_RXOI (1 << 3) 42#define SPI_INT_RXFI (1 << 4) 43#define SPI_INT_MSTI (1 << 5) 44 45/* TX RX interrupt level threshhold, max can be 256 */ 46#define SPI_INT_THRESHOLD 32 47 48enum dw_ssi_type { 49 SSI_MOTO_SPI = 0, 50 SSI_TI_SSP, 51 SSI_NS_MICROWIRE, 52}; 53 54struct dw_spi_reg { 55 u32 ctrl0; 56 u32 ctrl1; 57 u32 ssienr; 58 u32 mwcr; 59 u32 ser; 60 u32 baudr; 61 u32 txfltr; 62 u32 rxfltr; 63 u32 txflr; 64 u32 rxflr; 65 u32 sr; 66 u32 imr; 67 u32 isr; 68 u32 risr; 69 u32 txoicr; 70 u32 rxoicr; 71 u32 rxuicr; 72 u32 msticr; 73 u32 icr; 74 u32 dmacr; 75 u32 dmatdlr; 76 u32 dmardlr; 77 u32 idr; 78 u32 version; 79 u32 dr; /* Currently oper as 32 bits, 80 though only low 16 bits matters */ 81} __packed; 82 83struct dw_spi { 84 struct spi_master *master; 85 struct spi_device *cur_dev; 86 struct device *parent_dev; 87 enum dw_ssi_type type; 88 89 void __iomem *regs; 90 unsigned long paddr; 91 u32 iolen; 92 int irq; 93 u32 fifo_len; /* depth of the FIFO buffer */ 94 u32 max_freq; /* max bus freq supported */ 95 96 u16 bus_num; 97 u16 num_cs; /* supported slave numbers */ 98 99 /* Driver message queue */ 100 struct workqueue_struct *workqueue; 101 struct work_struct pump_messages; 102 spinlock_t lock; 103 struct list_head queue; 104 int busy; 105 int run; 106 107 /* Message Transfer pump */ 108 struct tasklet_struct pump_transfers; 109 110 /* Current message transfer state info */ 111 struct spi_message *cur_msg; 112 struct spi_transfer *cur_transfer; 113 struct chip_data *cur_chip; 114 struct chip_data *prev_chip; 115 size_t len; 116 void *tx; 117 void *tx_end; 118 void *rx; 119 void *rx_end; 120 int dma_mapped; 121 dma_addr_t rx_dma; 122 dma_addr_t tx_dma; 123 size_t rx_map_len; 124 size_t tx_map_len; 125 u8 n_bytes; /* current is a 1/2 bytes op */ 126 u8 max_bits_per_word; /* maxim is 16b */ 127 u32 dma_width; 128 int cs_change; 129 int (*write)(struct dw_spi *dws); 130 int (*read)(struct dw_spi *dws); 131 irqreturn_t (*transfer_handler)(struct dw_spi *dws); 132 void (*cs_control)(u32 command); 133 134 /* Dma info */ 135 int dma_inited; 136 struct dma_chan *txchan; 137 struct dma_chan *rxchan; 138 int txdma_done; 139 int rxdma_done; 140 u64 tx_param; 141 u64 rx_param; 142 struct device *dma_dev; 143 dma_addr_t dma_addr; 144 145 /* Bus interface info */ 146 void *priv; 147#ifdef CONFIG_DEBUG_FS 148 struct dentry *debugfs; 149#endif 150}; 151 152#define dw_readl(dw, name) \ 153 __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name)) 154#define dw_writel(dw, name, val) \ 155 __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name)) 156#define dw_readw(dw, name) \ 157 __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name)) 158#define dw_writew(dw, name, val) \ 159 __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name)) 160 161static inline void spi_enable_chip(struct dw_spi *dws, int enable) 162{ 163 dw_writel(dws, ssienr, (enable ? 1 : 0)); 164} 165 166static inline void spi_set_clk(struct dw_spi *dws, u16 div) 167{ 168 dw_writel(dws, baudr, div); 169} 170 171static inline void spi_chip_sel(struct dw_spi *dws, u16 cs) 172{ 173 if (cs > dws->num_cs) 174 return; 175 176 if (dws->cs_control) 177 dws->cs_control(1); 178 179 dw_writel(dws, ser, 1 << cs); 180} 181 182/* Disable IRQ bits */ 183static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 184{ 185 u32 new_mask; 186 187 new_mask = dw_readl(dws, imr) & ~mask; 188 dw_writel(dws, imr, new_mask); 189} 190 191/* Enable IRQ bits */ 192static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 193{ 194 u32 new_mask; 195 196 new_mask = dw_readl(dws, imr) | mask; 197 dw_writel(dws, imr, new_mask); 198} 199 200/* 201 * Each SPI slave device to work with dw_api controller should 202 * has such a structure claiming its working mode (PIO/DMA etc), 203 * which can be save in the "controller_data" member of the 204 * struct spi_device 205 */ 206struct dw_spi_chip { 207 u8 poll_mode; /* 0 for contoller polling mode */ 208 u8 type; /* SPI/SSP/Micrwire */ 209 u8 enable_dma; 210 void (*cs_control)(u32 command); 211}; 212 213extern int dw_spi_add_host(struct dw_spi *dws); 214extern void dw_spi_remove_host(struct dw_spi *dws); 215extern int dw_spi_suspend_host(struct dw_spi *dws); 216extern int dw_spi_resume_host(struct dw_spi *dws); 217#endif /* DW_SPI_HEADER_H */