/include/linux/spi/dw_spi.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35 · C++ Header · 217 lines · 170 code · 29 blank · 18 comment · 2 complexity · f7e58532194a8175c00b1a696af67a64 MD5 · raw file

  1. #ifndef DW_SPI_HEADER_H
  2. #define DW_SPI_HEADER_H
  3. #include <linux/io.h>
  4. /* Bit fields in CTRLR0 */
  5. #define SPI_DFS_OFFSET 0
  6. #define SPI_FRF_OFFSET 4
  7. #define SPI_FRF_SPI 0x0
  8. #define SPI_FRF_SSP 0x1
  9. #define SPI_FRF_MICROWIRE 0x2
  10. #define SPI_FRF_RESV 0x3
  11. #define SPI_MODE_OFFSET 6
  12. #define SPI_SCPH_OFFSET 6
  13. #define SPI_SCOL_OFFSET 7
  14. #define SPI_TMOD_OFFSET 8
  15. #define SPI_TMOD_TR 0x0 /* xmit & recv */
  16. #define SPI_TMOD_TO 0x1 /* xmit only */
  17. #define SPI_TMOD_RO 0x2 /* recv only */
  18. #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
  19. #define SPI_SLVOE_OFFSET 10
  20. #define SPI_SRL_OFFSET 11
  21. #define SPI_CFS_OFFSET 12
  22. /* Bit fields in SR, 7 bits */
  23. #define SR_MASK 0x7f /* cover 7 bits */
  24. #define SR_BUSY (1 << 0)
  25. #define SR_TF_NOT_FULL (1 << 1)
  26. #define SR_TF_EMPT (1 << 2)
  27. #define SR_RF_NOT_EMPT (1 << 3)
  28. #define SR_RF_FULL (1 << 4)
  29. #define SR_TX_ERR (1 << 5)
  30. #define SR_DCOL (1 << 6)
  31. /* Bit fields in ISR, IMR, RISR, 7 bits */
  32. #define SPI_INT_TXEI (1 << 0)
  33. #define SPI_INT_TXOI (1 << 1)
  34. #define SPI_INT_RXUI (1 << 2)
  35. #define SPI_INT_RXOI (1 << 3)
  36. #define SPI_INT_RXFI (1 << 4)
  37. #define SPI_INT_MSTI (1 << 5)
  38. /* TX RX interrupt level threshhold, max can be 256 */
  39. #define SPI_INT_THRESHOLD 32
  40. enum dw_ssi_type {
  41. SSI_MOTO_SPI = 0,
  42. SSI_TI_SSP,
  43. SSI_NS_MICROWIRE,
  44. };
  45. struct dw_spi_reg {
  46. u32 ctrl0;
  47. u32 ctrl1;
  48. u32 ssienr;
  49. u32 mwcr;
  50. u32 ser;
  51. u32 baudr;
  52. u32 txfltr;
  53. u32 rxfltr;
  54. u32 txflr;
  55. u32 rxflr;
  56. u32 sr;
  57. u32 imr;
  58. u32 isr;
  59. u32 risr;
  60. u32 txoicr;
  61. u32 rxoicr;
  62. u32 rxuicr;
  63. u32 msticr;
  64. u32 icr;
  65. u32 dmacr;
  66. u32 dmatdlr;
  67. u32 dmardlr;
  68. u32 idr;
  69. u32 version;
  70. u32 dr; /* Currently oper as 32 bits,
  71. though only low 16 bits matters */
  72. } __packed;
  73. struct dw_spi {
  74. struct spi_master *master;
  75. struct spi_device *cur_dev;
  76. struct device *parent_dev;
  77. enum dw_ssi_type type;
  78. void __iomem *regs;
  79. unsigned long paddr;
  80. u32 iolen;
  81. int irq;
  82. u32 fifo_len; /* depth of the FIFO buffer */
  83. u32 max_freq; /* max bus freq supported */
  84. u16 bus_num;
  85. u16 num_cs; /* supported slave numbers */
  86. /* Driver message queue */
  87. struct workqueue_struct *workqueue;
  88. struct work_struct pump_messages;
  89. spinlock_t lock;
  90. struct list_head queue;
  91. int busy;
  92. int run;
  93. /* Message Transfer pump */
  94. struct tasklet_struct pump_transfers;
  95. /* Current message transfer state info */
  96. struct spi_message *cur_msg;
  97. struct spi_transfer *cur_transfer;
  98. struct chip_data *cur_chip;
  99. struct chip_data *prev_chip;
  100. size_t len;
  101. void *tx;
  102. void *tx_end;
  103. void *rx;
  104. void *rx_end;
  105. int dma_mapped;
  106. dma_addr_t rx_dma;
  107. dma_addr_t tx_dma;
  108. size_t rx_map_len;
  109. size_t tx_map_len;
  110. u8 n_bytes; /* current is a 1/2 bytes op */
  111. u8 max_bits_per_word; /* maxim is 16b */
  112. u32 dma_width;
  113. int cs_change;
  114. int (*write)(struct dw_spi *dws);
  115. int (*read)(struct dw_spi *dws);
  116. irqreturn_t (*transfer_handler)(struct dw_spi *dws);
  117. void (*cs_control)(u32 command);
  118. /* Dma info */
  119. int dma_inited;
  120. struct dma_chan *txchan;
  121. struct dma_chan *rxchan;
  122. int txdma_done;
  123. int rxdma_done;
  124. u64 tx_param;
  125. u64 rx_param;
  126. struct device *dma_dev;
  127. dma_addr_t dma_addr;
  128. /* Bus interface info */
  129. void *priv;
  130. #ifdef CONFIG_DEBUG_FS
  131. struct dentry *debugfs;
  132. #endif
  133. };
  134. #define dw_readl(dw, name) \
  135. __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
  136. #define dw_writel(dw, name, val) \
  137. __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
  138. #define dw_readw(dw, name) \
  139. __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
  140. #define dw_writew(dw, name, val) \
  141. __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
  142. static inline void spi_enable_chip(struct dw_spi *dws, int enable)
  143. {
  144. dw_writel(dws, ssienr, (enable ? 1 : 0));
  145. }
  146. static inline void spi_set_clk(struct dw_spi *dws, u16 div)
  147. {
  148. dw_writel(dws, baudr, div);
  149. }
  150. static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
  151. {
  152. if (cs > dws->num_cs)
  153. return;
  154. if (dws->cs_control)
  155. dws->cs_control(1);
  156. dw_writel(dws, ser, 1 << cs);
  157. }
  158. /* Disable IRQ bits */
  159. static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
  160. {
  161. u32 new_mask;
  162. new_mask = dw_readl(dws, imr) & ~mask;
  163. dw_writel(dws, imr, new_mask);
  164. }
  165. /* Enable IRQ bits */
  166. static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
  167. {
  168. u32 new_mask;
  169. new_mask = dw_readl(dws, imr) | mask;
  170. dw_writel(dws, imr, new_mask);
  171. }
  172. /*
  173. * Each SPI slave device to work with dw_api controller should
  174. * has such a structure claiming its working mode (PIO/DMA etc),
  175. * which can be save in the "controller_data" member of the
  176. * struct spi_device
  177. */
  178. struct dw_spi_chip {
  179. u8 poll_mode; /* 0 for contoller polling mode */
  180. u8 type; /* SPI/SSP/Micrwire */
  181. u8 enable_dma;
  182. void (*cs_control)(u32 command);
  183. };
  184. extern int dw_spi_add_host(struct dw_spi *dws);
  185. extern void dw_spi_remove_host(struct dw_spi *dws);
  186. extern int dw_spi_suspend_host(struct dw_spi *dws);
  187. extern int dw_spi_resume_host(struct dw_spi *dws);
  188. #endif /* DW_SPI_HEADER_H */