/include/linux/mtd/sh_flctl.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35 · C++ Header · 131 lines · 92 code · 16 blank · 23 comment · 0 complexity · 0eaba80cf93dc9f889063e71028578f5 MD5 · raw file

  1. /*
  2. * SuperH FLCTL nand controller
  3. *
  4. * Copyright © 2008 Renesas Solutions Corp.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18. */
  19. #ifndef __SH_FLCTL_H__
  20. #define __SH_FLCTL_H__
  21. #include <linux/mtd/mtd.h>
  22. #include <linux/mtd/nand.h>
  23. #include <linux/mtd/partitions.h>
  24. /* FLCTL registers */
  25. #define FLCMNCR(f) (f->reg + 0x0)
  26. #define FLCMDCR(f) (f->reg + 0x4)
  27. #define FLCMCDR(f) (f->reg + 0x8)
  28. #define FLADR(f) (f->reg + 0xC)
  29. #define FLADR2(f) (f->reg + 0x3C)
  30. #define FLDATAR(f) (f->reg + 0x10)
  31. #define FLDTCNTR(f) (f->reg + 0x14)
  32. #define FLINTDMACR(f) (f->reg + 0x18)
  33. #define FLBSYTMR(f) (f->reg + 0x1C)
  34. #define FLBSYCNT(f) (f->reg + 0x20)
  35. #define FLDTFIFO(f) (f->reg + 0x24)
  36. #define FLECFIFO(f) (f->reg + 0x28)
  37. #define FLTRCR(f) (f->reg + 0x2C)
  38. #define FL4ECCRESULT0(f) (f->reg + 0x80)
  39. #define FL4ECCRESULT1(f) (f->reg + 0x84)
  40. #define FL4ECCRESULT2(f) (f->reg + 0x88)
  41. #define FL4ECCRESULT3(f) (f->reg + 0x8C)
  42. #define FL4ECCCR(f) (f->reg + 0x90)
  43. #define FL4ECCCNT(f) (f->reg + 0x94)
  44. #define FLERRADR(f) (f->reg + 0x98)
  45. /* FLCMNCR control bits */
  46. #define ECCPOS2 (0x1 << 25)
  47. #define _4ECCCNTEN (0x1 << 24)
  48. #define _4ECCEN (0x1 << 23)
  49. #define _4ECCCORRECT (0x1 << 22)
  50. #define SHBUSSEL (0x1 << 20)
  51. #define SEL_16BIT (0x1 << 19)
  52. #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/
  53. #define QTSEL_E (0x1 << 17)
  54. #define ENDIAN (0x1 << 16) /* 1 = little endian */
  55. #define FCKSEL_E (0x1 << 15)
  56. #define ECCPOS_00 (0x00 << 12)
  57. #define ECCPOS_01 (0x01 << 12)
  58. #define ECCPOS_02 (0x02 << 12)
  59. #define ACM_SACCES_MODE (0x01 << 10)
  60. #define NANWF_E (0x1 << 9)
  61. #define SE_D (0x1 << 8) /* Spare area disable */
  62. #define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */
  63. #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */
  64. #define TYPESEL_SET (0x1 << 0)
  65. /* FLCMDCR control bits */
  66. #define ADRCNT2_E (0x1 << 31) /* 5byte address enable */
  67. #define ADRMD_E (0x1 << 26) /* Sector address access */
  68. #define CDSRC_E (0x1 << 25) /* Data buffer selection */
  69. #define DOSR_E (0x1 << 24) /* Status read check */
  70. #define SELRW (0x1 << 21) /* 0:read 1:write */
  71. #define DOADR_E (0x1 << 20) /* Address stage execute */
  72. #define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */
  73. #define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */
  74. #define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */
  75. #define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */
  76. #define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */
  77. #define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */
  78. /* FLTRCR control bits */
  79. #define TRSTRT (0x1 << 0) /* translation start */
  80. #define TREND (0x1 << 1) /* translation end */
  81. /* FL4ECCCR control bits */
  82. #define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */
  83. #define _4ECCEND (0x1 << 1) /* 4 symbols end */
  84. #define _4ECCEXST (0x1 << 0) /* 4 symbols exist */
  85. #define INIT_FL4ECCRESULT_VAL 0x03FF03FF
  86. #define LOOP_TIMEOUT_MAX 0x00010000
  87. struct sh_flctl {
  88. struct mtd_info mtd;
  89. struct nand_chip chip;
  90. struct platform_device *pdev;
  91. void __iomem *reg;
  92. uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */
  93. int read_bytes;
  94. int index;
  95. int seqin_column; /* column in SEQIN cmd */
  96. int seqin_page_addr; /* page_addr in SEQIN cmd */
  97. uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */
  98. int erase1_page_addr; /* page_addr in ERASE1 cmd */
  99. uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */
  100. uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */
  101. int hwecc_cant_correct[4];
  102. unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
  103. unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
  104. };
  105. struct sh_flctl_platform_data {
  106. struct mtd_partition *parts;
  107. int nr_parts;
  108. unsigned long flcmncr_val;
  109. unsigned has_hwecc:1;
  110. };
  111. static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
  112. {
  113. return container_of(mtdinfo, struct sh_flctl, mtd);
  114. }
  115. #endif /* __SH_FLCTL_H__ */