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/include/sound/ak4117.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 189 lines | 143 code | 17 blank | 29 comment | 0 complexity | 4df250dc2cce079231252601d8c8414d MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1#ifndef __SOUND_AK4117_H
  2#define __SOUND_AK4117_H
  3
  4/*
  5 *  Routines for Asahi Kasei AK4117
  6 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
  7 *
  8 *
  9 *   This program is free software; you can redistribute it and/or modify
 10 *   it under the terms of the GNU General Public License as published by
 11 *   the Free Software Foundation; either version 2 of the License, or
 12 *   (at your option) any later version.
 13 *
 14 *   This program is distributed in the hope that it will be useful,
 15 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 16 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17 *   GNU General Public License for more details.
 18 *
 19 *   You should have received a copy of the GNU General Public License
 20 *   along with this program; if not, write to the Free Software
 21 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 22 *
 23 */
 24
 25#define AK4117_REG_PWRDN	0x00	/* power down */
 26#define AK4117_REG_CLOCK	0x01	/* clock control */
 27#define AK4117_REG_IO		0x02	/* input/output control */
 28#define AK4117_REG_INT0_MASK	0x03	/* interrupt0 mask */
 29#define AK4117_REG_INT1_MASK	0x04	/* interrupt1 mask */
 30#define AK4117_REG_RCS0		0x05	/* receiver status 0 */
 31#define AK4117_REG_RCS1		0x06	/* receiver status 1 */
 32#define AK4117_REG_RCS2		0x07	/* receiver status 2 */
 33#define AK4117_REG_RXCSB0	0x08	/* RX channel status byte 0 */
 34#define AK4117_REG_RXCSB1	0x09	/* RX channel status byte 1 */
 35#define AK4117_REG_RXCSB2	0x0a	/* RX channel status byte 2 */
 36#define AK4117_REG_RXCSB3	0x0b	/* RX channel status byte 3 */
 37#define AK4117_REG_RXCSB4	0x0c	/* RX channel status byte 4 */
 38#define AK4117_REG_Pc0		0x0d	/* burst preamble Pc byte 0 */
 39#define AK4117_REG_Pc1		0x0e	/* burst preamble Pc byte 1 */
 40#define AK4117_REG_Pd0		0x0f	/* burst preamble Pd byte 0 */
 41#define AK4117_REG_Pd1		0x10	/* burst preamble Pd byte 1 */
 42#define AK4117_REG_QSUB_ADDR	0x11	/* Q-subcode address + control */
 43#define AK4117_REG_QSUB_TRACK	0x12	/* Q-subcode track */
 44#define AK4117_REG_QSUB_INDEX	0x13	/* Q-subcode index */
 45#define AK4117_REG_QSUB_MINUTE	0x14	/* Q-subcode minute */
 46#define AK4117_REG_QSUB_SECOND	0x15	/* Q-subcode second */
 47#define AK4117_REG_QSUB_FRAME	0x16	/* Q-subcode frame */
 48#define AK4117_REG_QSUB_ZERO	0x17	/* Q-subcode zero */
 49#define AK4117_REG_QSUB_ABSMIN	0x18	/* Q-subcode absolute minute */
 50#define AK4117_REG_QSUB_ABSSEC	0x19	/* Q-subcode absolute second */
 51#define AK4117_REG_QSUB_ABSFRM	0x1a	/* Q-subcode absolute frame */
 52
 53/* sizes */
 54#define AK4117_REG_RXCSB_SIZE	((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
 55#define AK4117_REG_QSUB_SIZE	((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
 56
 57/* AK4117_REG_PWRDN bits */
 58#define AK4117_EXCT		(1<<4)	/* 0 = X'tal mode, 1 = external clock mode */
 59#define AK4117_XTL1		(1<<3)	/* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
 60#define AK4117_XTL0		(1<<2)	/* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
 61#define AK4117_XTL_11_2896M	(0)
 62#define AK4117_XTL_12_288M	AK4117_XTL0
 63#define AK4117_XTL_24_576M	AK4117_XTL1
 64#define AK4117_XTL_EXT		(AK4117_XTL1|AK4117_XTL0)
 65#define AK4117_PWN		(1<<1)	/* 0 = power down, 1 = normal operation */
 66#define AK4117_RST		(1<<0)	/* 0 = reset & initialize (except this register), 1 = normal operation */
 67
 68/* AK4117_REQ_CLOCK bits */
 69#define AK4117_LP		(1<<7)	/* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
 70#define AK4117_PKCS1		(1<<6)	/* master clock frequency at PLL mode (when LP == 0) */
 71#define AK4117_PKCS0		(1<<5)
 72#define AK4117_PKCS_512fs	(0)
 73#define AK4117_PKCS_256fs	AK4117_PKCS0
 74#define AK4117_PKCS_128fs	AK4117_PKCS1
 75#define AK4117_DIV		(1<<4)	/* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
 76#define AK4117_XCKS1		(1<<3)	/* master clock frequency at X'tal mode */
 77#define AK4117_XCKS0		(1<<2)
 78#define AK4117_XCKS_128fs	(0)
 79#define AK4117_XCKS_256fs	AK4117_XCKS0
 80#define AK4117_XCKS_512fs	AK4117_XCKS1
 81#define AK4117_XCKS_1024fs	(AK4117_XCKS1|AK4117_XCKS0)
 82#define AK4117_CM1		(1<<1)	/* MCKO operation mode select */
 83#define AK4117_CM0		(1<<0)
 84#define AK4117_CM_PLL		(0)		/* use RX input as master clock */
 85#define AK4117_CM_XTAL		(AK4117_CM0)	/* use X'tal as master clock */
 86#define AK4117_CM_PLL_XTAL	(AK4117_CM1)	/* use Rx input but X'tal when PLL loses lock */
 87#define AK4117_CM_MONITOR	(AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */
 88
 89/* AK4117_REG_IO */
 90#define AK4117_IPS		(1<<7)	/* Input Recovery Data Select, 0 = RX0, 1 = RX1 */
 91#define AK4117_UOUTE		(1<<6)	/* U-bit output enable to UOUT, 0 = disable, 1 = enable */
 92#define AK4117_CS12		(1<<5)	/* channel status select, 0 = channel1, 1 = channel2 */
 93#define AK4117_EFH2		(1<<4)	/* INT0 pin hold count select */
 94#define AK4117_EFH1		(1<<3)
 95#define AK4117_EFH_512LRCLK	(0)
 96#define AK4117_EFH_1024LRCLK	(AK4117_EFH1)
 97#define AK4117_EFH_2048LRCLK	(AK4117_EFH2)
 98#define AK4117_EFH_4096LRCLK	(AK4117_EFH1|AK4117_EFH2)
 99#define AK4117_DIF2		(1<<2)	/* audio data format control */
100#define AK4117_DIF1		(1<<1)
101#define AK4117_DIF0		(1<<0)
102#define AK4117_DIF_16R		(0)				/* STDO: 16-bit, right justified */
103#define AK4117_DIF_18R		(AK4117_DIF0)			/* STDO: 18-bit, right justified */
104#define AK4117_DIF_20R		(AK4117_DIF1)			/* STDO: 20-bit, right justified */
105#define AK4117_DIF_24R		(AK4117_DIF1|AK4117_DIF0)	/* STDO: 24-bit, right justified */
106#define AK4117_DIF_24L		(AK4117_DIF2)			/* STDO: 24-bit, left justified */
107#define AK4117_DIF_24I2S	(AK4117_DIF2|AK4117_DIF0)	/* STDO: I2S */
108
109/* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */
110#define AK4117_MULK		(1<<7)	/* mask enable for UNLOCK bit */
111#define AK4117_MPAR		(1<<6)	/* mask enable for PAR bit */
112#define AK4117_MAUTO		(1<<5)	/* mask enable for AUTO bit */
113#define AK4117_MV		(1<<4)	/* mask enable for V bit */
114#define AK4117_MAUD		(1<<3)	/* mask enable for AUDION bit */
115#define AK4117_MSTC		(1<<2)	/* mask enable for STC bit */
116#define AK4117_MCIT		(1<<1)	/* mask enable for CINT bit */
117#define AK4117_MQIT		(1<<0)	/* mask enable for QINT bit */
118
119/* AK4117_REG_RCS0 */
120#define AK4117_UNLCK		(1<<7)	/* PLL lock status, 0 = lock, 1 = unlock */
121#define AK4117_PAR		(1<<6)	/* parity error or biphase error status, 0 = no error, 1 = error */
122#define AK4117_AUTO		(1<<5)	/* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
123#define AK4117_V		(1<<4)	/* Validity bit, 0 = valid, 1 = invalid */
124#define AK4117_AUDION		(1<<3)	/* audio bit output, 0 = audio, 1 = non-audio */
125#define AK4117_STC		(1<<2)	/* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
126#define AK4117_CINT		(1<<1)	/* channel status buffer interrupt, 0 = no change, 1 = change */
127#define AK4117_QINT		(1<<0)	/* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
128
129/* AK4117_REG_RCS1 */
130#define AK4117_DTSCD		(1<<6)	/* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
131#define AK4117_NPCM		(1<<5)	/* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
132#define AK4117_PEM		(1<<4)	/* Pre-emphasis detect, 0 = OFF, 1 = ON */
133#define AK4117_FS3		(1<<3)	/* sampling frequency detection */
134#define AK4117_FS2		(1<<2)
135#define AK4117_FS1		(1<<1)
136#define AK4117_FS0		(1<<0)
137#define AK4117_FS_44100HZ	(0)
138#define AK4117_FS_48000HZ	(AK4117_FS1)
139#define AK4117_FS_32000HZ	(AK4117_FS1|AK4117_FS0)
140#define AK4117_FS_88200HZ	(AK4117_FS3)
141#define AK4117_FS_96000HZ	(AK4117_FS3|AK4117_FS1)
142#define AK4117_FS_176400HZ	(AK4117_FS3|AK4117_FS2)
143#define AK4117_FS_192000HZ	(AK4117_FS3|AK4117_FS2|AK4117_FS1)
144
145/* AK4117_REG_RCS2 */
146#define AK4117_CCRC		(1<<1)	/* CRC for channel status, 0 = no error, 1 = error */
147#define AK4117_QCRC		(1<<0)	/* CRC for Q-subcode, 0 = no error, 1 = error */
148
149/* flags for snd_ak4117_check_rate_and_errors() */
150#define AK4117_CHECK_NO_STAT	(1<<0)	/* no statistics */
151#define AK4117_CHECK_NO_RATE	(1<<1)	/* no rate check */
152
153#define AK4117_CONTROLS		13
154
155typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data);
156typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr);
157
158struct ak4117 {
159	struct snd_card *card;
160	ak4117_write_t * write;
161	ak4117_read_t * read;
162	void * private_data;
163	unsigned int init: 1;
164	spinlock_t lock;
165	unsigned char regmap[5];
166	struct snd_kcontrol *kctls[AK4117_CONTROLS];
167	struct snd_pcm_substream *substream;
168	unsigned long parity_errors;
169	unsigned long v_bit_errors;
170	unsigned long qcrc_errors;
171	unsigned long ccrc_errors;
172	unsigned char rcs0;
173	unsigned char rcs1;
174	unsigned char rcs2;
175	struct timer_list timer;	/* statistic timer */
176	void *change_callback_private;
177	void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1);
178};
179
180int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
181		      const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117);
182void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val);
183void snd_ak4117_reinit(struct ak4117 *ak4117);
184int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream);
185int snd_ak4117_external_rate(struct ak4117 *ak4117);
186int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags);
187
188#endif /* __SOUND_AK4117_H */
189