/include/sound/cs46xx_dsp_scb_types.h

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  1. /*
  2. * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
  3. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. *
  21. * NOTE: comments are copy/paste from cwcemb80.lst
  22. * provided by Tom Woller at Cirrus (my only
  23. * documentation about the SP OS running inside
  24. * the DSP)
  25. */
  26. #ifndef __CS46XX_DSP_SCB_TYPES_H__
  27. #define __CS46XX_DSP_SCB_TYPES_H__
  28. #include <asm/byteorder.h>
  29. #ifndef ___DSP_DUAL_16BIT_ALLOC
  30. #if defined(__LITTLE_ENDIAN)
  31. #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 a; u16 b;
  32. #elif defined(__BIG_ENDIAN)
  33. #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 b; u16 a;
  34. #else
  35. #error Not __LITTLE_ENDIAN and not __BIG_ENDIAN, then what ???
  36. #endif
  37. #endif
  38. /* This structs are used internally by the SP */
  39. struct dsp_basic_dma_req {
  40. /* DMA Requestor Word 0 (DCW) fields:
  41. 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
  42. _______________________________________________________________________________________
  43. |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword |
  44. |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
  45. */
  46. u32 dcw; /* DMA Control Word */
  47. u32 dmw; /* DMA Mode Word */
  48. u32 saw; /* Source Address Word */
  49. u32 daw; /* Destination Address Word */
  50. };
  51. struct dsp_scatter_gather_ext {
  52. u32 npaw; /* Next-Page Address Word */
  53. /* DMA Requestor Word 5 (NPCW) fields:
  54. 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
  55. _________________________________________________________________________________________
  56. |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
  57. |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
  58. */
  59. u32 npcw; /* Next-Page Control Word */
  60. u32 lbaw; /* Loop-Begin Address Word */
  61. u32 nplbaw; /* Next-Page after Loop-Begin Address Word */
  62. u32 sgaw; /* Scatter/Gather Address Word */
  63. };
  64. struct dsp_volume_control {
  65. ___DSP_DUAL_16BIT_ALLOC(
  66. rightTarg, /* Target volume for left & right channels */
  67. leftTarg
  68. )
  69. ___DSP_DUAL_16BIT_ALLOC(
  70. rightVol, /* Current left & right channel volumes */
  71. leftVol
  72. )
  73. };
  74. /* Generic stream control block (SCB) structure definition */
  75. struct dsp_generic_scb {
  76. /* For streaming I/O, the DSP should never alter any words in the DMA
  77. requestor or the scatter/gather extension. Only ad hoc DMA request
  78. streams are free to alter the requestor (currently only occur in the
  79. DOS-based MIDI controller and in debugger-inserted code).
  80. If an SCB does not have any associated DMA requestor, these 9 ints
  81. may be freed for use by other tasks, but the pointer to the SCB must
  82. still be such that the insOrd:nextSCB appear at offset 9 from the
  83. SCB pointer.
  84. Basic (non scatter/gather) DMA requestor (4 ints)
  85. */
  86. /* Initialized by the host, only modified by DMA
  87. R/O for the DSP task */
  88. struct dsp_basic_dma_req basic_req; /* Optional */
  89. /* Scatter/gather DMA requestor extension (5 ints)
  90. Initialized by the host, only modified by DMA
  91. DSP task never needs to even read these.
  92. */
  93. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  94. /* Sublist pointer & next stream control block (SCB) link.
  95. Initialized & modified by the host R/O for the DSP task
  96. */
  97. ___DSP_DUAL_16BIT_ALLOC(
  98. next_scb, /* REQUIRED */
  99. sub_list_ptr /* REQUIRED */
  100. )
  101. /* Pointer to this tasks parameter block & stream function pointer
  102. Initialized by the host R/O for the DSP task */
  103. ___DSP_DUAL_16BIT_ALLOC(
  104. entry_point, /* REQUIRED */
  105. this_spb /* REQUIRED */
  106. )
  107. /* rsConfig register for stream buffer (rsDMA reg.
  108. is loaded from basicReq.daw for incoming streams, or
  109. basicReq.saw, for outgoing streams)
  110. 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
  111. ______________________________________________________________________________
  112. |DMA |D|maxDMAsize| streamNum|dir|p| | | | | | |ds |shr 1|rev Cy | mod |
  113. |prio |_|__________|__________|___|_|__|__|__|__|_|_|___|_____|_______|_______|
  114. 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
  115. Initialized by the host R/O for the DSP task
  116. */
  117. u32 strm_rs_config; /* REQUIRED */
  118. //
  119. /* On mixer input streams: indicates mixer input stream configuration
  120. On Tees, this is copied from the stream being snooped
  121. Stream sample pointer & MAC-unit mode for this stream
  122. Initialized by the host Updated by the DSP task
  123. */
  124. u32 strm_buf_ptr; /* REQUIRED */
  125. /* On mixer input streams: points to next mixer input and is updated by the
  126. mixer subroutine in the "parent" DSP task
  127. (least-significant 16 bits are preserved, unused)
  128. On Tees, the pointer is copied from the stream being snooped on
  129. initialization, and, subsequently, it is copied into the
  130. stream being snooped.
  131. On wavetable/3D voices: the strmBufPtr will use all 32 bits to allow for
  132. fractional phase accumulation
  133. Fractional increment per output sample in the input sample buffer
  134. (Not used on mixer input streams & redefined on Tees)
  135. On wavetable/3D voices: this 32-bit word specifies the integer.fractional
  136. increment per output sample.
  137. */
  138. u32 strmPhiIncr;
  139. /* Standard stereo volume control
  140. Initialized by the host (host updates target volumes)
  141. Current volumes update by the DSP task
  142. On mixer input streams: required & updated by the mixer subroutine in the
  143. "parent" DSP task
  144. On Tees, both current & target volumes are copied up on initialization,
  145. and, subsequently, the target volume is copied up while the current
  146. volume is copied down.
  147. These two 32-bit words are redefined for wavetable & 3-D voices.
  148. */
  149. struct dsp_volume_control vol_ctrl_t; /* Optional */
  150. };
  151. struct dsp_spos_control_block {
  152. /* WARNING: Certain items in this structure are modified by the host
  153. Any dword that can be modified by the host, must not be
  154. modified by the SP as the host can only do atomic dword
  155. writes, and to do otherwise, even a read modify write,
  156. may lead to corrupted data on the SP.
  157. This rule does not apply to one off boot time initialisation prior to starting the SP
  158. */
  159. ___DSP_DUAL_16BIT_ALLOC(
  160. /* First element on the Hyper forground task tree */
  161. hfg_tree_root_ptr, /* HOST */
  162. /* First 3 dwords are written by the host and read-only on the DSP */
  163. hfg_stack_base /* HOST */
  164. )
  165. ___DSP_DUAL_16BIT_ALLOC(
  166. /* Point to this data structure to enable easy access */
  167. spos_cb_ptr, /* SP */
  168. prev_task_tree_ptr /* SP && HOST */
  169. )
  170. ___DSP_DUAL_16BIT_ALLOC(
  171. /* Currently Unused */
  172. xxinterval_timer_period,
  173. /* Enable extension of SPOS data structure */
  174. HFGSPB_ptr
  175. )
  176. ___DSP_DUAL_16BIT_ALLOC(
  177. xxnum_HFG_ticks_thisInterval,
  178. /* Modified by the DSP */
  179. xxnum_tntervals
  180. )
  181. /* Set by DSP upon encountering a trap (breakpoint) or a spurious
  182. interrupt. The host must clear this dword after reading it
  183. upon receiving spInt1. */
  184. ___DSP_DUAL_16BIT_ALLOC(
  185. spurious_int_flag, /* (Host & SP) Nature of the spurious interrupt */
  186. trap_flag /* (Host & SP) Nature of detected Trap */
  187. )
  188. ___DSP_DUAL_16BIT_ALLOC(
  189. unused2,
  190. invalid_IP_flag /* (Host & SP ) Indicate detection of invalid instruction pointer */
  191. )
  192. ___DSP_DUAL_16BIT_ALLOC(
  193. /* pointer to forground task tree header for use in next task search */
  194. fg_task_tree_hdr_ptr, /* HOST */
  195. /* Data structure for controlling synchronous link update */
  196. hfg_sync_update_ptr /* HOST */
  197. )
  198. ___DSP_DUAL_16BIT_ALLOC(
  199. begin_foreground_FCNT, /* SP */
  200. /* Place holder for holding sleep timing */
  201. last_FCNT_before_sleep /* SP */
  202. )
  203. ___DSP_DUAL_16BIT_ALLOC(
  204. unused7, /* SP */
  205. next_task_treePtr /* SP */
  206. )
  207. u32 unused5;
  208. ___DSP_DUAL_16BIT_ALLOC(
  209. active_flags, /* SP */
  210. /* State flags, used to assist control of execution of Hyper Forground */
  211. HFG_flags /* SP */
  212. )
  213. ___DSP_DUAL_16BIT_ALLOC(
  214. unused9,
  215. unused8
  216. )
  217. /* Space for saving enough context so that we can set up enough
  218. to save some more context.
  219. */
  220. u32 rFE_save_for_invalid_IP;
  221. u32 r32_save_for_spurious_int;
  222. u32 r32_save_for_trap;
  223. u32 r32_save_for_HFG;
  224. };
  225. /* SPB for MIX_TO_OSTREAM algorithm family */
  226. struct dsp_mix2_ostream_spb
  227. {
  228. /* 16b.16b integer.frac approximation to the
  229. number of 3 sample triplets to output each
  230. frame. (approximation must be floor, to
  231. insure that the fractional error is always
  232. positive)
  233. */
  234. u32 outTripletsPerFrame;
  235. /* 16b.16b integer.frac accumulated number of
  236. output triplets since the start of group
  237. */
  238. u32 accumOutTriplets;
  239. };
  240. /* SCB for Timing master algorithm */
  241. struct dsp_timing_master_scb {
  242. /* First 12 dwords from generic_scb_t */
  243. struct dsp_basic_dma_req basic_req; /* Optional */
  244. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  245. ___DSP_DUAL_16BIT_ALLOC(
  246. next_scb, /* REQUIRED */
  247. sub_list_ptr /* REQUIRED */
  248. )
  249. ___DSP_DUAL_16BIT_ALLOC(
  250. entry_point, /* REQUIRED */
  251. this_spb /* REQUIRED */
  252. )
  253. ___DSP_DUAL_16BIT_ALLOC(
  254. /* Initial values are 0000:xxxx */
  255. reserved,
  256. extra_sample_accum
  257. )
  258. /* Initial values are xxxx:0000
  259. hi: Current CODEC output FIFO pointer
  260. (0 to 0x0f)
  261. lo: Flag indicating that the CODEC
  262. FIFO is sync'd (host clears to
  263. resynchronize the FIFO pointer
  264. upon start/restart)
  265. */
  266. ___DSP_DUAL_16BIT_ALLOC(
  267. codec_FIFO_syncd,
  268. codec_FIFO_ptr
  269. )
  270. /* Init. 8000:0005 for 44.1k
  271. 8000:0001 for 48k
  272. hi: Fractional sample accumulator 0.16b
  273. lo: Number of frames remaining to be
  274. processed in the current group of
  275. frames
  276. */
  277. ___DSP_DUAL_16BIT_ALLOC(
  278. frac_samp_accum_qm1,
  279. TM_frms_left_in_group
  280. )
  281. /* Init. 0001:0005 for 44.1k
  282. 0000:0001 for 48k
  283. hi: Fractional sample correction factor 0.16b
  284. to be added every frameGroupLength frames
  285. to correct for truncation error in
  286. nsamp_per_frm_q15
  287. lo: Number of frames in the group
  288. */
  289. ___DSP_DUAL_16BIT_ALLOC(
  290. frac_samp_correction_qm1,
  291. TM_frm_group_length
  292. )
  293. /* Init. 44.1k*65536/8k = 0x00058333 for 44.1k
  294. 48k*65536/8k = 0x00060000 for 48k
  295. 16b.16b integer.frac approximation to the
  296. number of samples to output each frame.
  297. (approximation must be floor, to insure */
  298. u32 nsamp_per_frm_q15;
  299. };
  300. /* SCB for CODEC output algorithm */
  301. struct dsp_codec_output_scb {
  302. /* First 13 dwords from generic_scb_t */
  303. struct dsp_basic_dma_req basic_req; /* Optional */
  304. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  305. ___DSP_DUAL_16BIT_ALLOC(
  306. next_scb, /* REQUIRED */
  307. sub_list_ptr /* REQUIRED */
  308. )
  309. ___DSP_DUAL_16BIT_ALLOC(
  310. entry_point, /* REQUIRED */
  311. this_spb /* REQUIRED */
  312. )
  313. u32 strm_rs_config; /* REQUIRED */
  314. u32 strm_buf_ptr; /* REQUIRED */
  315. /* NOTE: The CODEC output task reads samples from the first task on its
  316. sublist at the stream buffer pointer (init. to lag DMA destination
  317. address word). After the required number of samples is transferred,
  318. the CODEC output task advances sub_list_ptr->strm_buf_ptr past the samples
  319. consumed.
  320. */
  321. /* Init. 0000:0010 for SDout
  322. 0060:0010 for SDout2
  323. 0080:0010 for SDout3
  324. hi: Base IO address of FIFO to which
  325. the left-channel samples are to
  326. be written.
  327. lo: Displacement for the base IO
  328. address for left-channel to obtain
  329. the base IO address for the FIFO
  330. to which the right-channel samples
  331. are to be written.
  332. */
  333. ___DSP_DUAL_16BIT_ALLOC(
  334. left_chan_base_IO_addr,
  335. right_chan_IO_disp
  336. )
  337. /* Init: 0x0080:0004 for non-AC-97
  338. Init: 0x0080:0000 for AC-97
  339. hi: Exponential volume change rate
  340. for input stream
  341. lo: Positive shift count to shift the
  342. 16-bit input sample to obtain the
  343. 32-bit output word
  344. */
  345. ___DSP_DUAL_16BIT_ALLOC(
  346. CO_scale_shift_count,
  347. CO_exp_vol_change_rate
  348. )
  349. /* Pointer to SCB at end of input chain */
  350. ___DSP_DUAL_16BIT_ALLOC(
  351. reserved,
  352. last_sub_ptr
  353. )
  354. };
  355. /* SCB for CODEC input algorithm */
  356. struct dsp_codec_input_scb {
  357. /* First 13 dwords from generic_scb_t */
  358. struct dsp_basic_dma_req basic_req; /* Optional */
  359. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  360. ___DSP_DUAL_16BIT_ALLOC(
  361. next_scb, /* REQUIRED */
  362. sub_list_ptr /* REQUIRED */
  363. )
  364. ___DSP_DUAL_16BIT_ALLOC(
  365. entry_point, /* REQUIRED */
  366. this_spb /* REQUIRED */
  367. )
  368. u32 strm_rs_config; /* REQUIRED */
  369. u32 strm_buf_ptr; /* REQUIRED */
  370. /* NOTE: The CODEC input task reads samples from the hardware FIFO
  371. sublist at the DMA source address word (sub_list_ptr->basic_req.saw).
  372. After the required number of samples is transferred, the CODEC
  373. output task advances sub_list_ptr->basic_req.saw past the samples
  374. consumed. SPuD must initialize the sub_list_ptr->basic_req.saw
  375. to point half-way around from the initial sub_list_ptr->strm_nuf_ptr
  376. to allow for lag/lead.
  377. */
  378. /* Init. 0000:0010 for SDout
  379. 0060:0010 for SDout2
  380. 0080:0010 for SDout3
  381. hi: Base IO address of FIFO to which
  382. the left-channel samples are to
  383. be written.
  384. lo: Displacement for the base IO
  385. address for left-channel to obtain
  386. the base IO address for the FIFO
  387. to which the right-channel samples
  388. are to be written.
  389. */
  390. ___DSP_DUAL_16BIT_ALLOC(
  391. rightChanINdisp,
  392. left_chan_base_IN_addr
  393. )
  394. /* Init. ?:fffc
  395. lo: Negative shift count to shift the
  396. 32-bit input dword to obtain the
  397. 16-bit sample msb-aligned (count
  398. is negative to shift left)
  399. */
  400. ___DSP_DUAL_16BIT_ALLOC(
  401. scaleShiftCount,
  402. reserver1
  403. )
  404. u32 reserved2;
  405. };
  406. struct dsp_pcm_serial_input_scb {
  407. /* First 13 dwords from generic_scb_t */
  408. struct dsp_basic_dma_req basic_req; /* Optional */
  409. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  410. ___DSP_DUAL_16BIT_ALLOC(
  411. next_scb, /* REQUIRED */
  412. sub_list_ptr /* REQUIRED */
  413. )
  414. ___DSP_DUAL_16BIT_ALLOC(
  415. entry_point, /* REQUIRED */
  416. this_spb /* REQUIRED */
  417. )
  418. u32 strm_buf_ptr; /* REQUIRED */
  419. u32 strm_rs_config; /* REQUIRED */
  420. /* Init. Ptr to CODEC input SCB
  421. hi: Pointer to the SCB containing the
  422. input buffer to which CODEC input
  423. samples are written
  424. lo: Flag indicating the link to the CODEC
  425. input task is to be initialized
  426. */
  427. ___DSP_DUAL_16BIT_ALLOC(
  428. init_codec_input_link,
  429. codec_input_buf_scb
  430. )
  431. /* Initialized by the host (host updates target volumes) */
  432. struct dsp_volume_control psi_vol_ctrl;
  433. };
  434. struct dsp_src_task_scb {
  435. ___DSP_DUAL_16BIT_ALLOC(
  436. frames_left_in_gof,
  437. gofs_left_in_sec
  438. )
  439. ___DSP_DUAL_16BIT_ALLOC(
  440. const2_thirds,
  441. num_extra_tnput_samples
  442. )
  443. ___DSP_DUAL_16BIT_ALLOC(
  444. cor_per_gof,
  445. correction_per_sec
  446. )
  447. ___DSP_DUAL_16BIT_ALLOC(
  448. output_buf_producer_ptr,
  449. junk_DMA_MID
  450. )
  451. ___DSP_DUAL_16BIT_ALLOC(
  452. gof_length,
  453. gofs_per_sec
  454. )
  455. u32 input_buf_strm_config;
  456. ___DSP_DUAL_16BIT_ALLOC(
  457. reserved_for_SRC_use,
  458. input_buf_consumer_ptr
  459. )
  460. u32 accum_phi;
  461. ___DSP_DUAL_16BIT_ALLOC(
  462. exp_src_vol_change_rate,
  463. input_buf_producer_ptr
  464. )
  465. ___DSP_DUAL_16BIT_ALLOC(
  466. src_next_scb,
  467. src_sub_list_ptr
  468. )
  469. ___DSP_DUAL_16BIT_ALLOC(
  470. src_entry_point,
  471. src_this_sbp
  472. )
  473. u32 src_strm_rs_config;
  474. u32 src_strm_buf_ptr;
  475. u32 phiIncr6int_26frac;
  476. struct dsp_volume_control src_vol_ctrl;
  477. };
  478. struct dsp_decimate_by_pow2_scb {
  479. /* decimationFactor = 2, 4, or 8 (larger factors waste too much memory
  480. when compared to cascading decimators)
  481. */
  482. ___DSP_DUAL_16BIT_ALLOC(
  483. dec2_coef_base_ptr,
  484. dec2_coef_increment
  485. )
  486. /* coefIncrement = 128 / decimationFactor (for our ROM filter)
  487. coefBasePtr = 0x8000 (for our ROM filter)
  488. */
  489. ___DSP_DUAL_16BIT_ALLOC(
  490. dec2_in_samples_per_out_triplet,
  491. dec2_extra_in_samples
  492. )
  493. /* extraInSamples: # of accumulated, unused input samples (init. to 0)
  494. inSamplesPerOutTriplet = 3 * decimationFactor
  495. */
  496. ___DSP_DUAL_16BIT_ALLOC(
  497. dec2_const2_thirds,
  498. dec2_half_num_taps_mp5
  499. )
  500. /* halfNumTapsM5: (1/2 number of taps in decimation filter) minus 5
  501. const2thirds: constant 2/3 in 16Q0 format (sign.15)
  502. */
  503. ___DSP_DUAL_16BIT_ALLOC(
  504. dec2_output_buf_producer_ptr,
  505. dec2_junkdma_mid
  506. )
  507. u32 dec2_reserved2;
  508. u32 dec2_input_nuf_strm_config;
  509. /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
  510. (buffer size = decimationFactor * 32 dwords)
  511. */
  512. ___DSP_DUAL_16BIT_ALLOC(
  513. dec2_phi_incr,
  514. dec2_input_buf_consumer_ptr
  515. )
  516. /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter)
  517. phiIncr = decimationFactor * 4
  518. */
  519. u32 dec2_reserved3;
  520. ___DSP_DUAL_16BIT_ALLOC(
  521. dec2_exp_vol_change_rate,
  522. dec2_input_buf_producer_ptr
  523. )
  524. /* inputBufProducerPtr: Input buffer write pointer
  525. expVolChangeRate: Exponential volume change rate for possible
  526. future mixer on input streams
  527. */
  528. ___DSP_DUAL_16BIT_ALLOC(
  529. dec2_next_scb,
  530. dec2_sub_list_ptr
  531. )
  532. ___DSP_DUAL_16BIT_ALLOC(
  533. dec2_entry_point,
  534. dec2_this_spb
  535. )
  536. u32 dec2_strm_rs_config;
  537. u32 dec2_strm_buf_ptr;
  538. u32 dec2_reserved4;
  539. struct dsp_volume_control dec2_vol_ctrl; /* Not used! */
  540. };
  541. struct dsp_vari_decimate_scb {
  542. ___DSP_DUAL_16BIT_ALLOC(
  543. vdec_frames_left_in_gof,
  544. vdec_gofs_left_in_sec
  545. )
  546. ___DSP_DUAL_16BIT_ALLOC(
  547. vdec_const2_thirds,
  548. vdec_extra_in_samples
  549. )
  550. /* extraInSamples: # of accumulated, unused input samples (init. to 0)
  551. const2thirds: constant 2/3 in 16Q0 format (sign.15) */
  552. ___DSP_DUAL_16BIT_ALLOC(
  553. vdec_cor_per_gof,
  554. vdec_correction_per_sec
  555. )
  556. ___DSP_DUAL_16BIT_ALLOC(
  557. vdec_output_buf_producer_ptr,
  558. vdec_input_buf_consumer_ptr
  559. )
  560. /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) */
  561. ___DSP_DUAL_16BIT_ALLOC(
  562. vdec_gof_length,
  563. vdec_gofs_per_sec
  564. )
  565. u32 vdec_input_buf_strm_config;
  566. /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
  567. (buffer size = 64 dwords) */
  568. u32 vdec_coef_increment;
  569. /* coefIncrement = - 128.0 / decimationFactor (as a 32Q15 number) */
  570. u32 vdec_accumphi;
  571. /* accumPhi: accumulated fractional phase increment (6.26) */
  572. ___DSP_DUAL_16BIT_ALLOC(
  573. vdec_exp_vol_change_rate,
  574. vdec_input_buf_producer_ptr
  575. )
  576. /* inputBufProducerPtr: Input buffer write pointer
  577. expVolChangeRate: Exponential volume change rate for possible
  578. future mixer on input streams */
  579. ___DSP_DUAL_16BIT_ALLOC(
  580. vdec_next_scb,
  581. vdec_sub_list_ptr
  582. )
  583. ___DSP_DUAL_16BIT_ALLOC(
  584. vdec_entry_point,
  585. vdec_this_spb
  586. )
  587. u32 vdec_strm_rs_config;
  588. u32 vdec_strm_buf_ptr;
  589. u32 vdec_phi_incr_6int_26frac;
  590. struct dsp_volume_control vdec_vol_ctrl;
  591. };
  592. /* SCB for MIX_TO_OSTREAM algorithm family */
  593. struct dsp_mix2_ostream_scb {
  594. /* First 13 dwords from generic_scb_t */
  595. struct dsp_basic_dma_req basic_req; /* Optional */
  596. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  597. ___DSP_DUAL_16BIT_ALLOC(
  598. next_scb, /* REQUIRED */
  599. sub_list_ptr /* REQUIRED */
  600. )
  601. ___DSP_DUAL_16BIT_ALLOC(
  602. entry_point, /* REQUIRED */
  603. this_spb /* REQUIRED */
  604. )
  605. u32 strm_rs_config; /* REQUIRED */
  606. u32 strm_buf_ptr; /* REQUIRED */
  607. /* hi: Number of mixed-down input triplets
  608. computed since start of group
  609. lo: Number of frames remaining to be
  610. processed in the current group of
  611. frames
  612. */
  613. ___DSP_DUAL_16BIT_ALLOC(
  614. frames_left_in_group,
  615. accum_input_triplets
  616. )
  617. /* hi: Exponential volume change rate
  618. for mixer on input streams
  619. lo: Number of frames in the group
  620. */
  621. ___DSP_DUAL_16BIT_ALLOC(
  622. frame_group_length,
  623. exp_vol_change_rate
  624. )
  625. ___DSP_DUAL_16BIT_ALLOC(
  626. const_FFFF,
  627. const_zero
  628. )
  629. };
  630. /* SCB for S16_MIX algorithm */
  631. struct dsp_mix_only_scb {
  632. /* First 13 dwords from generic_scb_t */
  633. struct dsp_basic_dma_req basic_req; /* Optional */
  634. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  635. ___DSP_DUAL_16BIT_ALLOC(
  636. next_scb, /* REQUIRED */
  637. sub_list_ptr /* REQUIRED */
  638. )
  639. ___DSP_DUAL_16BIT_ALLOC(
  640. entry_point, /* REQUIRED */
  641. this_spb /* REQUIRED */
  642. )
  643. u32 strm_rs_config; /* REQUIRED */
  644. u32 strm_buf_ptr; /* REQUIRED */
  645. u32 reserved;
  646. struct dsp_volume_control vol_ctrl;
  647. };
  648. /* SCB for the async. CODEC input algorithm */
  649. struct dsp_async_codec_input_scb {
  650. u32 io_free2;
  651. u32 io_current_total;
  652. u32 io_previous_total;
  653. u16 io_count;
  654. u16 io_count_limit;
  655. u16 o_fifo_base_addr;
  656. u16 ost_mo_format;
  657. /* 1 = stereo; 0 = mono
  658. xxx for ASER 1 (not allowed); 118 for ASER2 */
  659. u32 ostrm_rs_config;
  660. u32 ostrm_buf_ptr;
  661. ___DSP_DUAL_16BIT_ALLOC(
  662. io_sclks_per_lr_clk,
  663. io_io_enable
  664. )
  665. u32 io_free4;
  666. ___DSP_DUAL_16BIT_ALLOC(
  667. io_next_scb,
  668. io_sub_list_ptr
  669. )
  670. ___DSP_DUAL_16BIT_ALLOC(
  671. io_entry_point,
  672. io_this_spb
  673. )
  674. u32 istrm_rs_config;
  675. u32 istrm_buf_ptr;
  676. /* Init. 0000:8042: for ASER1
  677. 0000:8044: for ASER2 */
  678. ___DSP_DUAL_16BIT_ALLOC(
  679. io_stat_reg_addr,
  680. iofifo_pointer
  681. )
  682. /* Init 1 stero:100 ASER1
  683. Init 0 mono:110 ASER2
  684. */
  685. ___DSP_DUAL_16BIT_ALLOC(
  686. ififo_base_addr,
  687. ist_mo_format
  688. )
  689. u32 i_free;
  690. };
  691. /* SCB for the SP/DIF CODEC input and output */
  692. struct dsp_spdifiscb {
  693. ___DSP_DUAL_16BIT_ALLOC(
  694. status_ptr,
  695. status_start_ptr
  696. )
  697. u32 current_total;
  698. u32 previous_total;
  699. ___DSP_DUAL_16BIT_ALLOC(
  700. count,
  701. count_limit
  702. )
  703. u32 status_data;
  704. ___DSP_DUAL_16BIT_ALLOC(
  705. status,
  706. free4
  707. )
  708. u32 free3;
  709. ___DSP_DUAL_16BIT_ALLOC(
  710. free2,
  711. bit_count
  712. )
  713. u32 temp_status;
  714. ___DSP_DUAL_16BIT_ALLOC(
  715. next_SCB,
  716. sub_list_ptr
  717. )
  718. ___DSP_DUAL_16BIT_ALLOC(
  719. entry_point,
  720. this_spb
  721. )
  722. u32 strm_rs_config;
  723. u32 strm_buf_ptr;
  724. ___DSP_DUAL_16BIT_ALLOC(
  725. stat_reg_addr,
  726. fifo_pointer
  727. )
  728. ___DSP_DUAL_16BIT_ALLOC(
  729. fifo_base_addr,
  730. st_mo_format
  731. )
  732. u32 free1;
  733. };
  734. /* SCB for the SP/DIF CODEC input and output */
  735. struct dsp_spdifoscb {
  736. u32 free2;
  737. u32 free3[4];
  738. /* Need to be here for compatibility with AsynchFGTxCode */
  739. u32 strm_rs_config;
  740. u32 strm_buf_ptr;
  741. ___DSP_DUAL_16BIT_ALLOC(
  742. status,
  743. free5
  744. )
  745. u32 free4;
  746. ___DSP_DUAL_16BIT_ALLOC(
  747. next_scb,
  748. sub_list_ptr
  749. )
  750. ___DSP_DUAL_16BIT_ALLOC(
  751. entry_point,
  752. this_spb
  753. )
  754. u32 free6[2];
  755. ___DSP_DUAL_16BIT_ALLOC(
  756. stat_reg_addr,
  757. fifo_pointer
  758. )
  759. ___DSP_DUAL_16BIT_ALLOC(
  760. fifo_base_addr,
  761. st_mo_format
  762. )
  763. u32 free1;
  764. };
  765. struct dsp_asynch_fg_rx_scb {
  766. ___DSP_DUAL_16BIT_ALLOC(
  767. bot_buf_mask,
  768. buf_Mask
  769. )
  770. ___DSP_DUAL_16BIT_ALLOC(
  771. max,
  772. min
  773. )
  774. ___DSP_DUAL_16BIT_ALLOC(
  775. old_producer_pointer,
  776. hfg_scb_ptr
  777. )
  778. ___DSP_DUAL_16BIT_ALLOC(
  779. delta,
  780. adjust_count
  781. )
  782. u32 unused2[5];
  783. ___DSP_DUAL_16BIT_ALLOC(
  784. sibling_ptr,
  785. child_ptr
  786. )
  787. ___DSP_DUAL_16BIT_ALLOC(
  788. code_ptr,
  789. this_ptr
  790. )
  791. u32 strm_rs_config;
  792. u32 strm_buf_ptr;
  793. u32 unused_phi_incr;
  794. ___DSP_DUAL_16BIT_ALLOC(
  795. right_targ,
  796. left_targ
  797. )
  798. ___DSP_DUAL_16BIT_ALLOC(
  799. right_vol,
  800. left_vol
  801. )
  802. };
  803. struct dsp_asynch_fg_tx_scb {
  804. ___DSP_DUAL_16BIT_ALLOC(
  805. not_buf_mask,
  806. buf_mask
  807. )
  808. ___DSP_DUAL_16BIT_ALLOC(
  809. max,
  810. min
  811. )
  812. ___DSP_DUAL_16BIT_ALLOC(
  813. unused1,
  814. hfg_scb_ptr
  815. )
  816. ___DSP_DUAL_16BIT_ALLOC(
  817. delta,
  818. adjust_count
  819. )
  820. u32 accum_phi;
  821. ___DSP_DUAL_16BIT_ALLOC(
  822. unused2,
  823. const_one_third
  824. )
  825. u32 unused3[3];
  826. ___DSP_DUAL_16BIT_ALLOC(
  827. sibling_ptr,
  828. child_ptr
  829. )
  830. ___DSP_DUAL_16BIT_ALLOC(
  831. codePtr,
  832. this_ptr
  833. )
  834. u32 strm_rs_config;
  835. u32 strm_buf_ptr;
  836. u32 phi_incr;
  837. ___DSP_DUAL_16BIT_ALLOC(
  838. unused_right_targ,
  839. unused_left_targ
  840. )
  841. ___DSP_DUAL_16BIT_ALLOC(
  842. unused_right_vol,
  843. unused_left_vol
  844. )
  845. };
  846. struct dsp_output_snoop_scb {
  847. /* First 13 dwords from generic_scb_t */
  848. struct dsp_basic_dma_req basic_req; /* Optional */
  849. struct dsp_scatter_gather_ext sg_ext; /* Optional */
  850. ___DSP_DUAL_16BIT_ALLOC(
  851. next_scb, /* REQUIRED */
  852. sub_list_ptr /* REQUIRED */
  853. )
  854. ___DSP_DUAL_16BIT_ALLOC(
  855. entry_point, /* REQUIRED */
  856. this_spb /* REQUIRED */
  857. )
  858. u32 strm_rs_config; /* REQUIRED */
  859. u32 strm_buf_ptr; /* REQUIRED */
  860. ___DSP_DUAL_16BIT_ALLOC(
  861. init_snoop_input_link,
  862. snoop_child_input_scb
  863. )
  864. u32 snoop_input_buf_ptr;
  865. ___DSP_DUAL_16BIT_ALLOC(
  866. reserved,
  867. input_scb
  868. )
  869. };
  870. struct dsp_spio_write_scb {
  871. ___DSP_DUAL_16BIT_ALLOC(
  872. address1,
  873. address2
  874. )
  875. u32 data1;
  876. u32 data2;
  877. ___DSP_DUAL_16BIT_ALLOC(
  878. address3,
  879. address4
  880. )
  881. u32 data3;
  882. u32 data4;
  883. ___DSP_DUAL_16BIT_ALLOC(
  884. unused1,
  885. data_ptr
  886. )
  887. u32 unused2[2];
  888. ___DSP_DUAL_16BIT_ALLOC(
  889. sibling_ptr,
  890. child_ptr
  891. )
  892. ___DSP_DUAL_16BIT_ALLOC(
  893. entry_point,
  894. this_ptr
  895. )
  896. u32 unused3[5];
  897. };
  898. struct dsp_magic_snoop_task {
  899. u32 i0;
  900. u32 i1;
  901. u32 strm_buf_ptr1;
  902. u16 i2;
  903. u16 snoop_scb;
  904. u32 i3;
  905. u32 i4;
  906. u32 i5;
  907. u32 i6;
  908. u32 i7;
  909. ___DSP_DUAL_16BIT_ALLOC(
  910. next_scb,
  911. sub_list_ptr
  912. )
  913. ___DSP_DUAL_16BIT_ALLOC(
  914. entry_point,
  915. this_ptr
  916. )
  917. u32 strm_buf_config;
  918. u32 strm_buf_ptr2;
  919. u32 i8;
  920. struct dsp_volume_control vdec_vol_ctrl;
  921. };
  922. struct dsp_filter_scb {
  923. ___DSP_DUAL_16BIT_ALLOC(
  924. a0_right, /* 0x00 */
  925. a0_left
  926. )
  927. ___DSP_DUAL_16BIT_ALLOC(
  928. a1_right, /* 0x01 */
  929. a1_left
  930. )
  931. ___DSP_DUAL_16BIT_ALLOC(
  932. a2_right, /* 0x02 */
  933. a2_left
  934. )
  935. ___DSP_DUAL_16BIT_ALLOC(
  936. output_buf_ptr, /* 0x03 */
  937. init
  938. )
  939. ___DSP_DUAL_16BIT_ALLOC(
  940. filter_unused3, /* 0x04 */
  941. filter_unused2
  942. )
  943. u32 prev_sample_output1; /* 0x05 */
  944. u32 prev_sample_output2; /* 0x06 */
  945. u32 prev_sample_input1; /* 0x07 */
  946. u32 prev_sample_input2; /* 0x08 */
  947. ___DSP_DUAL_16BIT_ALLOC(
  948. next_scb_ptr, /* 0x09 */
  949. sub_list_ptr
  950. )
  951. ___DSP_DUAL_16BIT_ALLOC(
  952. entry_point, /* 0x0A */
  953. spb_ptr
  954. )
  955. u32 strm_rs_config; /* 0x0B */
  956. u32 strm_buf_ptr; /* 0x0C */
  957. ___DSP_DUAL_16BIT_ALLOC(
  958. b0_right, /* 0x0D */
  959. b0_left
  960. )
  961. ___DSP_DUAL_16BIT_ALLOC(
  962. b1_right, /* 0x0E */
  963. b1_left
  964. )
  965. ___DSP_DUAL_16BIT_ALLOC(
  966. b2_right, /* 0x0F */
  967. b2_left
  968. )
  969. };
  970. #endif /* __DSP_SCB_TYPES_H__ */