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/arch/mips/kernel/r6000_fpu.S

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
Assembly | 87 lines | 83 code | 4 blank | 0 comment | 3 complexity | cf9220bf4205cd0bba339eb863b414c1 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
 1/*
 2 * r6000_fpu.S: Save/restore floating point context for signal handlers.
 3 *
 4 * This file is subject to the terms and conditions of the GNU General Public
 5 * License.  See the file "COPYING" in the main directory of this archive
 6 * for more details.
 7 *
 8 * Copyright (C) 1996 by Ralf Baechle
 9 *
10 * Multi-arch abstraction and asm macros for easier reading:
11 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
12 */
13#include <asm/asm.h>
14#include <asm/fpregdef.h>
15#include <asm/mipsregs.h>
16#include <asm/asm-offsets.h>
17#include <asm/regdef.h>
18
19	.set	noreorder
20	.set	mips2
21	/* Save floating point context */
22	LEAF(_save_fp_context)
23	mfc0	t0,CP0_STATUS
24	sll	t0,t0,2
25	bgez	t0,1f
26	 nop
27
28	cfc1	t1,fcr31
29	/* Store the 16 double precision registers */
30	sdc1	$f0,(SC_FPREGS+0)(a0)
31	sdc1	$f2,(SC_FPREGS+16)(a0)
32	sdc1	$f4,(SC_FPREGS+32)(a0)
33	sdc1	$f6,(SC_FPREGS+48)(a0)
34	sdc1	$f8,(SC_FPREGS+64)(a0)
35	sdc1	$f10,(SC_FPREGS+80)(a0)
36	sdc1	$f12,(SC_FPREGS+96)(a0)
37	sdc1	$f14,(SC_FPREGS+112)(a0)
38	sdc1	$f16,(SC_FPREGS+128)(a0)
39	sdc1	$f18,(SC_FPREGS+144)(a0)
40	sdc1	$f20,(SC_FPREGS+160)(a0)
41	sdc1	$f22,(SC_FPREGS+176)(a0)
42	sdc1	$f24,(SC_FPREGS+192)(a0)
43	sdc1	$f26,(SC_FPREGS+208)(a0)
44	sdc1	$f28,(SC_FPREGS+224)(a0)
45	sdc1	$f30,(SC_FPREGS+240)(a0)
46	jr	ra
47	 sw	t0,SC_FPC_CSR(a0)
481:	jr	ra
49	 nop
50	END(_save_fp_context)
51
52/* Restore FPU state:
53 *  - fp gp registers
54 *  - cp1 status/control register
55 *
56 * We base the decision which registers to restore from the signal stack
57 * frame on the current content of c0_status, not on the content of the
58 * stack frame which might have been changed by the user.
59 */
60	LEAF(_restore_fp_context)
61	mfc0	t0,CP0_STATUS
62	sll	t0,t0,2
63
64	bgez	t0,1f
65	 lw	t0,SC_FPC_CSR(a0)
66	/* Restore the 16 double precision registers */
67	ldc1	$f0,(SC_FPREGS+0)(a0)
68	ldc1	$f2,(SC_FPREGS+16)(a0)
69	ldc1	$f4,(SC_FPREGS+32)(a0)
70	ldc1	$f6,(SC_FPREGS+48)(a0)
71	ldc1	$f8,(SC_FPREGS+64)(a0)
72	ldc1	$f10,(SC_FPREGS+80)(a0)
73	ldc1	$f12,(SC_FPREGS+96)(a0)
74	ldc1	$f14,(SC_FPREGS+112)(a0)
75	ldc1	$f16,(SC_FPREGS+128)(a0)
76	ldc1	$f18,(SC_FPREGS+144)(a0)
77	ldc1	$f20,(SC_FPREGS+160)(a0)
78	ldc1	$f22,(SC_FPREGS+176)(a0)
79	ldc1	$f24,(SC_FPREGS+192)(a0)
80	ldc1	$f26,(SC_FPREGS+208)(a0)
81	ldc1	$f28,(SC_FPREGS+224)(a0)
82	ldc1	$f30,(SC_FPREGS+240)(a0)
83	jr	ra
84	 ctc1	t0,fcr31
851:	jr	ra
86	 nop
87	END(_restore_fp_context)