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/arch/mips/include/asm/dma.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 315 lines | 175 code | 38 blank | 102 comment | 9 complexity | d39a8882a222bc44995e47dfd48106b3 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
  3 * Written by Hennus Bergman, 1992.
  4 * High DMA channel support & info by Hannu Savolainen
  5 * and John Boyd, Nov. 1992.
  6 *
  7 * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
  8 * and can only be used for expansion cards. Onboard DMA controllers, such
  9 * as the R4030 on Jazz boards behave totally different!
 10 */
 11
 12#ifndef _ASM_DMA_H
 13#define _ASM_DMA_H
 14
 15#include <asm/io.h>			/* need byte IO */
 16#include <linux/spinlock.h>		/* And spinlocks */
 17#include <linux/delay.h>
 18#include <asm/system.h>
 19
 20
 21#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
 22#define dma_outb	outb_p
 23#else
 24#define dma_outb	outb
 25#endif
 26
 27#define dma_inb		inb
 28
 29/*
 30 * NOTES about DMA transfers:
 31 *
 32 *  controller 1: channels 0-3, byte operations, ports 00-1F
 33 *  controller 2: channels 4-7, word operations, ports C0-DF
 34 *
 35 *  - ALL registers are 8 bits only, regardless of transfer size
 36 *  - channel 4 is not used - cascades 1 into 2.
 37 *  - channels 0-3 are byte - addresses/counts are for physical bytes
 38 *  - channels 5-7 are word - addresses/counts are for physical words
 39 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
 40 *  - transfer count loaded to registers is 1 less than actual count
 41 *  - controller 2 offsets are all even (2x offsets for controller 1)
 42 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
 43 *  - page registers for 0-3 use bit 0, represent 64K pages
 44 *
 45 * DMA transfers are limited to the lower 16MB of _physical_ memory.
 46 * Note that addresses loaded into registers must be _physical_ addresses,
 47 * not logical addresses (which may differ if paging is active).
 48 *
 49 *  Address mapping for channels 0-3:
 50 *
 51 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
 52 *    |  ...  |   |  ... |   |  ... |
 53 *    |  ...  |   |  ... |   |  ... |
 54 *    |  ...  |   |  ... |   |  ... |
 55 *   P7  ...  P0  A7 ... A0  A7 ... A0
 56 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
 57 *
 58 *  Address mapping for channels 5-7:
 59 *
 60 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
 61 *    |  ...  |   \   \   ... \  \  \  ... \  \
 62 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
 63 *    |  ...  |     \   \   ... \  \  \  ... \
 64 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
 65 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
 66 *
 67 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
 68 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
 69 * the hardware level, so odd-byte transfers aren't possible).
 70 *
 71 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
 72 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
 73 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
 74 *
 75 */
 76
 77#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
 78#define MAX_DMA_CHANNELS	8
 79#endif
 80
 81/*
 82 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
 83 * platform.  This describes only the PC style part of the DMA logic like on
 84 * Deskstations or Acer PICA but not the much more versatile DMA logic used
 85 * for the local devices on Acer PICA or Magnums.
 86 */
 87#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
 88/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
 89#define MAX_DMA_ADDRESS		PAGE_OFFSET
 90#else
 91#define MAX_DMA_ADDRESS		(PAGE_OFFSET + 0x01000000)
 92#endif
 93#define MAX_DMA_PFN		PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
 94#define MAX_DMA32_PFN		(1UL << (32 - PAGE_SHIFT))
 95
 96/* 8237 DMA controllers */
 97#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
 98#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
 99
100/* DMA controller registers */
101#define DMA1_CMD_REG		0x08	/* command register (w) */
102#define DMA1_STAT_REG		0x08	/* status register (r) */
103#define DMA1_REQ_REG            0x09    /* request register (w) */
104#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
105#define DMA1_MODE_REG		0x0B	/* mode register (w) */
106#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
107#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
108#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
109#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
110#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
111
112#define DMA2_CMD_REG		0xD0	/* command register (w) */
113#define DMA2_STAT_REG		0xD0	/* status register (r) */
114#define DMA2_REQ_REG            0xD2    /* request register (w) */
115#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
116#define DMA2_MODE_REG		0xD6	/* mode register (w) */
117#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
118#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
119#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
120#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
121#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
122
123#define DMA_ADDR_0              0x00    /* DMA address registers */
124#define DMA_ADDR_1              0x02
125#define DMA_ADDR_2              0x04
126#define DMA_ADDR_3              0x06
127#define DMA_ADDR_4              0xC0
128#define DMA_ADDR_5              0xC4
129#define DMA_ADDR_6              0xC8
130#define DMA_ADDR_7              0xCC
131
132#define DMA_CNT_0               0x01    /* DMA count registers */
133#define DMA_CNT_1               0x03
134#define DMA_CNT_2               0x05
135#define DMA_CNT_3               0x07
136#define DMA_CNT_4               0xC2
137#define DMA_CNT_5               0xC6
138#define DMA_CNT_6               0xCA
139#define DMA_CNT_7               0xCE
140
141#define DMA_PAGE_0              0x87    /* DMA page registers */
142#define DMA_PAGE_1              0x83
143#define DMA_PAGE_2              0x81
144#define DMA_PAGE_3              0x82
145#define DMA_PAGE_5              0x8B
146#define DMA_PAGE_6              0x89
147#define DMA_PAGE_7              0x8A
148
149#define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
150#define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
151#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
152
153#define DMA_AUTOINIT	0x10
154
155extern spinlock_t  dma_spin_lock;
156
157static __inline__ unsigned long claim_dma_lock(void)
158{
159	unsigned long flags;
160	spin_lock_irqsave(&dma_spin_lock, flags);
161	return flags;
162}
163
164static __inline__ void release_dma_lock(unsigned long flags)
165{
166	spin_unlock_irqrestore(&dma_spin_lock, flags);
167}
168
169/* enable/disable a specific DMA channel */
170static __inline__ void enable_dma(unsigned int dmanr)
171{
172	if (dmanr<=3)
173		dma_outb(dmanr,  DMA1_MASK_REG);
174	else
175		dma_outb(dmanr & 3,  DMA2_MASK_REG);
176}
177
178static __inline__ void disable_dma(unsigned int dmanr)
179{
180	if (dmanr<=3)
181		dma_outb(dmanr | 4,  DMA1_MASK_REG);
182	else
183		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
184}
185
186/* Clear the 'DMA Pointer Flip Flop'.
187 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
188 * Use this once to initialize the FF to a known state.
189 * After that, keep track of it. :-)
190 * --- In order to do that, the DMA routines below should ---
191 * --- only be used while holding the DMA lock ! ---
192 */
193static __inline__ void clear_dma_ff(unsigned int dmanr)
194{
195	if (dmanr<=3)
196		dma_outb(0,  DMA1_CLEAR_FF_REG);
197	else
198		dma_outb(0,  DMA2_CLEAR_FF_REG);
199}
200
201/* set mode (above) for a specific DMA channel */
202static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
203{
204	if (dmanr<=3)
205		dma_outb(mode | dmanr,  DMA1_MODE_REG);
206	else
207		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
208}
209
210/* Set only the page register bits of the transfer address.
211 * This is used for successive transfers when we know the contents of
212 * the lower 16 bits of the DMA current address register, but a 64k boundary
213 * may have been crossed.
214 */
215static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
216{
217	switch(dmanr) {
218		case 0:
219			dma_outb(pagenr, DMA_PAGE_0);
220			break;
221		case 1:
222			dma_outb(pagenr, DMA_PAGE_1);
223			break;
224		case 2:
225			dma_outb(pagenr, DMA_PAGE_2);
226			break;
227		case 3:
228			dma_outb(pagenr, DMA_PAGE_3);
229			break;
230		case 5:
231			dma_outb(pagenr & 0xfe, DMA_PAGE_5);
232			break;
233		case 6:
234			dma_outb(pagenr & 0xfe, DMA_PAGE_6);
235			break;
236		case 7:
237			dma_outb(pagenr & 0xfe, DMA_PAGE_7);
238			break;
239	}
240}
241
242
243/* Set transfer address & page bits for specific DMA channel.
244 * Assumes dma flipflop is clear.
245 */
246static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
247{
248	set_dma_page(dmanr, a>>16);
249	if (dmanr <= 3)  {
250	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
251            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
252	}  else  {
253	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
254	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
255	}
256}
257
258
259/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
260 * a specific DMA channel.
261 * You must ensure the parameters are valid.
262 * NOTE: from a manual: "the number of transfers is one more
263 * than the initial word count"! This is taken into account.
264 * Assumes dma flip-flop is clear.
265 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
266 */
267static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
268{
269        count--;
270	if (dmanr <= 3)  {
271	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
272	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
273        } else {
274	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
275	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
276        }
277}
278
279
280/* Get DMA residue count. After a DMA transfer, this
281 * should return zero. Reading this while a DMA transfer is
282 * still in progress will return unpredictable results.
283 * If called before the channel has been used, it may return 1.
284 * Otherwise, it returns the number of _bytes_ left to transfer.
285 *
286 * Assumes DMA flip-flop is clear.
287 */
288static __inline__ int get_dma_residue(unsigned int dmanr)
289{
290	unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
291					 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
292
293	/* using short to get 16-bit wrap around */
294	unsigned short count;
295
296	count = 1 + dma_inb(io_port);
297	count += dma_inb(io_port) << 8;
298
299	return (dmanr<=3)? count : (count<<1);
300}
301
302
303/* These are in kernel/dma.c: */
304extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */
305extern void free_dma(unsigned int dmanr);	/* release it again */
306
307/* From PCI */
308
309#ifdef CONFIG_PCI
310extern int isa_dma_bridge_buggy;
311#else
312#define isa_dma_bridge_buggy	(0)
313#endif
314
315#endif /* _ASM_DMA_H */