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/arch/mips/rb532/irq.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 236 lines | 166 code | 39 blank | 31 comment | 18 complexity | 007c5df61085df74a3f0594d891a56e4 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 *  This program is free software; you can redistribute  it and/or modify it
  3 *  under  the terms of  the GNU General  Public License as published by the
  4 *  Free Software Foundation;  either version 2 of the  License, or (at your
  5 *  option) any later version.
  6 *
  7 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  8 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  9 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 10 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 11 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 12 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 13 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 14 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 15 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 16 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 17 *
 18 *  You should have received a copy of the  GNU General Public License along
 19 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 20 *  675 Mass Ave, Cambridge, MA 02139, USA.
 21 *
 22 * Copyright 2002 MontaVista Software Inc.
 23 * Author: MontaVista Software, Inc.
 24 *              stevel@mvista.com or source@mvista.com
 25 */
 26
 27#include <linux/bitops.h>
 28#include <linux/errno.h>
 29#include <linux/init.h>
 30#include <linux/io.h>
 31#include <linux/kernel_stat.h>
 32#include <linux/module.h>
 33#include <linux/signal.h>
 34#include <linux/sched.h>
 35#include <linux/types.h>
 36#include <linux/interrupt.h>
 37#include <linux/ioport.h>
 38#include <linux/timex.h>
 39#include <linux/random.h>
 40#include <linux/delay.h>
 41
 42#include <asm/bootinfo.h>
 43#include <asm/time.h>
 44#include <asm/mipsregs.h>
 45#include <asm/system.h>
 46
 47#include <asm/mach-rc32434/irq.h>
 48#include <asm/mach-rc32434/gpio.h>
 49
 50struct intr_group {
 51	u32 mask;	/* mask of valid bits in pending/mask registers */
 52	volatile u32 *base_addr;
 53};
 54
 55#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
 56
 57#if (NR_IRQS < RC32434_NR_IRQS)
 58#error Too little irqs defined. Did you override <asm/irq.h> ?
 59#endif
 60
 61static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
 62	{
 63		.mask	= 0x0000efff,
 64		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
 65	{
 66		.mask	= 0x00001fff,
 67		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
 68	{
 69		.mask	= 0x00000007,
 70		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
 71	{
 72		.mask	= 0x0003ffff,
 73		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
 74	{
 75		.mask	= 0xffffffff,
 76		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
 77};
 78
 79#define READ_PEND(base) (*(base))
 80#define READ_MASK(base) (*(base + 2))
 81#define WRITE_MASK(base, val) (*(base + 2) = (val))
 82
 83static inline int irq_to_group(unsigned int irq_nr)
 84{
 85	return (irq_nr - GROUP0_IRQ_BASE) >> 5;
 86}
 87
 88static inline int group_to_ip(unsigned int group)
 89{
 90	return group + 2;
 91}
 92
 93static inline void enable_local_irq(unsigned int ip)
 94{
 95	int ipnum = 0x100 << ip;
 96
 97	set_c0_status(ipnum);
 98}
 99
100static inline void disable_local_irq(unsigned int ip)
101{
102	int ipnum = 0x100 << ip;
103
104	clear_c0_status(ipnum);
105}
106
107static inline void ack_local_irq(unsigned int ip)
108{
109	int ipnum = 0x100 << ip;
110
111	clear_c0_cause(ipnum);
112}
113
114static void rb532_enable_irq(unsigned int irq_nr)
115{
116	int ip = irq_nr - GROUP0_IRQ_BASE;
117	unsigned int group, intr_bit;
118	volatile unsigned int *addr;
119
120	if (ip < 0)
121		enable_local_irq(irq_nr);
122	else {
123		group = ip >> 5;
124
125		ip &= (1 << 5) - 1;
126		intr_bit = 1 << ip;
127
128		enable_local_irq(group_to_ip(group));
129
130		addr = intr_group[group].base_addr;
131		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
132	}
133}
134
135static void rb532_disable_irq(unsigned int irq_nr)
136{
137	int ip = irq_nr - GROUP0_IRQ_BASE;
138	unsigned int group, intr_bit, mask;
139	volatile unsigned int *addr;
140
141	if (ip < 0) {
142		disable_local_irq(irq_nr);
143	} else {
144		group = ip >> 5;
145
146		ip &= (1 << 5) - 1;
147		intr_bit = 1 << ip;
148		addr = intr_group[group].base_addr;
149		mask = READ_MASK(addr);
150		mask |= intr_bit;
151		WRITE_MASK(addr, mask);
152
153		/* There is a maximum of 14 GPIO interrupts */
154		if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
155			rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
156
157		/*
158		 * if there are no more interrupts enabled in this
159		 * group, disable corresponding IP
160		 */
161		if (mask == intr_group[group].mask)
162			disable_local_irq(group_to_ip(group));
163	}
164}
165
166static void rb532_mask_and_ack_irq(unsigned int irq_nr)
167{
168	rb532_disable_irq(irq_nr);
169	ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
170}
171
172static int rb532_set_type(unsigned int irq_nr, unsigned type)
173{
174	int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE;
175	int group = irq_to_group(irq_nr);
176
177	if (group != GPIO_MAPPED_IRQ_GROUP || irq_nr > (GROUP4_IRQ_BASE + 13))
178		return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
179
180	switch (type) {
181	case IRQ_TYPE_LEVEL_HIGH:
182		rb532_gpio_set_ilevel(1, gpio);
183		break;
184	case IRQ_TYPE_LEVEL_LOW:
185		rb532_gpio_set_ilevel(0, gpio);
186		break;
187	default:
188		return -EINVAL;
189	}
190
191	return 0;
192}
193
194static struct irq_chip rc32434_irq_type = {
195	.name		= "RB532",
196	.ack		= rb532_disable_irq,
197	.mask		= rb532_disable_irq,
198	.mask_ack	= rb532_mask_and_ack_irq,
199	.unmask		= rb532_enable_irq,
200	.set_type	= rb532_set_type,
201};
202
203void __init arch_init_irq(void)
204{
205	int i;
206
207	pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
208
209	for (i = 0; i < RC32434_NR_IRQS; i++)
210		set_irq_chip_and_handler(i,  &rc32434_irq_type,
211					handle_level_irq);
212}
213
214/* Main Interrupt dispatcher */
215asmlinkage void plat_irq_dispatch(void)
216{
217	unsigned int ip, pend, group;
218	volatile unsigned int *addr;
219	unsigned int cp0_cause = read_c0_cause() & read_c0_status();
220
221	if (cp0_cause & CAUSEF_IP7) {
222		do_IRQ(7);
223	} else {
224		ip = (cp0_cause & 0x7c00);
225		if (ip) {
226			group = 21 + (fls(ip) - 32);
227
228			addr = intr_group[group].base_addr;
229
230			pend = READ_PEND(addr);
231			pend &= ~READ_MASK(addr);	/* only unmasked interrupts */
232			pend = 39 + (fls(pend) - 32);
233			do_IRQ((group << 5) + pend);
234		}
235	}
236}