/arch/mips/txx9/rbtx4938/irq.c

  1/*
  2 * Toshiba RBTX4938 specific interrupt handlers
  3 * Copyright (C) 2000-2001 Toshiba Corporation
  4 *
  5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  6 * terms of the GNU General Public License version 2. This program is
  7 * licensed "as is" without any warranty of any kind, whether express
  8 * or implied.
  9 *
 10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
 11 */
 12
 13/*
 14 * MIPS_CPU_IRQ_BASE+00 Software 0
 15 * MIPS_CPU_IRQ_BASE+01 Software 1
 16 * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
 17 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
 18 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
 19 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
 20 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
 21 * MIPS_CPU_IRQ_BASE+07 CPU TIMER
 22 *
 23 * TXX9_IRQ_BASE+00
 24 * TXX9_IRQ_BASE+01
 25 * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
 26 * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
 27 * TXX9_IRQ_BASE+04
 28 * TXX9_IRQ_BASE+05 TX4938 ETH1
 29 * TXX9_IRQ_BASE+06 TX4938 ETH0
 30 * TXX9_IRQ_BASE+07
 31 * TXX9_IRQ_BASE+08 TX4938 SIO 0
 32 * TXX9_IRQ_BASE+09 TX4938 SIO 1
 33 * TXX9_IRQ_BASE+10 TX4938 DMA0
 34 * TXX9_IRQ_BASE+11 TX4938 DMA1
 35 * TXX9_IRQ_BASE+12 TX4938 DMA2
 36 * TXX9_IRQ_BASE+13 TX4938 DMA3
 37 * TXX9_IRQ_BASE+14
 38 * TXX9_IRQ_BASE+15
 39 * TXX9_IRQ_BASE+16 TX4938 PCIC
 40 * TXX9_IRQ_BASE+17 TX4938 TMR0
 41 * TXX9_IRQ_BASE+18 TX4938 TMR1
 42 * TXX9_IRQ_BASE+19 TX4938 TMR2
 43 * TXX9_IRQ_BASE+20
 44 * TXX9_IRQ_BASE+21
 45 * TXX9_IRQ_BASE+22 TX4938 PCIERR
 46 * TXX9_IRQ_BASE+23
 47 * TXX9_IRQ_BASE+24
 48 * TXX9_IRQ_BASE+25
 49 * TXX9_IRQ_BASE+26
 50 * TXX9_IRQ_BASE+27
 51 * TXX9_IRQ_BASE+28
 52 * TXX9_IRQ_BASE+29
 53 * TXX9_IRQ_BASE+30
 54 * TXX9_IRQ_BASE+31 TX4938 SPI
 55 *
 56 * RBTX4938_IRQ_IOC+00 PCI-D
 57 * RBTX4938_IRQ_IOC+01 PCI-C
 58 * RBTX4938_IRQ_IOC+02 PCI-B
 59 * RBTX4938_IRQ_IOC+03 PCI-A
 60 * RBTX4938_IRQ_IOC+04 RTC
 61 * RBTX4938_IRQ_IOC+05 ATA
 62 * RBTX4938_IRQ_IOC+06 MODEM
 63 * RBTX4938_IRQ_IOC+07 SWINT
 64 */
 65#include <linux/init.h>
 66#include <linux/interrupt.h>
 67#include <asm/mipsregs.h>
 68#include <asm/txx9/generic.h>
 69#include <asm/txx9/rbtx4938.h>
 70
 71static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
 72static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
 73
 74#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
 75static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
 76	.name = TOSHIBA_RBTX4938_IOC_NAME,
 77	.ack = toshiba_rbtx4938_irq_ioc_disable,
 78	.mask = toshiba_rbtx4938_irq_ioc_disable,
 79	.mask_ack = toshiba_rbtx4938_irq_ioc_disable,
 80	.unmask = toshiba_rbtx4938_irq_ioc_enable,
 81};
 82
 83static int toshiba_rbtx4938_irq_nested(int sw_irq)
 84{
 85	u8 level3;
 86
 87	level3 = readb(rbtx4938_imstat_addr);
 88	if (unlikely(!level3))
 89		return -1;
 90	/* must use fls so onboard ATA has priority */
 91	return RBTX4938_IRQ_IOC + __fls8(level3);
 92}
 93
 94static void __init
 95toshiba_rbtx4938_irq_ioc_init(void)
 96{
 97	int i;
 98
 99	for (i = RBTX4938_IRQ_IOC;
100	     i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
101		set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
102					 handle_level_irq);
103
104	set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
105}
106
107static void
108toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
109{
110	unsigned char v;
111
112	v = readb(rbtx4938_imask_addr);
113	v |= (1 << (irq - RBTX4938_IRQ_IOC));
114	writeb(v, rbtx4938_imask_addr);
115	mmiowb();
116}
117
118static void
119toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
120{
121	unsigned char v;
122
123	v = readb(rbtx4938_imask_addr);
124	v &= ~(1 << (irq - RBTX4938_IRQ_IOC));
125	writeb(v, rbtx4938_imask_addr);
126	mmiowb();
127}
128
129static int rbtx4938_irq_dispatch(int pending)
130{
131	int irq;
132
133	if (pending & STATUSF_IP7)
134		irq = MIPS_CPU_IRQ_BASE + 7;
135	else if (pending & STATUSF_IP2) {
136		irq = txx9_irq();
137		if (irq == RBTX4938_IRQ_IOCINT)
138			irq = toshiba_rbtx4938_irq_nested(irq);
139	} else if (pending & STATUSF_IP1)
140		irq = MIPS_CPU_IRQ_BASE + 0;
141	else if (pending & STATUSF_IP0)
142		irq = MIPS_CPU_IRQ_BASE + 1;
143	else
144		irq = -1;
145	return irq;
146}
147
148void __init rbtx4938_irq_setup(void)
149{
150	txx9_irq_dispatch = rbtx4938_irq_dispatch;
151	/* Now, interrupt control disabled, */
152	/* all IRC interrupts are masked, */
153	/* all IRC interrupt mode are Low Active. */
154
155	/* mask all IOC interrupts */
156	writeb(0, rbtx4938_imask_addr);
157
158	/* clear SoftInt interrupts */
159	writeb(0, rbtx4938_softint_addr);
160	tx4938_irq_init();
161	toshiba_rbtx4938_irq_ioc_init();
162	/* Onboard 10M Ether: High Active */
163	set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
164}