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/arch/mips/loongson/common/cs5536/cs5536_acc.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 140 lines | 119 code | 6 blank | 15 comment | 19 complexity | 298ed803727ca3ed0148de38b33b01c5 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * the ACC Virtual Support Module of AMD CS5536
  3 *
  4 * Copyright (C) 2007 Lemote, Inc.
  5 * Author : jlliu, liujl@lemote.com
  6 *
  7 * Copyright (C) 2009 Lemote, Inc.
  8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
  9 *
 10 * This program is free software; you can redistribute  it and/or modify it
 11 * under  the terms of  the GNU General  Public License as published by the
 12 * Free Software Foundation;  either version 2 of the  License, or (at your
 13 * option) any later version.
 14 */
 15
 16#include <cs5536/cs5536.h>
 17#include <cs5536/cs5536_pci.h>
 18
 19void pci_acc_write_reg(int reg, u32 value)
 20{
 21	u32 hi = 0, lo = value;
 22
 23	switch (reg) {
 24	case PCI_COMMAND:
 25		_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
 26		if (value & PCI_COMMAND_MASTER)
 27			lo |= (0x03 << 8);
 28		else
 29			lo &= ~(0x03 << 8);
 30		_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
 31		break;
 32	case PCI_STATUS:
 33		if (value & PCI_STATUS_PARITY) {
 34			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
 35			if (lo & SB_PARE_ERR_FLAG) {
 36				lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
 37				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
 38			}
 39		}
 40		break;
 41	case PCI_BAR0_REG:
 42		if (value == PCI_BAR_RANGE_MASK) {
 43			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
 44			lo |= SOFT_BAR_ACC_FLAG;
 45			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
 46		} else if (value & 0x01) {
 47			value &= 0xfffffffc;
 48			hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
 49			lo = 0x000fff80 | ((value & 0x00000fff) << 20);
 50			_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
 51		}
 52		break;
 53	case PCI_ACC_INT_REG:
 54		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
 55		/* disable all the usb interrupt in PIC */
 56		lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
 57		if (value)	/* enable all the acc interrupt in PIC */
 58			lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
 59		_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
 60		break;
 61	default:
 62		break;
 63	}
 64}
 65
 66u32 pci_acc_read_reg(int reg)
 67{
 68	u32 hi, lo;
 69	u32 conf_data = 0;
 70
 71	switch (reg) {
 72	case PCI_VENDOR_ID:
 73		conf_data =
 74		    CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
 75		break;
 76	case PCI_COMMAND:
 77		_rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
 78		if (((lo & 0xfff00000) || (hi & 0x000000ff))
 79		    && ((hi & 0xf0000000) == 0xa0000000))
 80			conf_data |= PCI_COMMAND_IO;
 81		_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
 82		if ((lo & 0x300) == 0x300)
 83			conf_data |= PCI_COMMAND_MASTER;
 84		break;
 85	case PCI_STATUS:
 86		conf_data |= PCI_STATUS_66MHZ;
 87		conf_data |= PCI_STATUS_FAST_BACK;
 88		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
 89		if (lo & SB_PARE_ERR_FLAG)
 90			conf_data |= PCI_STATUS_PARITY;
 91		conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
 92		break;
 93	case PCI_CLASS_REVISION:
 94		_rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
 95		conf_data = lo & 0x000000ff;
 96		conf_data |= (CS5536_ACC_CLASS_CODE << 8);
 97		break;
 98	case PCI_CACHE_LINE_SIZE:
 99		conf_data =
100		    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101					    PCI_NORMAL_LATENCY_TIMER);
102		break;
103	case PCI_BAR0_REG:
104		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105		if (lo & SOFT_BAR_ACC_FLAG) {
106			conf_data = CS5536_ACC_RANGE |
107			    PCI_BASE_ADDRESS_SPACE_IO;
108			lo &= ~SOFT_BAR_ACC_FLAG;
109			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110		} else {
111			_rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112			conf_data = (hi & 0x000000ff) << 12;
113			conf_data |= (lo & 0xfff00000) >> 20;
114			conf_data |= 0x01;
115			conf_data &= ~0x02;
116		}
117		break;
118	case PCI_CARDBUS_CIS:
119		conf_data = PCI_CARDBUS_CIS_POINTER;
120		break;
121	case PCI_SUBSYSTEM_VENDOR_ID:
122		conf_data =
123		    CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124		break;
125	case PCI_ROM_ADDRESS:
126		conf_data = PCI_EXPANSION_ROM_BAR;
127		break;
128	case PCI_CAPABILITY_LIST:
129		conf_data = PCI_CAPLIST_USB_POINTER;
130		break;
131	case PCI_INTERRUPT_LINE:
132		conf_data =
133		    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134		break;
135	default:
136		break;
137	}
138
139	return conf_data;
140}