/arch/mips/loongson/fuloong-2e/irq.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35 · C · 71 lines · 43 code · 10 blank · 18 comment · 8 complexity · 749b1b7e0927bf1f33e09d799d79929e MD5 · raw file 

    

  1. /*
    2. 

  2.  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
    3. 

  3.  * Author: Fuxin Zhang, zhangfx@lemote.com
    4. 

  4.  *
    5. 

  5.  *  This program is free software; you can redistribute  it and/or modify it
    6. 

  6.  *  under  the terms of  the GNU General  Public License as published by the
    7. 

  7.  *  Free Software Foundation;  either version 2 of the  License, or (at your
    8. 

  8.  *  option) any later version.
    9. 

  9.  */
    10. 

  10. #include <linux/interrupt.h>
    11. 

  11. 

  12. #include <asm/irq_cpu.h>
    13. 

  13. #include <asm/i8259.h>
    14. 

  14. 

  15. #include <loongson.h>
    16. 

  16. 

  17. static void i8259_irqdispatch(void)
    18. 

  18. {
    19. 

  19. 	int irq;
    20. 

  20. 

  21. 	irq = i8259_irq();
    22. 

  22. 	if (irq >= 0)
    23. 

  23. 		do_IRQ(irq);
    24. 

  24. 	else
    25. 

  25. 		spurious_interrupt();
    26. 

  26. }
    27. 

  27. 

  28. asmlinkage void mach_irq_dispatch(unsigned int pending)
    29. 

  29. {
    30. 

  30. 	if (pending & CAUSEF_IP7)
    31. 

  31. 		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
    32. 

  32. 	else if (pending & CAUSEF_IP6) /* perf counter loverflow */
    33. 

  33. 		do_IRQ(LOONGSON2_PERFCNT_IRQ);
    34. 

  34. 	else if (pending & CAUSEF_IP5)
    35. 

  35. 		i8259_irqdispatch();
    36. 

  36. 	else if (pending & CAUSEF_IP2)
    37. 

  37. 		bonito_irqdispatch();
    38. 

  38. 	else
    39. 

  39. 		spurious_interrupt();
    40. 

  40. }
    41. 

  41. 

  42. static struct irqaction cascade_irqaction = {
    43. 

  43. 	.handler = no_action,
    44. 

  44. 	.name = "cascade",
    45. 

  45. };
    46. 

  46. 

  47. void __init set_irq_trigger_mode(void)
    48. 

  48. {
    49. 

  49. 	/* most bonito irq should be level triggered */
    50. 

  50. 	LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
    51. 

  51. 	    LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
    52. 

  52. }
    53. 

  53. 

  54. void __init mach_init_irq(void)
    55. 

  55. {
    56. 

  56. 	/* init all controller
    57. 

  57. 	 *   0-15         ------> i8259 interrupt
    58. 

  58. 	 *   16-23        ------> mips cpu interrupt
    59. 

  59. 	 *   32-63        ------> bonito irq
    60. 

  60. 	 */
    61. 

  61. 

  62. 	/* Sets the first-level interrupt dispatcher. */
    63. 

  63. 	mips_cpu_irq_init();
    64. 

  64. 	init_i8259_irqs();
    65. 

  65. 	bonito_irq_init();
    66. 

  66. 

  67. 	/* bonito irq at IP2 */
    68. 

  68. 	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
    69. 

  69. 	/* 8259 irq at IP5 */
    70. 

  70. 	setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
    71. 

  71. }
    72.