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/arch/mips/mti-malta/malta-setup.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 224 lines | 169 code | 25 blank | 30 comment | 16 complexity | a6b7e3a25e7eaa2e35019f5c8a267642 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * Carsten Langgaard, carstenl@mips.com
  3 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  4 * Copyright (C) 2008 Dmitri Vorobiev
  5 *
  6 *  This program is free software; you can distribute it and/or modify it
  7 *  under the terms of the GNU General Public License (Version 2) as
  8 *  published by the Free Software Foundation.
  9 *
 10 *  This program is distributed in the hope it will be useful, but WITHOUT
 11 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13 *  for more details.
 14 *
 15 *  You should have received a copy of the GNU General Public License along
 16 *  with this program; if not, write to the Free Software Foundation, Inc.,
 17 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 18 */
 19#include <linux/cpu.h>
 20#include <linux/init.h>
 21#include <linux/sched.h>
 22#include <linux/ioport.h>
 23#include <linux/irq.h>
 24#include <linux/pci.h>
 25#include <linux/screen_info.h>
 26#include <linux/time.h>
 27
 28#include <asm/bootinfo.h>
 29#include <asm/mips-boards/generic.h>
 30#include <asm/mips-boards/prom.h>
 31#include <asm/mips-boards/malta.h>
 32#include <asm/mips-boards/maltaint.h>
 33#include <asm/dma.h>
 34#include <asm/traps.h>
 35#ifdef CONFIG_VT
 36#include <linux/console.h>
 37#endif
 38
 39extern void malta_be_init(void);
 40extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
 41
 42static struct resource standard_io_resources[] = {
 43	{
 44		.name = "dma1",
 45		.start = 0x00,
 46		.end = 0x1f,
 47		.flags = IORESOURCE_BUSY
 48	},
 49	{
 50		.name = "timer",
 51		.start = 0x40,
 52		.end = 0x5f,
 53		.flags = IORESOURCE_BUSY
 54	},
 55	{
 56		.name = "keyboard",
 57		.start = 0x60,
 58		.end = 0x6f,
 59		.flags = IORESOURCE_BUSY
 60	},
 61	{
 62		.name = "dma page reg",
 63		.start = 0x80,
 64		.end = 0x8f,
 65		.flags = IORESOURCE_BUSY
 66	},
 67	{
 68		.name = "dma2",
 69		.start = 0xc0,
 70		.end = 0xdf,
 71		.flags = IORESOURCE_BUSY
 72	},
 73};
 74
 75const char *get_system_type(void)
 76{
 77	return "MIPS Malta";
 78}
 79
 80#if defined(CONFIG_MIPS_MT_SMTC)
 81const char display_string[] = "       SMTC LINUX ON MALTA       ";
 82#else
 83const char display_string[] = "        LINUX ON MALTA       ";
 84#endif /* CONFIG_MIPS_MT_SMTC */
 85
 86#ifdef CONFIG_BLK_DEV_FD
 87static void __init fd_activate(void)
 88{
 89	/*
 90	 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
 91	 * Controller.
 92	 * Done by YAMON 2.00 onwards
 93	 */
 94	/* Entering config state. */
 95	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
 96
 97	/* Activate floppy controller. */
 98	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
 99	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
100	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
101	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
102
103	/* Exit config state. */
104	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
105}
106#endif
107
108#ifdef CONFIG_BLK_DEV_IDE
109static void __init pci_clock_check(void)
110{
111	unsigned int __iomem *jmpr_p =
112		(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
113	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
114	static const int pciclocks[] __initdata = {
115		33, 20, 25, 30, 12, 16, 37, 10
116	};
117	int pciclock = pciclocks[jmpr];
118	char *argptr = prom_getcmdline();
119
120	if (pciclock != 33 && !strstr(argptr, "idebus=")) {
121		printk(KERN_WARNING "WARNING: PCI clock is %dMHz, "
122				"setting idebus\n", pciclock);
123		argptr += strlen(argptr);
124		sprintf(argptr, " idebus=%d", pciclock);
125		if (pciclock < 20 || pciclock > 66)
126			printk(KERN_WARNING "WARNING: IDE timing "
127					"calculations will be incorrect\n");
128	}
129}
130#endif
131
132#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
133static void __init screen_info_setup(void)
134{
135	screen_info = (struct screen_info) {
136		.orig_x = 0,
137		.orig_y = 25,
138		.ext_mem_k = 0,
139		.orig_video_page = 0,
140		.orig_video_mode = 0,
141		.orig_video_cols = 80,
142		.unused2 = 0,
143		.orig_video_ega_bx = 0,
144		.unused3 = 0,
145		.orig_video_lines = 25,
146		.orig_video_isVGA = VIDEO_TYPE_VGAC,
147		.orig_video_points = 16
148	};
149}
150#endif
151
152static void __init bonito_quirks_setup(void)
153{
154	char *argptr;
155
156	argptr = prom_getcmdline();
157	if (strstr(argptr, "debug")) {
158		BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
159		printk(KERN_INFO "Enabled Bonito debug mode\n");
160	} else
161		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
162
163#ifdef CONFIG_DMA_COHERENT
164	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
165		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
166		printk(KERN_INFO "Enabled Bonito CPU coherency\n");
167
168		argptr = prom_getcmdline();
169		if (strstr(argptr, "iobcuncached")) {
170			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
171			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
172				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
173					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
174			printk(KERN_INFO "Disabled Bonito IOBC coherency\n");
175		} else {
176			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
177			BONITO_PCIMEMBASECFG |=
178				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
179					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
180			printk(KERN_INFO "Enabled Bonito IOBC coherency\n");
181		}
182	} else
183		panic("Hardware DMA cache coherency not supported");
184#endif
185}
186
187void __init plat_mem_setup(void)
188{
189	unsigned int i;
190
191	mips_pcibios_init();
192
193	/* Request I/O space for devices used on the Malta board. */
194	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
195		request_resource(&ioport_resource, standard_io_resources+i);
196
197	/*
198	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
199	 */
200	enable_dma(4);
201
202#ifdef CONFIG_DMA_COHERENT
203	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
204		panic("Hardware DMA cache coherency not supported");
205#endif
206
207	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
208		bonito_quirks_setup();
209
210#ifdef CONFIG_BLK_DEV_IDE
211	pci_clock_check();
212#endif
213
214#ifdef CONFIG_BLK_DEV_FD
215	fd_activate();
216#endif
217
218#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
219	screen_info_setup();
220#endif
221
222	board_be_init = malta_be_init;
223	board_be_handler = malta_be_handler;
224}