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/arch/ia64/kernel/gate.S

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
Assembly | 385 lines | 324 code | 15 blank | 46 comment | 6 complexity | 78aea324749704f8006435f6c0535e1f MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * This file contains the code that gets mapped at the upper end of each task's text
  3 * region.  For now, it contains the signal trampoline code only.
  4 *
  5 * Copyright (C) 1999-2003 Hewlett-Packard Co
  6 * 	David Mosberger-Tang <davidm@hpl.hp.com>
  7 */
  8
  9
 10#include <asm/asmmacro.h>
 11#include <asm/errno.h>
 12#include <asm/asm-offsets.h>
 13#include <asm/sigcontext.h>
 14#include <asm/system.h>
 15#include <asm/unistd.h>
 16#include "paravirt_inst.h"
 17
 18/*
 19 * We can't easily refer to symbols inside the kernel.  To avoid full runtime relocation,
 20 * complications with the linker (which likes to create PLT stubs for branches
 21 * to targets outside the shared object) and to avoid multi-phase kernel builds, we
 22 * simply create minimalistic "patch lists" in special ELF sections.
 23 */
 24	.section ".data..patch.fsyscall_table", "a"
 25	.previous
 26#define LOAD_FSYSCALL_TABLE(reg)			\
 27[1:]	movl reg=0;					\
 28	.xdata4 ".data..patch.fsyscall_table", 1b-.
 29
 30	.section ".data..patch.brl_fsys_bubble_down", "a"
 31	.previous
 32#define BRL_COND_FSYS_BUBBLE_DOWN(pr)			\
 33[1:](pr)brl.cond.sptk 0;				\
 34	;;						\
 35	.xdata4 ".data..patch.brl_fsys_bubble_down", 1b-.
 36
 37GLOBAL_ENTRY(__kernel_syscall_via_break)
 38	.prologue
 39	.altrp b6
 40	.body
 41	/*
 42	 * Note: for (fast) syscall restart to work, the break instruction must be
 43	 *	 the first one in the bundle addressed by syscall_via_break.
 44	 */
 45{ .mib
 46	break 0x100000
 47	nop.i 0
 48	br.ret.sptk.many b6
 49}
 50END(__kernel_syscall_via_break)
 51
 52#	define ARG0_OFF		(16 + IA64_SIGFRAME_ARG0_OFFSET)
 53#	define ARG1_OFF		(16 + IA64_SIGFRAME_ARG1_OFFSET)
 54#	define ARG2_OFF		(16 + IA64_SIGFRAME_ARG2_OFFSET)
 55#	define SIGHANDLER_OFF	(16 + IA64_SIGFRAME_HANDLER_OFFSET)
 56#	define SIGCONTEXT_OFF	(16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET)
 57
 58#	define FLAGS_OFF	IA64_SIGCONTEXT_FLAGS_OFFSET
 59#	define CFM_OFF		IA64_SIGCONTEXT_CFM_OFFSET
 60#	define FR6_OFF		IA64_SIGCONTEXT_FR6_OFFSET
 61#	define BSP_OFF		IA64_SIGCONTEXT_AR_BSP_OFFSET
 62#	define RNAT_OFF		IA64_SIGCONTEXT_AR_RNAT_OFFSET
 63#	define UNAT_OFF		IA64_SIGCONTEXT_AR_UNAT_OFFSET
 64#	define FPSR_OFF		IA64_SIGCONTEXT_AR_FPSR_OFFSET
 65#	define PR_OFF		IA64_SIGCONTEXT_PR_OFFSET
 66#	define RP_OFF		IA64_SIGCONTEXT_IP_OFFSET
 67#	define SP_OFF		IA64_SIGCONTEXT_R12_OFFSET
 68#	define RBS_BASE_OFF	IA64_SIGCONTEXT_RBS_BASE_OFFSET
 69#	define LOADRS_OFF	IA64_SIGCONTEXT_LOADRS_OFFSET
 70#	define base0		r2
 71#	define base1		r3
 72	/*
 73	 * When we get here, the memory stack looks like this:
 74	 *
 75	 *   +===============================+
 76       	 *   |				     |
 77       	 *   //	    struct sigframe          //
 78       	 *   |				     |
 79	 *   +-------------------------------+ <-- sp+16
 80	 *   |      16 byte of scratch       |
 81	 *   |            space              |
 82	 *   +-------------------------------+ <-- sp
 83	 *
 84	 * The register stack looks _exactly_ the way it looked at the time the signal
 85	 * occurred.  In other words, we're treading on a potential mine-field: each
 86	 * incoming general register may be a NaT value (including sp, in which case the
 87	 * process ends up dying with a SIGSEGV).
 88	 *
 89	 * The first thing need to do is a cover to get the registers onto the backing
 90	 * store.  Once that is done, we invoke the signal handler which may modify some
 91	 * of the machine state.  After returning from the signal handler, we return
 92	 * control to the previous context by executing a sigreturn system call.  A signal
 93	 * handler may call the rt_sigreturn() function to directly return to a given
 94	 * sigcontext.  However, the user-level sigreturn() needs to do much more than
 95	 * calling the rt_sigreturn() system call as it needs to unwind the stack to
 96	 * restore preserved registers that may have been saved on the signal handler's
 97	 * call stack.
 98	 */
 99
100#define SIGTRAMP_SAVES										\
101	.unwabi 3, 's';		/* mark this as a sigtramp handler (saves scratch regs) */	\
102	.unwabi @svr4, 's'; /* backwards compatibility with old unwinders (remove in v2.7) */	\
103	.savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF;						\
104	.savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF;						\
105	.savesp pr, PR_OFF+SIGCONTEXT_OFF;     							\
106	.savesp rp, RP_OFF+SIGCONTEXT_OFF;							\
107	.savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF;							\
108	.vframesp SP_OFF+SIGCONTEXT_OFF
109
110GLOBAL_ENTRY(__kernel_sigtramp)
111	// describe the state that is active when we get here:
112	.prologue
113	SIGTRAMP_SAVES
114	.body
115
116	.label_state 1
117
118	adds base0=SIGHANDLER_OFF,sp
119	adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp
120	br.call.sptk.many rp=1f
1211:
122	ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF)	// get pointer to signal handler's plabel
123	ld8 r15=[base1]					// get address of new RBS base (or NULL)
124	cover				// push args in interrupted frame onto backing store
125	;;
126	cmp.ne p1,p0=r15,r0		// do we need to switch rbs? (note: pr is saved by kernel)
127	mov.m r9=ar.bsp			// fetch ar.bsp
128	.spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
129(p1)	br.cond.spnt setup_rbs		// yup -> (clobbers p8, r14-r16, and r18-r20)
130back_from_setup_rbs:
131	alloc r8=ar.pfs,0,0,3,0
132	ld8 out0=[base0],16		// load arg0 (signum)
133	adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
134	;;
135	ld8 out1=[base1]		// load arg1 (siginfop)
136	ld8 r10=[r17],8			// get signal handler entry point
137	;;
138	ld8 out2=[base0]		// load arg2 (sigcontextp)
139	ld8 gp=[r17]			// get signal handler's global pointer
140	adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
141	;;
142	.spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
143	st8 [base0]=r9			// save sc_ar_bsp
144	adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
145	adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
146	;;
147	stf.spill [base0]=f6,32
148	stf.spill [base1]=f7,32
149	;;
150	stf.spill [base0]=f8,32
151	stf.spill [base1]=f9,32
152	mov b6=r10
153	;;
154	stf.spill [base0]=f10,32
155	stf.spill [base1]=f11,32
156	;;
157	stf.spill [base0]=f12,32
158	stf.spill [base1]=f13,32
159	;;
160	stf.spill [base0]=f14,32
161	stf.spill [base1]=f15,32
162	br.call.sptk.many rp=b6			// call the signal handler
163.ret0:	adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
164	;;
165	ld8 r15=[base0]				// fetch sc_ar_bsp
166	mov r14=ar.bsp
167	;;
168	cmp.ne p1,p0=r14,r15			// do we need to restore the rbs?
169(p1)	br.cond.spnt restore_rbs		// yup -> (clobbers r14-r18, f6 & f7)
170	;;
171back_from_restore_rbs:
172	adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
173	adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
174	;;
175	ldf.fill f6=[base0],32
176	ldf.fill f7=[base1],32
177	;;
178	ldf.fill f8=[base0],32
179	ldf.fill f9=[base1],32
180	;;
181	ldf.fill f10=[base0],32
182	ldf.fill f11=[base1],32
183	;;
184	ldf.fill f12=[base0],32
185	ldf.fill f13=[base1],32
186	;;
187	ldf.fill f14=[base0],32
188	ldf.fill f15=[base1],32
189	mov r15=__NR_rt_sigreturn
190	.restore sp				// pop .prologue
191	break __BREAK_SYSCALL
192
193	.prologue
194	SIGTRAMP_SAVES
195setup_rbs:
196	mov ar.rsc=0				// put RSE into enforced lazy mode
197	;;
198	.save ar.rnat, r19
199	mov r19=ar.rnat				// save RNaT before switching backing store area
200	adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp
201
202	mov r18=ar.bspstore
203	mov ar.bspstore=r15			// switch over to new register backing store area
204	;;
205
206	.spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
207	st8 [r14]=r19				// save sc_ar_rnat
208	.body
209	mov.m r16=ar.bsp			// sc_loadrs <- (new bsp - new bspstore) << 16
210	adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp
211	;;
212	invala
213	sub r15=r16,r15
214	extr.u r20=r18,3,6
215	;;
216	mov ar.rsc=0xf				// set RSE into eager mode, pl 3
217	cmp.eq p8,p0=63,r20
218	shl r15=r15,16
219	;;
220	st8 [r14]=r15				// save sc_loadrs
221(p8)	st8 [r18]=r19		// if bspstore points at RNaT slot, store RNaT there now
222	.restore sp				// pop .prologue
223	br.cond.sptk back_from_setup_rbs
224
225	.prologue
226	SIGTRAMP_SAVES
227	.spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
228	.body
229restore_rbs:
230	// On input:
231	//	r14 = bsp1 (bsp at the time of return from signal handler)
232	//	r15 = bsp0 (bsp at the time the signal occurred)
233	//
234	// Here, we need to calculate bspstore0, the value that ar.bspstore needs
235	// to be set to, based on bsp0 and the size of the dirty partition on
236	// the alternate stack (sc_loadrs >> 16).  This can be done with the
237	// following algorithm:
238	//
239	//  bspstore0 = rse_skip_regs(bsp0, -rse_num_regs(bsp1 - (loadrs >> 19), bsp1));
240	//
241	// This is what the code below does.
242	//
243	alloc r2=ar.pfs,0,0,0,0			// alloc null frame
244	adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
245	adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp
246	;;
247	ld8 r17=[r16]
248	ld8 r16=[r18]			// get new rnat
249	extr.u r18=r15,3,6	// r18 <- rse_slot_num(bsp0)
250	;;
251	mov ar.rsc=r17			// put RSE into enforced lazy mode
252	shr.u r17=r17,16
253	;;
254	sub r14=r14,r17		// r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)
255	shr.u r17=r17,3		// r17 <- (sc_loadrs >> 19)
256	;;
257	loadrs			// restore dirty partition
258	extr.u r14=r14,3,6	// r14 <- rse_slot_num(bspstore1)
259	;;
260	add r14=r14,r17		// r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)
261	;;
262	shr.u r14=r14,6		// r14 <- (rse_slot_num(bspstore1) + (sc_loadrs >> 19))/0x40
263	;;
264	sub r14=r14,r17		// r14 <- -rse_num_regs(bspstore1, bsp1)
265	movl r17=0x8208208208208209
266	;;
267	add r18=r18,r14		// r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1)
268	setf.sig f7=r17
269	cmp.lt p7,p0=r14,r0	// p7 <- (r14 < 0)?
270	;;
271(p7)	adds r18=-62,r18	// delta -= 62
272	;;
273	setf.sig f6=r18
274	;;
275	xmpy.h f6=f6,f7
276	;;
277	getf.sig r17=f6
278	;;
279	add r17=r17,r18
280	shr r18=r18,63
281	;;
282	shr r17=r17,5
283	;;
284	sub r17=r17,r18		// r17 = delta/63
285	;;
286	add r17=r14,r17		// r17 <- delta/63 - rse_num_regs(bspstore1, bsp1)
287	;;
288	shladd r15=r17,3,r15	// r15 <- bsp0 + 8*(delta/63 - rse_num_regs(bspstore1, bsp1))
289	;;
290	mov ar.bspstore=r15			// switch back to old register backing store area
291	;;
292	mov ar.rnat=r16				// restore RNaT
293	mov ar.rsc=0xf				// (will be restored later on from sc_ar_rsc)
294	// invala not necessary as that will happen when returning to user-mode
295	br.cond.sptk back_from_restore_rbs
296END(__kernel_sigtramp)
297
298/*
299 * On entry:
300 *	r11 = saved ar.pfs
301 *	r15 = system call #
302 *	b0  = saved return address
303 *	b6  = return address
304 * On exit:
305 *	r11 = saved ar.pfs
306 *	r15 = system call #
307 *	b0  = saved return address
308 *	all other "scratch" registers:	undefined
309 *	all "preserved" registers:	same as on entry
310 */
311
312GLOBAL_ENTRY(__kernel_syscall_via_epc)
313	.prologue
314	.altrp b6
315	.body
316{
317	/*
318	 * Note: the kernel cannot assume that the first two instructions in this
319	 * bundle get executed.  The remaining code must be safe even if
320	 * they do not get executed.
321	 */
322	adds r17=-1024,r15			// A
323	mov r10=0				// A    default to successful syscall execution
324	epc					// B	causes split-issue
325}
326	;;
327	RSM_PSR_BE_I(r20, r22)			// M2 (5 cyc to srlz.d)
328	LOAD_FSYSCALL_TABLE(r14)		// X
329	;;
330	mov r16=IA64_KR(CURRENT)		// M2 (12 cyc)
331	shladd r18=r17,3,r14			// A
332	mov r19=NR_syscalls-1			// A
333	;;
334	lfetch [r18]				// M0|1
335	MOV_FROM_PSR(p0, r29, r8)		// M2 (12 cyc)
336	// If r17 is a NaT, p6 will be zero
337	cmp.geu p6,p7=r19,r17			// A    (sysnr > 0 && sysnr < 1024+NR_syscalls)?
338	;;
339	mov r21=ar.fpsr				// M2 (12 cyc)
340	tnat.nz p10,p9=r15			// I0
341	mov.i r26=ar.pfs			// I0 (would stall anyhow due to srlz.d...)
342	;;
343	srlz.d					// M0 (forces split-issue) ensure PSR.BE==0
344(p6)	ld8 r18=[r18]				// M0|1
345	nop.i 0
346	;;
347	nop.m 0
348(p6)	tbit.z.unc p8,p0=r18,0			// I0 (dual-issues with "mov b7=r18"!)
349	nop.i 0
350	;;
351	SSM_PSR_I(p8, p14, r25)
352(p6)	mov b7=r18				// I0
353(p8)	br.dptk.many b7				// B
354
355	mov r27=ar.rsc				// M2 (12 cyc)
356/*
357 * brl.cond doesn't work as intended because the linker would convert this branch
358 * into a branch to a PLT.  Perhaps there will be a way to avoid this with some
359 * future version of the linker.  In the meantime, we just use an indirect branch
360 * instead.
361 */
362#ifdef CONFIG_ITANIUM
363(p6)	add r14=-8,r14				// r14 <- addr of fsys_bubble_down entry
364	;;
365(p6)	ld8 r14=[r14]				// r14 <- fsys_bubble_down
366	;;
367(p6)	mov b7=r14
368(p6)	br.sptk.many b7
369#else
370	BRL_COND_FSYS_BUBBLE_DOWN(p6)
371#endif
372	SSM_PSR_I(p0, p14, r10)
373	mov r10=-1
374(p10)	mov r8=EINVAL
375(p9)	mov r8=ENOSYS
376	FSYS_RETURN
377
378#ifdef CONFIG_PARAVIRT
379	/*
380	 * padd to make the size of this symbol constant
381	 * independent of paravirtualization.
382	 */
383	.align PAGE_SIZE / 8
384#endif
385END(__kernel_syscall_via_epc)