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/arch/ia64/kernel/minstate.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 250 lines | 202 code | 8 blank | 40 comment | 0 complexity | e1548d525bd1bf0e8a425204b77c9b27 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1
  2#include <asm/cache.h>
  3
  4#include "entry.h"
  5#include "paravirt_inst.h"
  6
  7#ifdef CONFIG_VIRT_CPU_ACCOUNTING
  8/* read ar.itc in advance, and use it before leaving bank 0 */
  9#define ACCOUNT_GET_STAMP				\
 10(pUStk) mov.m r20=ar.itc;
 11#define ACCOUNT_SYS_ENTER				\
 12(pUStk) br.call.spnt rp=account_sys_enter		\
 13	;;
 14#else
 15#define ACCOUNT_GET_STAMP
 16#define ACCOUNT_SYS_ENTER
 17#endif
 18
 19.section ".data..patch.rse", "a"
 20.previous
 21
 22/*
 23 * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
 24 * the minimum state necessary that allows us to turn psr.ic back
 25 * on.
 26 *
 27 * Assumed state upon entry:
 28 *	psr.ic: off
 29 *	r31:	contains saved predicates (pr)
 30 *
 31 * Upon exit, the state is as follows:
 32 *	psr.ic: off
 33 *	 r2 = points to &pt_regs.r16
 34 *	 r8 = contents of ar.ccv
 35 *	 r9 = contents of ar.csd
 36 *	r10 = contents of ar.ssd
 37 *	r11 = FPSR_DEFAULT
 38 *	r12 = kernel sp (kernel virtual address)
 39 *	r13 = points to current task_struct (kernel virtual address)
 40 *	p15 = TRUE if psr.i is set in cr.ipsr
 41 *	predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
 42 *		preserved
 43 *
 44 * Note that psr.ic is NOT turned on by this macro.  This is so that
 45 * we can pass interruption state as arguments to a handler.
 46 */
 47#define IA64_NATIVE_DO_SAVE_MIN(__COVER,SAVE_IFS,EXTRA,WORKAROUND)				\
 48	mov r16=IA64_KR(CURRENT);	/* M */							\
 49	mov r27=ar.rsc;			/* M */							\
 50	mov r20=r1;			/* A */							\
 51	mov r25=ar.unat;		/* M */							\
 52	MOV_FROM_IPSR(p0,r29);		/* M */							\
 53	mov r26=ar.pfs;			/* I */							\
 54	MOV_FROM_IIP(r28);			/* M */						\
 55	mov r21=ar.fpsr;		/* M */							\
 56	__COVER;				/* B;; (or nothing) */				\
 57	;;											\
 58	adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16;						\
 59	;;											\
 60	ld1 r17=[r16];				/* load current->thread.on_ustack flag */	\
 61	st1 [r16]=r0;				/* clear current->thread.on_ustack flag */	\
 62	adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16						\
 63	/* switch from user to kernel RBS: */							\
 64	;;											\
 65	invala;				/* M */							\
 66	SAVE_IFS;										\
 67	cmp.eq pKStk,pUStk=r0,r17;		/* are we in kernel mode already? */		\
 68	;;											\
 69(pUStk)	mov ar.rsc=0;		/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */	\
 70	;;											\
 71(pUStk)	mov.m r24=ar.rnat;									\
 72(pUStk)	addl r22=IA64_RBS_OFFSET,r1;			/* compute base of RBS */		\
 73(pKStk) mov r1=sp;					/* get sp  */				\
 74	;;											\
 75(pUStk) lfetch.fault.excl.nt1 [r22];								\
 76(pUStk)	addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1;	/* compute base of memory stack */	\
 77(pUStk)	mov r23=ar.bspstore;				/* save ar.bspstore */			\
 78	;;											\
 79(pUStk)	mov ar.bspstore=r22;				/* switch to kernel RBS */		\
 80(pKStk) addl r1=-IA64_PT_REGS_SIZE,r1;			/* if in kernel mode, use sp (r12) */	\
 81	;;											\
 82(pUStk)	mov r18=ar.bsp;										\
 83(pUStk)	mov ar.rsc=0x3;		/* set eager mode, pl 0, little-endian, loadrs=0 */		\
 84	adds r17=2*L1_CACHE_BYTES,r1;		/* really: biggest cache-line size */		\
 85	adds r16=PT(CR_IPSR),r1;								\
 86	;;											\
 87	lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES;						\
 88	st8 [r16]=r29;		/* save cr.ipsr */						\
 89	;;											\
 90	lfetch.fault.excl.nt1 [r17];								\
 91	tbit.nz p15,p0=r29,IA64_PSR_I_BIT;							\
 92	mov r29=b0										\
 93	;;											\
 94	WORKAROUND;										\
 95	adds r16=PT(R8),r1;	/* initialize first base pointer */				\
 96	adds r17=PT(R9),r1;	/* initialize second base pointer */				\
 97(pKStk)	mov r18=r0;		/* make sure r18 isn't NaT */					\
 98	;;											\
 99.mem.offset 0,0; st8.spill [r16]=r8,16;								\
100.mem.offset 8,0; st8.spill [r17]=r9,16;								\
101        ;;											\
102.mem.offset 0,0; st8.spill [r16]=r10,24;							\
103.mem.offset 8,0; st8.spill [r17]=r11,24;							\
104        ;;											\
105	st8 [r16]=r28,16;	/* save cr.iip */						\
106	st8 [r17]=r30,16;	/* save cr.ifs */						\
107(pUStk)	sub r18=r18,r22;	/* r18=RSE.ndirty*8 */						\
108	mov r8=ar.ccv;										\
109	mov r9=ar.csd;										\
110	mov r10=ar.ssd;										\
111	movl r11=FPSR_DEFAULT;   /* L-unit */							\
112	;;											\
113	st8 [r16]=r25,16;	/* save ar.unat */						\
114	st8 [r17]=r26,16;	/* save ar.pfs */						\
115	shl r18=r18,16;		/* compute ar.rsc to be used for "loadrs" */			\
116	;;											\
117	st8 [r16]=r27,16;	/* save ar.rsc */						\
118(pUStk)	st8 [r17]=r24,16;	/* save ar.rnat */						\
119(pKStk)	adds r17=16,r17;	/* skip over ar_rnat field */					\
120	;;			/* avoid RAW on r16 & r17 */					\
121(pUStk)	st8 [r16]=r23,16;	/* save ar.bspstore */						\
122	st8 [r17]=r31,16;	/* save predicates */						\
123(pKStk)	adds r16=16,r16;	/* skip over ar_bspstore field */				\
124	;;											\
125	st8 [r16]=r29,16;	/* save b0 */							\
126	st8 [r17]=r18,16;	/* save ar.rsc value for "loadrs" */				\
127	cmp.eq pNonSys,pSys=r0,r0	/* initialize pSys=0, pNonSys=1 */			\
128	;;											\
129.mem.offset 0,0; st8.spill [r16]=r20,16;	/* save original r1 */				\
130.mem.offset 8,0; st8.spill [r17]=r12,16;							\
131	adds r12=-16,r1;	/* switch to kernel memory stack (with 16 bytes of scratch) */	\
132	;;											\
133.mem.offset 0,0; st8.spill [r16]=r13,16;							\
134.mem.offset 8,0; st8.spill [r17]=r21,16;	/* save ar.fpsr */				\
135	mov r13=IA64_KR(CURRENT);	/* establish `current' */				\
136	;;											\
137.mem.offset 0,0; st8.spill [r16]=r15,16;							\
138.mem.offset 8,0; st8.spill [r17]=r14,16;							\
139	;;											\
140.mem.offset 0,0; st8.spill [r16]=r2,16;								\
141.mem.offset 8,0; st8.spill [r17]=r3,16;								\
142	ACCOUNT_GET_STAMP									\
143	adds r2=IA64_PT_REGS_R16_OFFSET,r1;							\
144	;;											\
145	EXTRA;											\
146	movl r1=__gp;		/* establish kernel global pointer */				\
147	;;											\
148	ACCOUNT_SYS_ENTER									\
149	bsw.1;			/* switch back to bank 1 (must be last in insn group) */	\
150	;;
151
152/*
153 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
154 *
155 * Assumed state upon entry:
156 *	psr.ic: on
157 *	r2:	points to &pt_regs.r16
158 *	r3:	points to &pt_regs.r17
159 *	r8:	contents of ar.ccv
160 *	r9:	contents of ar.csd
161 *	r10:	contents of ar.ssd
162 *	r11:	FPSR_DEFAULT
163 *
164 * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
165 */
166#define SAVE_REST				\
167.mem.offset 0,0; st8.spill [r2]=r16,16;		\
168.mem.offset 8,0; st8.spill [r3]=r17,16;		\
169	;;					\
170.mem.offset 0,0; st8.spill [r2]=r18,16;		\
171.mem.offset 8,0; st8.spill [r3]=r19,16;		\
172	;;					\
173.mem.offset 0,0; st8.spill [r2]=r20,16;		\
174.mem.offset 8,0; st8.spill [r3]=r21,16;		\
175	mov r18=b6;				\
176	;;					\
177.mem.offset 0,0; st8.spill [r2]=r22,16;		\
178.mem.offset 8,0; st8.spill [r3]=r23,16;		\
179	mov r19=b7;				\
180	;;					\
181.mem.offset 0,0; st8.spill [r2]=r24,16;		\
182.mem.offset 8,0; st8.spill [r3]=r25,16;		\
183	;;					\
184.mem.offset 0,0; st8.spill [r2]=r26,16;		\
185.mem.offset 8,0; st8.spill [r3]=r27,16;		\
186	;;					\
187.mem.offset 0,0; st8.spill [r2]=r28,16;		\
188.mem.offset 8,0; st8.spill [r3]=r29,16;		\
189	;;					\
190.mem.offset 0,0; st8.spill [r2]=r30,16;		\
191.mem.offset 8,0; st8.spill [r3]=r31,32;		\
192	;;					\
193	mov ar.fpsr=r11;	/* M-unit */	\
194	st8 [r2]=r8,8;		/* ar.ccv */	\
195	adds r24=PT(B6)-PT(F7),r3;		\
196	;;					\
197	stf.spill [r2]=f6,32;			\
198	stf.spill [r3]=f7,32;			\
199	;;					\
200	stf.spill [r2]=f8,32;			\
201	stf.spill [r3]=f9,32;			\
202	;;					\
203	stf.spill [r2]=f10;			\
204	stf.spill [r3]=f11;			\
205	adds r25=PT(B7)-PT(F11),r3;		\
206	;;					\
207	st8 [r24]=r18,16;       /* b6 */	\
208	st8 [r25]=r19,16;       /* b7 */	\
209	;;					\
210	st8 [r24]=r9;        	/* ar.csd */	\
211	st8 [r25]=r10;      	/* ar.ssd */	\
212	;;
213
214#define RSE_WORKAROUND				\
215(pUStk) extr.u r17=r18,3,6;			\
216(pUStk)	sub r16=r18,r22;			\
217[1:](pKStk)	br.cond.sptk.many 1f;		\
218	.xdata4 ".data..patch.rse",1b-.		\
219	;;					\
220	cmp.ge p6,p7 = 33,r17;			\
221	;;					\
222(p6)	mov r17=0x310;				\
223(p7)	mov r17=0x308;				\
224	;;					\
225	cmp.leu p1,p0=r16,r17;			\
226(p1)	br.cond.sptk.many 1f;			\
227	dep.z r17=r26,0,62;			\
228	movl r16=2f;				\
229	;;					\
230	mov ar.pfs=r17;				\
231	dep r27=r0,r27,16,14;			\
232	mov b0=r16;				\
233	;;					\
234	br.ret.sptk b0;				\
235	;;					\
2362:						\
237	mov ar.rsc=r0				\
238	;;					\
239	flushrs;				\
240	;;					\
241	mov ar.bspstore=r22			\
242	;;					\
243	mov r18=ar.bsp;				\
244	;;					\
2451:						\
246	.pred.rel "mutex", pKStk, pUStk
247
248#define SAVE_MIN_WITH_COVER	DO_SAVE_MIN(COVER, mov r30=cr.ifs, , RSE_WORKAROUND)
249#define SAVE_MIN_WITH_COVER_R19	DO_SAVE_MIN(COVER, mov r30=cr.ifs, mov r15=r19, RSE_WORKAROUND)
250#define SAVE_MIN			DO_SAVE_MIN(     , mov r30=r0, , )