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/arch/ia64/lib/memset.S

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
Assembly | 362 lines | 291 code | 20 blank | 51 comment | 7 complexity | f98703f96f897cb3865cd2851f57e1cc MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /* Optimized version of the standard memset() function.
  2. Copyright (c) 2002 Hewlett-Packard Co/CERN
  3. Sverre Jarp <Sverre.Jarp@cern.ch>
  4. Return: dest
  5. Inputs:
  6. in0: dest
  7. in1: value
  8. in2: count
  9. The algorithm is fairly straightforward: set byte by byte until we
  10. we get to a 16B-aligned address, then loop on 128 B chunks using an
  11. early store as prefetching, then loop on 32B chucks, then clear remaining
  12. words, finally clear remaining bytes.
  13. Since a stf.spill f0 can store 16B in one go, we use this instruction
  14. to get peak speed when value = 0. */
  15. #include <asm/asmmacro.h>
  16. #undef ret
  17. #define dest in0
  18. #define value in1
  19. #define cnt in2
  20. #define tmp r31
  21. #define save_lc r30
  22. #define ptr0 r29
  23. #define ptr1 r28
  24. #define ptr2 r27
  25. #define ptr3 r26
  26. #define ptr9 r24
  27. #define loopcnt r23
  28. #define linecnt r22
  29. #define bytecnt r21
  30. #define fvalue f6
  31. // This routine uses only scratch predicate registers (p6 - p15)
  32. #define p_scr p6 // default register for same-cycle branches
  33. #define p_nz p7
  34. #define p_zr p8
  35. #define p_unalgn p9
  36. #define p_y p11
  37. #define p_n p12
  38. #define p_yy p13
  39. #define p_nn p14
  40. #define MIN1 15
  41. #define MIN1P1HALF 8
  42. #define LINE_SIZE 128
  43. #define LSIZE_SH 7 // shift amount
  44. #define PREF_AHEAD 8
  45. GLOBAL_ENTRY(memset)
  46. { .mmi
  47. .prologue
  48. alloc tmp = ar.pfs, 3, 0, 0, 0
  49. lfetch.nt1 [dest] //
  50. .save ar.lc, save_lc
  51. mov.i save_lc = ar.lc
  52. .body
  53. } { .mmi
  54. mov ret0 = dest // return value
  55. cmp.ne p_nz, p_zr = value, r0 // use stf.spill if value is zero
  56. cmp.eq p_scr, p0 = cnt, r0
  57. ;; }
  58. { .mmi
  59. and ptr2 = -(MIN1+1), dest // aligned address
  60. and tmp = MIN1, dest // prepare to check for correct alignment
  61. tbit.nz p_y, p_n = dest, 0 // Do we have an odd address? (M_B_U)
  62. } { .mib
  63. mov ptr1 = dest
  64. mux1 value = value, @brcst // create 8 identical bytes in word
  65. (p_scr) br.ret.dpnt.many rp // return immediately if count = 0
  66. ;; }
  67. { .mib
  68. cmp.ne p_unalgn, p0 = tmp, r0 //
  69. } { .mib
  70. sub bytecnt = (MIN1+1), tmp // NB: # of bytes to move is 1 higher than loopcnt
  71. cmp.gt p_scr, p0 = 16, cnt // is it a minimalistic task?
  72. (p_scr) br.cond.dptk.many .move_bytes_unaligned // go move just a few (M_B_U)
  73. ;; }
  74. { .mmi
  75. (p_unalgn) add ptr1 = (MIN1+1), ptr2 // after alignment
  76. (p_unalgn) add ptr2 = MIN1P1HALF, ptr2 // after alignment
  77. (p_unalgn) tbit.nz.unc p_y, p_n = bytecnt, 3 // should we do a st8 ?
  78. ;; }
  79. { .mib
  80. (p_y) add cnt = -8, cnt //
  81. (p_unalgn) tbit.nz.unc p_yy, p_nn = bytecnt, 2 // should we do a st4 ?
  82. } { .mib
  83. (p_y) st8 [ptr2] = value,-4 //
  84. (p_n) add ptr2 = 4, ptr2 //
  85. ;; }
  86. { .mib
  87. (p_yy) add cnt = -4, cnt //
  88. (p_unalgn) tbit.nz.unc p_y, p_n = bytecnt, 1 // should we do a st2 ?
  89. } { .mib
  90. (p_yy) st4 [ptr2] = value,-2 //
  91. (p_nn) add ptr2 = 2, ptr2 //
  92. ;; }
  93. { .mmi
  94. mov tmp = LINE_SIZE+1 // for compare
  95. (p_y) add cnt = -2, cnt //
  96. (p_unalgn) tbit.nz.unc p_yy, p_nn = bytecnt, 0 // should we do a st1 ?
  97. } { .mmi
  98. setf.sig fvalue=value // transfer value to FLP side
  99. (p_y) st2 [ptr2] = value,-1 //
  100. (p_n) add ptr2 = 1, ptr2 //
  101. ;; }
  102. { .mmi
  103. (p_yy) st1 [ptr2] = value //
  104. cmp.gt p_scr, p0 = tmp, cnt // is it a minimalistic task?
  105. } { .mbb
  106. (p_yy) add cnt = -1, cnt //
  107. (p_scr) br.cond.dpnt.many .fraction_of_line // go move just a few
  108. ;; }
  109. { .mib
  110. nop.m 0
  111. shr.u linecnt = cnt, LSIZE_SH
  112. (p_zr) br.cond.dptk.many .l1b // Jump to use stf.spill
  113. ;; }
  114. TEXT_ALIGN(32) // --------------------- // L1A: store ahead into cache lines; fill later
  115. { .mmi
  116. and tmp = -(LINE_SIZE), cnt // compute end of range
  117. mov ptr9 = ptr1 // used for prefetching
  118. and cnt = (LINE_SIZE-1), cnt // remainder
  119. } { .mmi
  120. mov loopcnt = PREF_AHEAD-1 // default prefetch loop
  121. cmp.gt p_scr, p0 = PREF_AHEAD, linecnt // check against actual value
  122. ;; }
  123. { .mmi
  124. (p_scr) add loopcnt = -1, linecnt //
  125. add ptr2 = 8, ptr1 // start of stores (beyond prefetch stores)
  126. add ptr1 = tmp, ptr1 // first address beyond total range
  127. ;; }
  128. { .mmi
  129. add tmp = -1, linecnt // next loop count
  130. mov.i ar.lc = loopcnt //
  131. ;; }
  132. .pref_l1a:
  133. { .mib
  134. stf8 [ptr9] = fvalue, 128 // Do stores one cache line apart
  135. nop.i 0
  136. br.cloop.dptk.few .pref_l1a
  137. ;; }
  138. { .mmi
  139. add ptr0 = 16, ptr2 // Two stores in parallel
  140. mov.i ar.lc = tmp //
  141. ;; }
  142. .l1ax:
  143. { .mmi
  144. stf8 [ptr2] = fvalue, 8
  145. stf8 [ptr0] = fvalue, 8
  146. ;; }
  147. { .mmi
  148. stf8 [ptr2] = fvalue, 24
  149. stf8 [ptr0] = fvalue, 24
  150. ;; }
  151. { .mmi
  152. stf8 [ptr2] = fvalue, 8
  153. stf8 [ptr0] = fvalue, 8
  154. ;; }
  155. { .mmi
  156. stf8 [ptr2] = fvalue, 24
  157. stf8 [ptr0] = fvalue, 24
  158. ;; }
  159. { .mmi
  160. stf8 [ptr2] = fvalue, 8
  161. stf8 [ptr0] = fvalue, 8
  162. ;; }
  163. { .mmi
  164. stf8 [ptr2] = fvalue, 24
  165. stf8 [ptr0] = fvalue, 24
  166. ;; }
  167. { .mmi
  168. stf8 [ptr2] = fvalue, 8
  169. stf8 [ptr0] = fvalue, 32
  170. cmp.lt p_scr, p0 = ptr9, ptr1 // do we need more prefetching?
  171. ;; }
  172. { .mmb
  173. stf8 [ptr2] = fvalue, 24
  174. (p_scr) stf8 [ptr9] = fvalue, 128
  175. br.cloop.dptk.few .l1ax
  176. ;; }
  177. { .mbb
  178. cmp.le p_scr, p0 = 8, cnt // just a few bytes left ?
  179. (p_scr) br.cond.dpnt.many .fraction_of_line // Branch no. 2
  180. br.cond.dpnt.many .move_bytes_from_alignment // Branch no. 3
  181. ;; }
  182. TEXT_ALIGN(32)
  183. .l1b: // ------------------------------------ // L1B: store ahead into cache lines; fill later
  184. { .mmi
  185. and tmp = -(LINE_SIZE), cnt // compute end of range
  186. mov ptr9 = ptr1 // used for prefetching
  187. and cnt = (LINE_SIZE-1), cnt // remainder
  188. } { .mmi
  189. mov loopcnt = PREF_AHEAD-1 // default prefetch loop
  190. cmp.gt p_scr, p0 = PREF_AHEAD, linecnt // check against actual value
  191. ;; }
  192. { .mmi
  193. (p_scr) add loopcnt = -1, linecnt
  194. add ptr2 = 16, ptr1 // start of stores (beyond prefetch stores)
  195. add ptr1 = tmp, ptr1 // first address beyond total range
  196. ;; }
  197. { .mmi
  198. add tmp = -1, linecnt // next loop count
  199. mov.i ar.lc = loopcnt
  200. ;; }
  201. .pref_l1b:
  202. { .mib
  203. stf.spill [ptr9] = f0, 128 // Do stores one cache line apart
  204. nop.i 0
  205. br.cloop.dptk.few .pref_l1b
  206. ;; }
  207. { .mmi
  208. add ptr0 = 16, ptr2 // Two stores in parallel
  209. mov.i ar.lc = tmp
  210. ;; }
  211. .l1bx:
  212. { .mmi
  213. stf.spill [ptr2] = f0, 32
  214. stf.spill [ptr0] = f0, 32
  215. ;; }
  216. { .mmi
  217. stf.spill [ptr2] = f0, 32
  218. stf.spill [ptr0] = f0, 32
  219. ;; }
  220. { .mmi
  221. stf.spill [ptr2] = f0, 32
  222. stf.spill [ptr0] = f0, 64
  223. cmp.lt p_scr, p0 = ptr9, ptr1 // do we need more prefetching?
  224. ;; }
  225. { .mmb
  226. stf.spill [ptr2] = f0, 32
  227. (p_scr) stf.spill [ptr9] = f0, 128
  228. br.cloop.dptk.few .l1bx
  229. ;; }
  230. { .mib
  231. cmp.gt p_scr, p0 = 8, cnt // just a few bytes left ?
  232. (p_scr) br.cond.dpnt.many .move_bytes_from_alignment //
  233. ;; }
  234. .fraction_of_line:
  235. { .mib
  236. add ptr2 = 16, ptr1
  237. shr.u loopcnt = cnt, 5 // loopcnt = cnt / 32
  238. ;; }
  239. { .mib
  240. cmp.eq p_scr, p0 = loopcnt, r0
  241. add loopcnt = -1, loopcnt
  242. (p_scr) br.cond.dpnt.many .store_words
  243. ;; }
  244. { .mib
  245. and cnt = 0x1f, cnt // compute the remaining cnt
  246. mov.i ar.lc = loopcnt
  247. ;; }
  248. TEXT_ALIGN(32)
  249. .l2: // ------------------------------------ // L2A: store 32B in 2 cycles
  250. { .mmb
  251. stf8 [ptr1] = fvalue, 8
  252. stf8 [ptr2] = fvalue, 8
  253. ;; } { .mmb
  254. stf8 [ptr1] = fvalue, 24
  255. stf8 [ptr2] = fvalue, 24
  256. br.cloop.dptk.many .l2
  257. ;; }
  258. .store_words:
  259. { .mib
  260. cmp.gt p_scr, p0 = 8, cnt // just a few bytes left ?
  261. (p_scr) br.cond.dpnt.many .move_bytes_from_alignment // Branch
  262. ;; }
  263. { .mmi
  264. stf8 [ptr1] = fvalue, 8 // store
  265. cmp.le p_y, p_n = 16, cnt
  266. add cnt = -8, cnt // subtract
  267. ;; }
  268. { .mmi
  269. (p_y) stf8 [ptr1] = fvalue, 8 // store
  270. (p_y) cmp.le.unc p_yy, p_nn = 16, cnt
  271. (p_y) add cnt = -8, cnt // subtract
  272. ;; }
  273. { .mmi // store
  274. (p_yy) stf8 [ptr1] = fvalue, 8
  275. (p_yy) add cnt = -8, cnt // subtract
  276. ;; }
  277. .move_bytes_from_alignment:
  278. { .mib
  279. cmp.eq p_scr, p0 = cnt, r0
  280. tbit.nz.unc p_y, p0 = cnt, 2 // should we terminate with a st4 ?
  281. (p_scr) br.cond.dpnt.few .restore_and_exit
  282. ;; }
  283. { .mib
  284. (p_y) st4 [ptr1] = value,4
  285. tbit.nz.unc p_yy, p0 = cnt, 1 // should we terminate with a st2 ?
  286. ;; }
  287. { .mib
  288. (p_yy) st2 [ptr1] = value,2
  289. tbit.nz.unc p_y, p0 = cnt, 0 // should we terminate with a st1 ?
  290. ;; }
  291. { .mib
  292. (p_y) st1 [ptr1] = value
  293. ;; }
  294. .restore_and_exit:
  295. { .mib
  296. nop.m 0
  297. mov.i ar.lc = save_lc
  298. br.ret.sptk.many rp
  299. ;; }
  300. .move_bytes_unaligned:
  301. { .mmi
  302. .pred.rel "mutex",p_y, p_n
  303. .pred.rel "mutex",p_yy, p_nn
  304. (p_n) cmp.le p_yy, p_nn = 4, cnt
  305. (p_y) cmp.le p_yy, p_nn = 5, cnt
  306. (p_n) add ptr2 = 2, ptr1
  307. } { .mmi
  308. (p_y) add ptr2 = 3, ptr1
  309. (p_y) st1 [ptr1] = value, 1 // fill 1 (odd-aligned) byte [15, 14 (or less) left]
  310. (p_y) add cnt = -1, cnt
  311. ;; }
  312. { .mmi
  313. (p_yy) cmp.le.unc p_y, p0 = 8, cnt
  314. add ptr3 = ptr1, cnt // prepare last store
  315. mov.i ar.lc = save_lc
  316. } { .mmi
  317. (p_yy) st2 [ptr1] = value, 4 // fill 2 (aligned) bytes
  318. (p_yy) st2 [ptr2] = value, 4 // fill 2 (aligned) bytes [11, 10 (o less) left]
  319. (p_yy) add cnt = -4, cnt
  320. ;; }
  321. { .mmi
  322. (p_y) cmp.le.unc p_yy, p0 = 8, cnt
  323. add ptr3 = -1, ptr3 // last store
  324. tbit.nz p_scr, p0 = cnt, 1 // will there be a st2 at the end ?
  325. } { .mmi
  326. (p_y) st2 [ptr1] = value, 4 // fill 2 (aligned) bytes
  327. (p_y) st2 [ptr2] = value, 4 // fill 2 (aligned) bytes [7, 6 (or less) left]
  328. (p_y) add cnt = -4, cnt
  329. ;; }
  330. { .mmi
  331. (p_yy) st2 [ptr1] = value, 4 // fill 2 (aligned) bytes
  332. (p_yy) st2 [ptr2] = value, 4 // fill 2 (aligned) bytes [3, 2 (or less) left]
  333. tbit.nz p_y, p0 = cnt, 0 // will there be a st1 at the end ?
  334. } { .mmi
  335. (p_yy) add cnt = -4, cnt
  336. ;; }
  337. { .mmb
  338. (p_scr) st2 [ptr1] = value // fill 2 (aligned) bytes
  339. (p_y) st1 [ptr3] = value // fill last byte (using ptr3)
  340. br.ret.sptk.many rp
  341. }
  342. END(memset)