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/arch/x86/kernel/mmconf-fam10h_64.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 240 lines | 178 code | 39 blank | 23 comment | 37 complexity | 25ec1bef8148fea1c1b191475c91c2a1 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * AMD Family 10h mmconfig enablement
  3 */
  4
  5#include <linux/types.h>
  6#include <linux/mm.h>
  7#include <linux/string.h>
  8#include <linux/pci.h>
  9#include <linux/dmi.h>
 10#include <linux/range.h>
 11
 12#include <asm/pci-direct.h>
 13#include <linux/sort.h>
 14#include <asm/io.h>
 15#include <asm/msr.h>
 16#include <asm/acpi.h>
 17#include <asm/mmconfig.h>
 18#include <asm/pci_x86.h>
 19
 20struct pci_hostbridge_probe {
 21	u32 bus;
 22	u32 slot;
 23	u32 vendor;
 24	u32 device;
 25};
 26
 27static u64 __cpuinitdata fam10h_pci_mmconf_base;
 28static int __cpuinitdata fam10h_pci_mmconf_base_status;
 29
 30static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
 31	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
 32	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
 33};
 34
 35static int __cpuinit cmp_range(const void *x1, const void *x2)
 36{
 37	const struct range *r1 = x1;
 38	const struct range *r2 = x2;
 39	int start1, start2;
 40
 41	start1 = r1->start >> 32;
 42	start2 = r2->start >> 32;
 43
 44	return start1 - start2;
 45}
 46
 47/*[47:0] */
 48/* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
 49#define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
 50#define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32)))
 51static void __cpuinit get_fam10h_pci_mmconf_base(void)
 52{
 53	int i;
 54	unsigned bus;
 55	unsigned slot;
 56	int found;
 57
 58	u64 val;
 59	u32 address;
 60	u64 tom2;
 61	u64 base = FAM10H_PCI_MMCONF_BASE;
 62
 63	int hi_mmio_num;
 64	struct range range[8];
 65
 66	/* only try to get setting from BSP */
 67	/* -1 or 1 */
 68	if (fam10h_pci_mmconf_base_status)
 69		return;
 70
 71	if (!early_pci_allowed())
 72		goto fail;
 73
 74	found = 0;
 75	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
 76		u32 id;
 77		u16 device;
 78		u16 vendor;
 79
 80		bus = pci_probes[i].bus;
 81		slot = pci_probes[i].slot;
 82		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 83
 84		vendor = id & 0xffff;
 85		device = (id>>16) & 0xffff;
 86		if (pci_probes[i].vendor == vendor &&
 87		    pci_probes[i].device == device) {
 88			found = 1;
 89			break;
 90		}
 91	}
 92
 93	if (!found)
 94		goto fail;
 95
 96	/* SYS_CFG */
 97	address = MSR_K8_SYSCFG;
 98	rdmsrl(address, val);
 99
100	/* TOP_MEM2 is not enabled? */
101	if (!(val & (1<<21))) {
102		tom2 = 0;
103	} else {
104		/* TOP_MEM2 */
105		address = MSR_K8_TOP_MEM2;
106		rdmsrl(address, val);
107		tom2 = val & (0xffffULL<<32);
108	}
109
110	if (base <= tom2)
111		base = tom2 + (1ULL<<32);
112
113	/*
114	 * need to check if the range is in the high mmio range that is
115	 * above 4G
116	 */
117	hi_mmio_num = 0;
118	for (i = 0; i < 8; i++) {
119		u32 reg;
120		u64 start;
121		u64 end;
122		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
123		if (!(reg & 3))
124			continue;
125
126		start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
127		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
128		end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
129
130		if (!end)
131			continue;
132
133		range[hi_mmio_num].start = start;
134		range[hi_mmio_num].end = end;
135		hi_mmio_num++;
136	}
137
138	if (!hi_mmio_num)
139		goto out;
140
141	/* sort the range */
142	sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
143
144	if (range[hi_mmio_num - 1].end < base)
145		goto out;
146	if (range[0].start > base)
147		goto out;
148
149	/* need to find one window */
150	base = range[0].start - (1ULL << 32);
151	if ((base > tom2) && BASE_VALID(base))
152		goto out;
153	base = range[hi_mmio_num - 1].end + (1ULL << 32);
154	if ((base > tom2) && BASE_VALID(base))
155		goto out;
156	/* need to find window between ranges */
157	if (hi_mmio_num > 1)
158	for (i = 0; i < hi_mmio_num - 1; i++) {
159		if (range[i + 1].start > (range[i].end + (1ULL << 32))) {
160			base = range[i].end + (1ULL << 32);
161			if ((base > tom2) && BASE_VALID(base))
162				goto out;
163		}
164	}
165
166fail:
167	fam10h_pci_mmconf_base_status = -1;
168	return;
169out:
170	fam10h_pci_mmconf_base = base;
171	fam10h_pci_mmconf_base_status = 1;
172}
173
174void __cpuinit fam10h_check_enable_mmcfg(void)
175{
176	u64 val;
177	u32 address;
178
179	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
180		return;
181
182	address = MSR_FAM10H_MMIO_CONF_BASE;
183	rdmsrl(address, val);
184
185	/* try to make sure that AP's setting is identical to BSP setting */
186	if (val & FAM10H_MMIO_CONF_ENABLE) {
187		unsigned busnbits;
188		busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
189			FAM10H_MMIO_CONF_BUSRANGE_MASK;
190
191		/* only trust the one handle 256 buses, if acpi=off */
192		if (!acpi_pci_disabled || busnbits >= 8) {
193			u64 base;
194			base = val & (0xffffULL << 32);
195			if (fam10h_pci_mmconf_base_status <= 0) {
196				fam10h_pci_mmconf_base = base;
197				fam10h_pci_mmconf_base_status = 1;
198				return;
199			} else if (fam10h_pci_mmconf_base ==  base)
200				return;
201		}
202	}
203
204	/*
205	 * if it is not enabled, try to enable it and assume only one segment
206	 * with 256 buses
207	 */
208	get_fam10h_pci_mmconf_base();
209	if (fam10h_pci_mmconf_base_status <= 0)
210		return;
211
212	printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
213	val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
214	     (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
215	val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
216	       FAM10H_MMIO_CONF_ENABLE;
217	wrmsrl(address, val);
218}
219
220static int __devinit set_check_enable_amd_mmconf(const struct dmi_system_id *d)
221{
222        pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
223        return 0;
224}
225
226static const struct dmi_system_id __cpuinitconst mmconf_dmi_table[] = {
227        {
228                .callback = set_check_enable_amd_mmconf,
229                .ident = "Sun Microsystems Machine",
230                .matches = {
231                        DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
232                },
233        },
234	{}
235};
236
237void __cpuinit check_enable_amd_mmconf_dmi(void)
238{
239	dmi_check_system(mmconf_dmi_table);
240}