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/arch/x86/kernel/pci-calgary_64.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 1596 lines | 1158 code | 286 blank | 152 comment | 167 complexity | ebb34b41ab0d90b73abc1c8ac1c7b67d MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
   1/*
   2 * Derived from arch/powerpc/kernel/iommu.c
   3 *
   4 * Copyright IBM Corporation, 2006-2007
   5 * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6 *
   7 * Author: Jon Mason <jdmason@kudzu.us>
   8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23 */
  24
  25#include <linux/kernel.h>
  26#include <linux/init.h>
  27#include <linux/types.h>
  28#include <linux/slab.h>
  29#include <linux/mm.h>
  30#include <linux/spinlock.h>
  31#include <linux/string.h>
  32#include <linux/crash_dump.h>
  33#include <linux/dma-mapping.h>
  34#include <linux/bitmap.h>
  35#include <linux/pci_ids.h>
  36#include <linux/pci.h>
  37#include <linux/delay.h>
  38#include <linux/scatterlist.h>
  39#include <linux/iommu-helper.h>
  40
  41#include <asm/iommu.h>
  42#include <asm/calgary.h>
  43#include <asm/tce.h>
  44#include <asm/pci-direct.h>
  45#include <asm/system.h>
  46#include <asm/dma.h>
  47#include <asm/rio.h>
  48#include <asm/bios_ebda.h>
  49#include <asm/x86_init.h>
  50
  51#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  52int use_calgary __read_mostly = 1;
  53#else
  54int use_calgary __read_mostly = 0;
  55#endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  56
  57#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  58#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  59
  60/* register offsets inside the host bridge space */
  61#define CALGARY_CONFIG_REG	0x0108
  62#define PHB_CSR_OFFSET		0x0110 /* Channel Status */
  63#define PHB_PLSSR_OFFSET	0x0120
  64#define PHB_CONFIG_RW_OFFSET	0x0160
  65#define PHB_IOBASE_BAR_LOW	0x0170
  66#define PHB_IOBASE_BAR_HIGH	0x0180
  67#define PHB_MEM_1_LOW		0x0190
  68#define PHB_MEM_1_HIGH		0x01A0
  69#define PHB_IO_ADDR_SIZE	0x01B0
  70#define PHB_MEM_1_SIZE		0x01C0
  71#define PHB_MEM_ST_OFFSET	0x01D0
  72#define PHB_AER_OFFSET		0x0200
  73#define PHB_CONFIG_0_HIGH	0x0220
  74#define PHB_CONFIG_0_LOW	0x0230
  75#define PHB_CONFIG_0_END	0x0240
  76#define PHB_MEM_2_LOW		0x02B0
  77#define PHB_MEM_2_HIGH		0x02C0
  78#define PHB_MEM_2_SIZE_HIGH	0x02D0
  79#define PHB_MEM_2_SIZE_LOW	0x02E0
  80#define PHB_DOSHOLE_OFFSET	0x08E0
  81
  82/* CalIOC2 specific */
  83#define PHB_SAVIOR_L2		0x0DB0
  84#define PHB_PAGE_MIG_CTRL	0x0DA8
  85#define PHB_PAGE_MIG_DEBUG	0x0DA0
  86#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  87
  88/* PHB_CONFIG_RW */
  89#define PHB_TCE_ENABLE		0x20000000
  90#define PHB_SLOT_DISABLE	0x1C000000
  91#define PHB_DAC_DISABLE		0x01000000
  92#define PHB_MEM2_ENABLE		0x00400000
  93#define PHB_MCSR_ENABLE		0x00100000
  94/* TAR (Table Address Register) */
  95#define TAR_SW_BITS		0x0000ffffffff800fUL
  96#define TAR_VALID		0x0000000000000008UL
  97/* CSR (Channel/DMA Status Register) */
  98#define CSR_AGENT_MASK		0xffe0ffff
  99/* CCR (Calgary Configuration Register) */
 100#define CCR_2SEC_TIMEOUT	0x000000000000000EUL
 101/* PMCR/PMDR (Page Migration Control/Debug Registers */
 102#define PMR_SOFTSTOP		0x80000000
 103#define PMR_SOFTSTOPFAULT	0x40000000
 104#define PMR_HARDSTOP		0x20000000
 105
 106/*
 107 * The maximum PHB bus number.
 108 * x3950M2 (rare): 8 chassis, 48 PHBs per chassis = 384
 109 * x3950M2: 4 chassis, 48 PHBs per chassis        = 192
 110 * x3950 (PCIE): 8 chassis, 32 PHBs per chassis   = 256
 111 * x3950 (PCIX): 8 chassis, 16 PHBs per chassis   = 128
 112 */
 113#define MAX_PHB_BUS_NUM		256
 114
 115#define PHBS_PER_CALGARY	  4
 116
 117/* register offsets in Calgary's internal register space */
 118static const unsigned long tar_offsets[] = {
 119	0x0580 /* TAR0 */,
 120	0x0588 /* TAR1 */,
 121	0x0590 /* TAR2 */,
 122	0x0598 /* TAR3 */
 123};
 124
 125static const unsigned long split_queue_offsets[] = {
 126	0x4870 /* SPLIT QUEUE 0 */,
 127	0x5870 /* SPLIT QUEUE 1 */,
 128	0x6870 /* SPLIT QUEUE 2 */,
 129	0x7870 /* SPLIT QUEUE 3 */
 130};
 131
 132static const unsigned long phb_offsets[] = {
 133	0x8000 /* PHB0 */,
 134	0x9000 /* PHB1 */,
 135	0xA000 /* PHB2 */,
 136	0xB000 /* PHB3 */
 137};
 138
 139/* PHB debug registers */
 140
 141static const unsigned long phb_debug_offsets[] = {
 142	0x4000	/* PHB 0 DEBUG */,
 143	0x5000	/* PHB 1 DEBUG */,
 144	0x6000	/* PHB 2 DEBUG */,
 145	0x7000	/* PHB 3 DEBUG */
 146};
 147
 148/*
 149 * STUFF register for each debug PHB,
 150 * byte 1 = start bus number, byte 2 = end bus number
 151 */
 152
 153#define PHB_DEBUG_STUFF_OFFSET	0x0020
 154
 155#define EMERGENCY_PAGES 32 /* = 128KB */
 156
 157unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 158static int translate_empty_slots __read_mostly = 0;
 159static int calgary_detected __read_mostly = 0;
 160
 161static struct rio_table_hdr	*rio_table_hdr __initdata;
 162static struct scal_detail	*scal_devs[MAX_NUMNODES] __initdata;
 163static struct rio_detail	*rio_devs[MAX_NUMNODES * 4] __initdata;
 164
 165struct calgary_bus_info {
 166	void *tce_space;
 167	unsigned char translation_disabled;
 168	signed char phbid;
 169	void __iomem *bbar;
 170};
 171
 172static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 173static void calgary_tce_cache_blast(struct iommu_table *tbl);
 174static void calgary_dump_error_regs(struct iommu_table *tbl);
 175static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 176static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 177static void calioc2_dump_error_regs(struct iommu_table *tbl);
 178static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 179static void get_tce_space_from_tar(void);
 180
 181static struct cal_chipset_ops calgary_chip_ops = {
 182	.handle_quirks = calgary_handle_quirks,
 183	.tce_cache_blast = calgary_tce_cache_blast,
 184	.dump_error_regs = calgary_dump_error_regs
 185};
 186
 187static struct cal_chipset_ops calioc2_chip_ops = {
 188	.handle_quirks = calioc2_handle_quirks,
 189	.tce_cache_blast = calioc2_tce_cache_blast,
 190	.dump_error_regs = calioc2_dump_error_regs
 191};
 192
 193static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 194
 195static inline int translation_enabled(struct iommu_table *tbl)
 196{
 197	/* only PHBs with translation enabled have an IOMMU table */
 198	return (tbl != NULL);
 199}
 200
 201static void iommu_range_reserve(struct iommu_table *tbl,
 202	unsigned long start_addr, unsigned int npages)
 203{
 204	unsigned long index;
 205	unsigned long end;
 206	unsigned long flags;
 207
 208	index = start_addr >> PAGE_SHIFT;
 209
 210	/* bail out if we're asked to reserve a region we don't cover */
 211	if (index >= tbl->it_size)
 212		return;
 213
 214	end = index + npages;
 215	if (end > tbl->it_size) /* don't go off the table */
 216		end = tbl->it_size;
 217
 218	spin_lock_irqsave(&tbl->it_lock, flags);
 219
 220	bitmap_set(tbl->it_map, index, npages);
 221
 222	spin_unlock_irqrestore(&tbl->it_lock, flags);
 223}
 224
 225static unsigned long iommu_range_alloc(struct device *dev,
 226				       struct iommu_table *tbl,
 227				       unsigned int npages)
 228{
 229	unsigned long flags;
 230	unsigned long offset;
 231	unsigned long boundary_size;
 232
 233	boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 234			      PAGE_SIZE) >> PAGE_SHIFT;
 235
 236	BUG_ON(npages == 0);
 237
 238	spin_lock_irqsave(&tbl->it_lock, flags);
 239
 240	offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 241				  npages, 0, boundary_size, 0);
 242	if (offset == ~0UL) {
 243		tbl->chip_ops->tce_cache_blast(tbl);
 244
 245		offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 246					  npages, 0, boundary_size, 0);
 247		if (offset == ~0UL) {
 248			printk(KERN_WARNING "Calgary: IOMMU full.\n");
 249			spin_unlock_irqrestore(&tbl->it_lock, flags);
 250			if (panic_on_overflow)
 251				panic("Calgary: fix the allocator.\n");
 252			else
 253				return DMA_ERROR_CODE;
 254		}
 255	}
 256
 257	tbl->it_hint = offset + npages;
 258	BUG_ON(tbl->it_hint > tbl->it_size);
 259
 260	spin_unlock_irqrestore(&tbl->it_lock, flags);
 261
 262	return offset;
 263}
 264
 265static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 266			      void *vaddr, unsigned int npages, int direction)
 267{
 268	unsigned long entry;
 269	dma_addr_t ret;
 270
 271	entry = iommu_range_alloc(dev, tbl, npages);
 272
 273	if (unlikely(entry == DMA_ERROR_CODE)) {
 274		printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 275		       "iommu %p\n", npages, tbl);
 276		return DMA_ERROR_CODE;
 277	}
 278
 279	/* set the return dma address */
 280	ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 281
 282	/* put the TCEs in the HW table */
 283	tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 284		  direction);
 285	return ret;
 286}
 287
 288static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 289	unsigned int npages)
 290{
 291	unsigned long entry;
 292	unsigned long badend;
 293	unsigned long flags;
 294
 295	/* were we called with bad_dma_address? */
 296	badend = DMA_ERROR_CODE + (EMERGENCY_PAGES * PAGE_SIZE);
 297	if (unlikely((dma_addr >= DMA_ERROR_CODE) && (dma_addr < badend))) {
 298		WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 299		       "address 0x%Lx\n", dma_addr);
 300		return;
 301	}
 302
 303	entry = dma_addr >> PAGE_SHIFT;
 304
 305	BUG_ON(entry + npages > tbl->it_size);
 306
 307	tce_free(tbl, entry, npages);
 308
 309	spin_lock_irqsave(&tbl->it_lock, flags);
 310
 311	bitmap_clear(tbl->it_map, entry, npages);
 312
 313	spin_unlock_irqrestore(&tbl->it_lock, flags);
 314}
 315
 316static inline struct iommu_table *find_iommu_table(struct device *dev)
 317{
 318	struct pci_dev *pdev;
 319	struct pci_bus *pbus;
 320	struct iommu_table *tbl;
 321
 322	pdev = to_pci_dev(dev);
 323
 324	/* search up the device tree for an iommu */
 325	pbus = pdev->bus;
 326	do {
 327		tbl = pci_iommu(pbus);
 328		if (tbl && tbl->it_busno == pbus->number)
 329			break;
 330		tbl = NULL;
 331		pbus = pbus->parent;
 332	} while (pbus);
 333
 334	BUG_ON(tbl && (tbl->it_busno != pbus->number));
 335
 336	return tbl;
 337}
 338
 339static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 340			     int nelems,enum dma_data_direction dir,
 341			     struct dma_attrs *attrs)
 342{
 343	struct iommu_table *tbl = find_iommu_table(dev);
 344	struct scatterlist *s;
 345	int i;
 346
 347	if (!translation_enabled(tbl))
 348		return;
 349
 350	for_each_sg(sglist, s, nelems, i) {
 351		unsigned int npages;
 352		dma_addr_t dma = s->dma_address;
 353		unsigned int dmalen = s->dma_length;
 354
 355		if (dmalen == 0)
 356			break;
 357
 358		npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
 359		iommu_free(tbl, dma, npages);
 360	}
 361}
 362
 363static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 364			  int nelems, enum dma_data_direction dir,
 365			  struct dma_attrs *attrs)
 366{
 367	struct iommu_table *tbl = find_iommu_table(dev);
 368	struct scatterlist *s;
 369	unsigned long vaddr;
 370	unsigned int npages;
 371	unsigned long entry;
 372	int i;
 373
 374	for_each_sg(sg, s, nelems, i) {
 375		BUG_ON(!sg_page(s));
 376
 377		vaddr = (unsigned long) sg_virt(s);
 378		npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
 379
 380		entry = iommu_range_alloc(dev, tbl, npages);
 381		if (entry == DMA_ERROR_CODE) {
 382			/* makes sure unmap knows to stop */
 383			s->dma_length = 0;
 384			goto error;
 385		}
 386
 387		s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 388
 389		/* insert into HW table */
 390		tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
 391
 392		s->dma_length = s->length;
 393	}
 394
 395	return nelems;
 396error:
 397	calgary_unmap_sg(dev, sg, nelems, dir, NULL);
 398	for_each_sg(sg, s, nelems, i) {
 399		sg->dma_address = DMA_ERROR_CODE;
 400		sg->dma_length = 0;
 401	}
 402	return 0;
 403}
 404
 405static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
 406				   unsigned long offset, size_t size,
 407				   enum dma_data_direction dir,
 408				   struct dma_attrs *attrs)
 409{
 410	void *vaddr = page_address(page) + offset;
 411	unsigned long uaddr;
 412	unsigned int npages;
 413	struct iommu_table *tbl = find_iommu_table(dev);
 414
 415	uaddr = (unsigned long)vaddr;
 416	npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
 417
 418	return iommu_alloc(dev, tbl, vaddr, npages, dir);
 419}
 420
 421static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
 422			       size_t size, enum dma_data_direction dir,
 423			       struct dma_attrs *attrs)
 424{
 425	struct iommu_table *tbl = find_iommu_table(dev);
 426	unsigned int npages;
 427
 428	npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
 429	iommu_free(tbl, dma_addr, npages);
 430}
 431
 432static void* calgary_alloc_coherent(struct device *dev, size_t size,
 433	dma_addr_t *dma_handle, gfp_t flag)
 434{
 435	void *ret = NULL;
 436	dma_addr_t mapping;
 437	unsigned int npages, order;
 438	struct iommu_table *tbl = find_iommu_table(dev);
 439
 440	size = PAGE_ALIGN(size); /* size rounded up to full pages */
 441	npages = size >> PAGE_SHIFT;
 442	order = get_order(size);
 443
 444	flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
 445
 446	/* alloc enough pages (and possibly more) */
 447	ret = (void *)__get_free_pages(flag, order);
 448	if (!ret)
 449		goto error;
 450	memset(ret, 0, size);
 451
 452	/* set up tces to cover the allocated range */
 453	mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 454	if (mapping == DMA_ERROR_CODE)
 455		goto free;
 456	*dma_handle = mapping;
 457	return ret;
 458free:
 459	free_pages((unsigned long)ret, get_order(size));
 460	ret = NULL;
 461error:
 462	return ret;
 463}
 464
 465static void calgary_free_coherent(struct device *dev, size_t size,
 466				  void *vaddr, dma_addr_t dma_handle)
 467{
 468	unsigned int npages;
 469	struct iommu_table *tbl = find_iommu_table(dev);
 470
 471	size = PAGE_ALIGN(size);
 472	npages = size >> PAGE_SHIFT;
 473
 474	iommu_free(tbl, dma_handle, npages);
 475	free_pages((unsigned long)vaddr, get_order(size));
 476}
 477
 478static struct dma_map_ops calgary_dma_ops = {
 479	.alloc_coherent = calgary_alloc_coherent,
 480	.free_coherent = calgary_free_coherent,
 481	.map_sg = calgary_map_sg,
 482	.unmap_sg = calgary_unmap_sg,
 483	.map_page = calgary_map_page,
 484	.unmap_page = calgary_unmap_page,
 485};
 486
 487static inline void __iomem * busno_to_bbar(unsigned char num)
 488{
 489	return bus_info[num].bbar;
 490}
 491
 492static inline int busno_to_phbid(unsigned char num)
 493{
 494	return bus_info[num].phbid;
 495}
 496
 497static inline unsigned long split_queue_offset(unsigned char num)
 498{
 499	size_t idx = busno_to_phbid(num);
 500
 501	return split_queue_offsets[idx];
 502}
 503
 504static inline unsigned long tar_offset(unsigned char num)
 505{
 506	size_t idx = busno_to_phbid(num);
 507
 508	return tar_offsets[idx];
 509}
 510
 511static inline unsigned long phb_offset(unsigned char num)
 512{
 513	size_t idx = busno_to_phbid(num);
 514
 515	return phb_offsets[idx];
 516}
 517
 518static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 519{
 520	unsigned long target = ((unsigned long)bar) | offset;
 521	return (void __iomem*)target;
 522}
 523
 524static inline int is_calioc2(unsigned short device)
 525{
 526	return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 527}
 528
 529static inline int is_calgary(unsigned short device)
 530{
 531	return (device == PCI_DEVICE_ID_IBM_CALGARY);
 532}
 533
 534static inline int is_cal_pci_dev(unsigned short device)
 535{
 536	return (is_calgary(device) || is_calioc2(device));
 537}
 538
 539static void calgary_tce_cache_blast(struct iommu_table *tbl)
 540{
 541	u64 val;
 542	u32 aer;
 543	int i = 0;
 544	void __iomem *bbar = tbl->bbar;
 545	void __iomem *target;
 546
 547	/* disable arbitration on the bus */
 548	target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 549	aer = readl(target);
 550	writel(0, target);
 551
 552	/* read plssr to ensure it got there */
 553	target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 554	val = readl(target);
 555
 556	/* poll split queues until all DMA activity is done */
 557	target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 558	do {
 559		val = readq(target);
 560		i++;
 561	} while ((val & 0xff) != 0xff && i < 100);
 562	if (i == 100)
 563		printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 564		       "continuing anyway\n");
 565
 566	/* invalidate TCE cache */
 567	target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 568	writeq(tbl->tar_val, target);
 569
 570	/* enable arbitration */
 571	target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 572	writel(aer, target);
 573	(void)readl(target); /* flush */
 574}
 575
 576static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 577{
 578	void __iomem *bbar = tbl->bbar;
 579	void __iomem *target;
 580	u64 val64;
 581	u32 val;
 582	int i = 0;
 583	int count = 1;
 584	unsigned char bus = tbl->it_busno;
 585
 586begin:
 587	printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 588	       "sequence - count %d\n", bus, count);
 589
 590	/* 1. using the Page Migration Control reg set SoftStop */
 591	target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 592	val = be32_to_cpu(readl(target));
 593	printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 594	val |= PMR_SOFTSTOP;
 595	printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 596	writel(cpu_to_be32(val), target);
 597
 598	/* 2. poll split queues until all DMA activity is done */
 599	printk(KERN_DEBUG "2a. starting to poll split queues\n");
 600	target = calgary_reg(bbar, split_queue_offset(bus));
 601	do {
 602		val64 = readq(target);
 603		i++;
 604	} while ((val64 & 0xff) != 0xff && i < 100);
 605	if (i == 100)
 606		printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 607		       "continuing anyway\n");
 608
 609	/* 3. poll Page Migration DEBUG for SoftStopFault */
 610	target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 611	val = be32_to_cpu(readl(target));
 612	printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 613
 614	/* 4. if SoftStopFault - goto (1) */
 615	if (val & PMR_SOFTSTOPFAULT) {
 616		if (++count < 100)
 617			goto begin;
 618		else {
 619			printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 620			       "aborting TCE cache flush sequence!\n");
 621			return; /* pray for the best */
 622		}
 623	}
 624
 625	/* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 626	target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 627	printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 628	val = be32_to_cpu(readl(target));
 629	printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 630	target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 631	val = be32_to_cpu(readl(target));
 632	printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 633
 634	/* 6. invalidate TCE cache */
 635	printk(KERN_DEBUG "6. invalidating TCE cache\n");
 636	target = calgary_reg(bbar, tar_offset(bus));
 637	writeq(tbl->tar_val, target);
 638
 639	/* 7. Re-read PMCR */
 640	printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 641	target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 642	val = be32_to_cpu(readl(target));
 643	printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 644
 645	/* 8. Remove HardStop */
 646	printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 647	target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 648	val = 0;
 649	printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 650	writel(cpu_to_be32(val), target);
 651	val = be32_to_cpu(readl(target));
 652	printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 653}
 654
 655static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 656	u64 limit)
 657{
 658	unsigned int numpages;
 659
 660	limit = limit | 0xfffff;
 661	limit++;
 662
 663	numpages = ((limit - start) >> PAGE_SHIFT);
 664	iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 665}
 666
 667static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 668{
 669	void __iomem *target;
 670	u64 low, high, sizelow;
 671	u64 start, limit;
 672	struct iommu_table *tbl = pci_iommu(dev->bus);
 673	unsigned char busnum = dev->bus->number;
 674	void __iomem *bbar = tbl->bbar;
 675
 676	/* peripheral MEM_1 region */
 677	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 678	low = be32_to_cpu(readl(target));
 679	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 680	high = be32_to_cpu(readl(target));
 681	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 682	sizelow = be32_to_cpu(readl(target));
 683
 684	start = (high << 32) | low;
 685	limit = sizelow;
 686
 687	calgary_reserve_mem_region(dev, start, limit);
 688}
 689
 690static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 691{
 692	void __iomem *target;
 693	u32 val32;
 694	u64 low, high, sizelow, sizehigh;
 695	u64 start, limit;
 696	struct iommu_table *tbl = pci_iommu(dev->bus);
 697	unsigned char busnum = dev->bus->number;
 698	void __iomem *bbar = tbl->bbar;
 699
 700	/* is it enabled? */
 701	target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 702	val32 = be32_to_cpu(readl(target));
 703	if (!(val32 & PHB_MEM2_ENABLE))
 704		return;
 705
 706	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 707	low = be32_to_cpu(readl(target));
 708	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 709	high = be32_to_cpu(readl(target));
 710	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 711	sizelow = be32_to_cpu(readl(target));
 712	target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 713	sizehigh = be32_to_cpu(readl(target));
 714
 715	start = (high << 32) | low;
 716	limit = (sizehigh << 32) | sizelow;
 717
 718	calgary_reserve_mem_region(dev, start, limit);
 719}
 720
 721/*
 722 * some regions of the IO address space do not get translated, so we
 723 * must not give devices IO addresses in those regions. The regions
 724 * are the 640KB-1MB region and the two PCI peripheral memory holes.
 725 * Reserve all of them in the IOMMU bitmap to avoid giving them out
 726 * later.
 727 */
 728static void __init calgary_reserve_regions(struct pci_dev *dev)
 729{
 730	unsigned int npages;
 731	u64 start;
 732	struct iommu_table *tbl = pci_iommu(dev->bus);
 733
 734	/* reserve EMERGENCY_PAGES from bad_dma_address and up */
 735	iommu_range_reserve(tbl, DMA_ERROR_CODE, EMERGENCY_PAGES);
 736
 737	/* avoid the BIOS/VGA first 640KB-1MB region */
 738	/* for CalIOC2 - avoid the entire first MB */
 739	if (is_calgary(dev->device)) {
 740		start = (640 * 1024);
 741		npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 742	} else { /* calioc2 */
 743		start = 0;
 744		npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 745	}
 746	iommu_range_reserve(tbl, start, npages);
 747
 748	/* reserve the two PCI peripheral memory regions in IO space */
 749	calgary_reserve_peripheral_mem_1(dev);
 750	calgary_reserve_peripheral_mem_2(dev);
 751}
 752
 753static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 754{
 755	u64 val64;
 756	u64 table_phys;
 757	void __iomem *target;
 758	int ret;
 759	struct iommu_table *tbl;
 760
 761	/* build TCE tables for each PHB */
 762	ret = build_tce_table(dev, bbar);
 763	if (ret)
 764		return ret;
 765
 766	tbl = pci_iommu(dev->bus);
 767	tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 768
 769	if (is_kdump_kernel())
 770		calgary_init_bitmap_from_tce_table(tbl);
 771	else
 772		tce_free(tbl, 0, tbl->it_size);
 773
 774	if (is_calgary(dev->device))
 775		tbl->chip_ops = &calgary_chip_ops;
 776	else if (is_calioc2(dev->device))
 777		tbl->chip_ops = &calioc2_chip_ops;
 778	else
 779		BUG();
 780
 781	calgary_reserve_regions(dev);
 782
 783	/* set TARs for each PHB */
 784	target = calgary_reg(bbar, tar_offset(dev->bus->number));
 785	val64 = be64_to_cpu(readq(target));
 786
 787	/* zero out all TAR bits under sw control */
 788	val64 &= ~TAR_SW_BITS;
 789	table_phys = (u64)__pa(tbl->it_base);
 790
 791	val64 |= table_phys;
 792
 793	BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 794	val64 |= (u64) specified_table_size;
 795
 796	tbl->tar_val = cpu_to_be64(val64);
 797
 798	writeq(tbl->tar_val, target);
 799	readq(target); /* flush */
 800
 801	return 0;
 802}
 803
 804static void __init calgary_free_bus(struct pci_dev *dev)
 805{
 806	u64 val64;
 807	struct iommu_table *tbl = pci_iommu(dev->bus);
 808	void __iomem *target;
 809	unsigned int bitmapsz;
 810
 811	target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 812	val64 = be64_to_cpu(readq(target));
 813	val64 &= ~TAR_SW_BITS;
 814	writeq(cpu_to_be64(val64), target);
 815	readq(target); /* flush */
 816
 817	bitmapsz = tbl->it_size / BITS_PER_BYTE;
 818	free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 819	tbl->it_map = NULL;
 820
 821	kfree(tbl);
 822	
 823	set_pci_iommu(dev->bus, NULL);
 824
 825	/* Can't free bootmem allocated memory after system is up :-( */
 826	bus_info[dev->bus->number].tce_space = NULL;
 827}
 828
 829static void calgary_dump_error_regs(struct iommu_table *tbl)
 830{
 831	void __iomem *bbar = tbl->bbar;
 832	void __iomem *target;
 833	u32 csr, plssr;
 834
 835	target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 836	csr = be32_to_cpu(readl(target));
 837
 838	target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 839	plssr = be32_to_cpu(readl(target));
 840
 841	/* If no error, the agent ID in the CSR is not valid */
 842	printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 843	       "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 844}
 845
 846static void calioc2_dump_error_regs(struct iommu_table *tbl)
 847{
 848	void __iomem *bbar = tbl->bbar;
 849	u32 csr, csmr, plssr, mck, rcstat;
 850	void __iomem *target;
 851	unsigned long phboff = phb_offset(tbl->it_busno);
 852	unsigned long erroff;
 853	u32 errregs[7];
 854	int i;
 855
 856	/* dump CSR */
 857	target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 858	csr = be32_to_cpu(readl(target));
 859	/* dump PLSSR */
 860	target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 861	plssr = be32_to_cpu(readl(target));
 862	/* dump CSMR */
 863	target = calgary_reg(bbar, phboff | 0x290);
 864	csmr = be32_to_cpu(readl(target));
 865	/* dump mck */
 866	target = calgary_reg(bbar, phboff | 0x800);
 867	mck = be32_to_cpu(readl(target));
 868
 869	printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 870	       tbl->it_busno);
 871
 872	printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 873	       csr, plssr, csmr, mck);
 874
 875	/* dump rest of error regs */
 876	printk(KERN_EMERG "Calgary: ");
 877	for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 878		/* err regs are at 0x810 - 0x870 */
 879		erroff = (0x810 + (i * 0x10));
 880		target = calgary_reg(bbar, phboff | erroff);
 881		errregs[i] = be32_to_cpu(readl(target));
 882		printk("0x%08x@0x%lx ", errregs[i], erroff);
 883	}
 884	printk("\n");
 885
 886	/* root complex status */
 887	target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 888	rcstat = be32_to_cpu(readl(target));
 889	printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 890	       PHB_ROOT_COMPLEX_STATUS);
 891}
 892
 893static void calgary_watchdog(unsigned long data)
 894{
 895	struct pci_dev *dev = (struct pci_dev *)data;
 896	struct iommu_table *tbl = pci_iommu(dev->bus);
 897	void __iomem *bbar = tbl->bbar;
 898	u32 val32;
 899	void __iomem *target;
 900
 901	target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 902	val32 = be32_to_cpu(readl(target));
 903
 904	/* If no error, the agent ID in the CSR is not valid */
 905	if (val32 & CSR_AGENT_MASK) {
 906		tbl->chip_ops->dump_error_regs(tbl);
 907
 908		/* reset error */
 909		writel(0, target);
 910
 911		/* Disable bus that caused the error */
 912		target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 913				     PHB_CONFIG_RW_OFFSET);
 914		val32 = be32_to_cpu(readl(target));
 915		val32 |= PHB_SLOT_DISABLE;
 916		writel(cpu_to_be32(val32), target);
 917		readl(target); /* flush */
 918	} else {
 919		/* Reset the timer */
 920		mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 921	}
 922}
 923
 924static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 925	unsigned char busnum, unsigned long timeout)
 926{
 927	u64 val64;
 928	void __iomem *target;
 929	unsigned int phb_shift = ~0; /* silence gcc */
 930	u64 mask;
 931
 932	switch (busno_to_phbid(busnum)) {
 933	case 0: phb_shift = (63 - 19);
 934		break;
 935	case 1: phb_shift = (63 - 23);
 936		break;
 937	case 2: phb_shift = (63 - 27);
 938		break;
 939	case 3: phb_shift = (63 - 35);
 940		break;
 941	default:
 942		BUG_ON(busno_to_phbid(busnum));
 943	}
 944
 945	target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 946	val64 = be64_to_cpu(readq(target));
 947
 948	/* zero out this PHB's timer bits */
 949	mask = ~(0xFUL << phb_shift);
 950	val64 &= mask;
 951	val64 |= (timeout << phb_shift);
 952	writeq(cpu_to_be64(val64), target);
 953	readq(target); /* flush */
 954}
 955
 956static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 957{
 958	unsigned char busnum = dev->bus->number;
 959	void __iomem *bbar = tbl->bbar;
 960	void __iomem *target;
 961	u32 val;
 962
 963	/*
 964	 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
 965	 */
 966	target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
 967	val = cpu_to_be32(readl(target));
 968	val |= 0x00800000;
 969	writel(cpu_to_be32(val), target);
 970}
 971
 972static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 973{
 974	unsigned char busnum = dev->bus->number;
 975
 976	/*
 977	 * Give split completion a longer timeout on bus 1 for aic94xx
 978	 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 979	 */
 980	if (is_calgary(dev->device) && (busnum == 1))
 981		calgary_set_split_completion_timeout(tbl->bbar, busnum,
 982						     CCR_2SEC_TIMEOUT);
 983}
 984
 985static void __init calgary_enable_translation(struct pci_dev *dev)
 986{
 987	u32 val32;
 988	unsigned char busnum;
 989	void __iomem *target;
 990	void __iomem *bbar;
 991	struct iommu_table *tbl;
 992
 993	busnum = dev->bus->number;
 994	tbl = pci_iommu(dev->bus);
 995	bbar = tbl->bbar;
 996
 997	/* enable TCE in PHB Config Register */
 998	target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 999	val32 = be32_to_cpu(readl(target));
1000	val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1001
1002	printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1003	       (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1004	       "Calgary" : "CalIOC2", busnum);
1005	printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1006	       "bus.\n");
1007
1008	writel(cpu_to_be32(val32), target);
1009	readl(target); /* flush */
1010
1011	init_timer(&tbl->watchdog_timer);
1012	tbl->watchdog_timer.function = &calgary_watchdog;
1013	tbl->watchdog_timer.data = (unsigned long)dev;
1014	mod_timer(&tbl->watchdog_timer, jiffies);
1015}
1016
1017static void __init calgary_disable_translation(struct pci_dev *dev)
1018{
1019	u32 val32;
1020	unsigned char busnum;
1021	void __iomem *target;
1022	void __iomem *bbar;
1023	struct iommu_table *tbl;
1024
1025	busnum = dev->bus->number;
1026	tbl = pci_iommu(dev->bus);
1027	bbar = tbl->bbar;
1028
1029	/* disable TCE in PHB Config Register */
1030	target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1031	val32 = be32_to_cpu(readl(target));
1032	val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1033
1034	printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1035	writel(cpu_to_be32(val32), target);
1036	readl(target); /* flush */
1037
1038	del_timer_sync(&tbl->watchdog_timer);
1039}
1040
1041static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1042{
1043	pci_dev_get(dev);
1044	set_pci_iommu(dev->bus, NULL);
1045
1046	/* is the device behind a bridge? */
1047	if (dev->bus->parent)
1048		dev->bus->parent->self = dev;
1049	else
1050		dev->bus->self = dev;
1051}
1052
1053static int __init calgary_init_one(struct pci_dev *dev)
1054{
1055	void __iomem *bbar;
1056	struct iommu_table *tbl;
1057	int ret;
1058
1059	bbar = busno_to_bbar(dev->bus->number);
1060	ret = calgary_setup_tar(dev, bbar);
1061	if (ret)
1062		goto done;
1063
1064	pci_dev_get(dev);
1065
1066	if (dev->bus->parent) {
1067		if (dev->bus->parent->self)
1068			printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1069			       "bus->parent->self!\n", dev);
1070		dev->bus->parent->self = dev;
1071	} else
1072		dev->bus->self = dev;
1073
1074	tbl = pci_iommu(dev->bus);
1075	tbl->chip_ops->handle_quirks(tbl, dev);
1076
1077	calgary_enable_translation(dev);
1078
1079	return 0;
1080
1081done:
1082	return ret;
1083}
1084
1085static int __init calgary_locate_bbars(void)
1086{
1087	int ret;
1088	int rioidx, phb, bus;
1089	void __iomem *bbar;
1090	void __iomem *target;
1091	unsigned long offset;
1092	u8 start_bus, end_bus;
1093	u32 val;
1094
1095	ret = -ENODATA;
1096	for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1097		struct rio_detail *rio = rio_devs[rioidx];
1098
1099		if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1100			continue;
1101
1102		/* map entire 1MB of Calgary config space */
1103		bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1104		if (!bbar)
1105			goto error;
1106
1107		for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1108			offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1109			target = calgary_reg(bbar, offset);
1110
1111			val = be32_to_cpu(readl(target));
1112
1113			start_bus = (u8)((val & 0x00FF0000) >> 16);
1114			end_bus = (u8)((val & 0x0000FF00) >> 8);
1115
1116			if (end_bus) {
1117				for (bus = start_bus; bus <= end_bus; bus++) {
1118					bus_info[bus].bbar = bbar;
1119					bus_info[bus].phbid = phb;
1120				}
1121			} else {
1122				bus_info[start_bus].bbar = bbar;
1123				bus_info[start_bus].phbid = phb;
1124			}
1125		}
1126	}
1127
1128	return 0;
1129
1130error:
1131	/* scan bus_info and iounmap any bbars we previously ioremap'd */
1132	for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1133		if (bus_info[bus].bbar)
1134			iounmap(bus_info[bus].bbar);
1135
1136	return ret;
1137}
1138
1139static int __init calgary_init(void)
1140{
1141	int ret;
1142	struct pci_dev *dev = NULL;
1143	struct calgary_bus_info *info;
1144
1145	ret = calgary_locate_bbars();
1146	if (ret)
1147		return ret;
1148
1149	/* Purely for kdump kernel case */
1150	if (is_kdump_kernel())
1151		get_tce_space_from_tar();
1152
1153	do {
1154		dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1155		if (!dev)
1156			break;
1157		if (!is_cal_pci_dev(dev->device))
1158			continue;
1159
1160		info = &bus_info[dev->bus->number];
1161		if (info->translation_disabled) {
1162			calgary_init_one_nontraslated(dev);
1163			continue;
1164		}
1165
1166		if (!info->tce_space && !translate_empty_slots)
1167			continue;
1168
1169		ret = calgary_init_one(dev);
1170		if (ret)
1171			goto error;
1172	} while (1);
1173
1174	dev = NULL;
1175	for_each_pci_dev(dev) {
1176		struct iommu_table *tbl;
1177
1178		tbl = find_iommu_table(&dev->dev);
1179
1180		if (translation_enabled(tbl))
1181			dev->dev.archdata.dma_ops = &calgary_dma_ops;
1182	}
1183
1184	return ret;
1185
1186error:
1187	do {
1188		dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1189		if (!dev)
1190			break;
1191		if (!is_cal_pci_dev(dev->device))
1192			continue;
1193
1194		info = &bus_info[dev->bus->number];
1195		if (info->translation_disabled) {
1196			pci_dev_put(dev);
1197			continue;
1198		}
1199		if (!info->tce_space && !translate_empty_slots)
1200			continue;
1201
1202		calgary_disable_translation(dev);
1203		calgary_free_bus(dev);
1204		pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1205		dev->dev.archdata.dma_ops = NULL;
1206	} while (1);
1207
1208	return ret;
1209}
1210
1211static inline int __init determine_tce_table_size(u64 ram)
1212{
1213	int ret;
1214
1215	if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1216		return specified_table_size;
1217
1218	/*
1219	 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1220	 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1221	 * larger table size has twice as many entries, so shift the
1222	 * max ram address by 13 to divide by 8K and then look at the
1223	 * order of the result to choose between 0-7.
1224	 */
1225	ret = get_order(ram >> 13);
1226	if (ret > TCE_TABLE_SIZE_8M)
1227		ret = TCE_TABLE_SIZE_8M;
1228
1229	return ret;
1230}
1231
1232static int __init build_detail_arrays(void)
1233{
1234	unsigned long ptr;
1235	unsigned numnodes, i;
1236	int scal_detail_size, rio_detail_size;
1237
1238	numnodes = rio_table_hdr->num_scal_dev;
1239	if (numnodes > MAX_NUMNODES){
1240		printk(KERN_WARNING
1241			"Calgary: MAX_NUMNODES too low! Defined as %d, "
1242			"but system has %d nodes.\n",
1243			MAX_NUMNODES, numnodes);
1244		return -ENODEV;
1245	}
1246
1247	switch (rio_table_hdr->version){
1248	case 2:
1249		scal_detail_size = 11;
1250		rio_detail_size = 13;
1251		break;
1252	case 3:
1253		scal_detail_size = 12;
1254		rio_detail_size = 15;
1255		break;
1256	default:
1257		printk(KERN_WARNING
1258		       "Calgary: Invalid Rio Grande Table Version: %d\n",
1259		       rio_table_hdr->version);
1260		return -EPROTO;
1261	}
1262
1263	ptr = ((unsigned long)rio_table_hdr) + 3;
1264	for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1265		scal_devs[i] = (struct scal_detail *)ptr;
1266
1267	for (i = 0; i < rio_table_hdr->num_rio_dev;
1268		    i++, ptr += rio_detail_size)
1269		rio_devs[i] = (struct rio_detail *)ptr;
1270
1271	return 0;
1272}
1273
1274static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1275{
1276	int dev;
1277	u32 val;
1278
1279	if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1280		/*
1281		 * FIXME: properly scan for devices accross the
1282		 * PCI-to-PCI bridge on every CalIOC2 port.
1283		 */
1284		return 1;
1285	}
1286
1287	for (dev = 1; dev < 8; dev++) {
1288		val = read_pci_config(bus, dev, 0, 0);
1289		if (val != 0xffffffff)
1290			break;
1291	}
1292	return (val != 0xffffffff);
1293}
1294
1295/*
1296 * calgary_init_bitmap_from_tce_table():
1297 * Funtion for kdump case. In the second/kdump kernel initialize
1298 * the bitmap based on the tce table entries obtained from first kernel
1299 */
1300static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1301{
1302	u64 *tp;
1303	unsigned int index;
1304	tp = ((u64 *)tbl->it_base);
1305	for (index = 0 ; index < tbl->it_size; index++) {
1306		if (*tp != 0x0)
1307			set_bit(index, tbl->it_map);
1308		tp++;
1309	}
1310}
1311
1312/*
1313 * get_tce_space_from_tar():
1314 * Function for kdump case. Get the tce tables from first kernel
1315 * by reading the contents of the base address register of calgary iommu
1316 */
1317static void __init get_tce_space_from_tar(void)
1318{
1319	int bus;
1320	void __iomem *target;
1321	unsigned long tce_space;
1322
1323	for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1324		struct calgary_bus_info *info = &bus_info[bus];
1325		unsigned short pci_device;
1326		u32 val;
1327
1328		val = read_pci_config(bus, 0, 0, 0);
1329		pci_device = (val & 0xFFFF0000) >> 16;
1330
1331		if (!is_cal_pci_dev(pci_device))
1332			continue;
1333		if (info->translation_disabled)
1334			continue;
1335
1336		if (calgary_bus_has_devices(bus, pci_device) ||
1337						translate_empty_slots) {
1338			target = calgary_reg(bus_info[bus].bbar,
1339						tar_offset(bus));
1340			tce_space = be64_to_cpu(readq(target));
1341			tce_space = tce_space & TAR_SW_BITS;
1342
1343			tce_space = tce_space & (~specified_table_size);
1344			info->tce_space = (u64 *)__va(tce_space);
1345		}
1346	}
1347	return;
1348}
1349
1350static int __init calgary_iommu_init(void)
1351{
1352	int ret;
1353
1354	/* ok, we're trying to use Calgary - let's roll */
1355	printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1356
1357	ret = calgary_init();
1358	if (ret) {
1359		printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1360		       "falling back to no_iommu\n", ret);
1361		return ret;
1362	}
1363
1364	return 0;
1365}
1366
1367void __init detect_calgary(void)
1368{
1369	int bus;
1370	void *tbl;
1371	int calgary_found = 0;
1372	unsigned long ptr;
1373	unsigned int offset, prev_offset;
1374	int ret;
1375
1376	/*
1377	 * if the user specified iommu=off or iommu=soft or we found
1378	 * another HW IOMMU already, bail out.
1379	 */
1380	if (no_iommu || iommu_detected)
1381		return;
1382
1383	if (!use_calgary)
1384		return;
1385
1386	if (!early_pci_allowed())
1387		return;
1388
1389	printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1390
1391	ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1392
1393	rio_table_hdr = NULL;
1394	prev_offset = 0;
1395	offset = 0x180;
1396	/*
1397	 * The next offset is stored in the 1st word.
1398	 * Only parse up until the offset increases:
1399	 */
1400	while (offset > prev_offset) {
1401		/* The block id is stored in the 2nd word */
1402		if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1403			/* set the pointer past the offset & block id */
1404			rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1405			break;
1406		}
1407		prev_offset = offset;
1408		offset = *((unsigned short *)(ptr + offset));
1409	}
1410	if (!rio_table_hdr) {
1411		printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1412		       "in EBDA - bailing!\n");
1413		return;
1414	}
1415
1416	ret = build_detail_arrays();
1417	if (ret) {
1418		printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1419		return;
1420	}
1421
1422	specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1423					saved_max_pfn : max_pfn) * PAGE_SIZE);
1424
1425	for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1426		struct calgary_bus_info *info = &bus_info[bus];
1427		unsigned short pci_device;
1428		u32 val;
1429
1430		val = read_pci_config(bus, 0, 0, 0);
1431		pci_device = (val & 0xFFFF0000) >> 16;
1432
1433		if (!is_cal_pci_dev(pci_device))
1434			continue;
1435
1436		if (info->translation_disabled)
1437			continue;
1438
1439		if (calgary_bus_has_devices(bus, pci_device) ||
1440		    translate_empty_slots) {
1441			/*
1442			 * If it is kdump kernel, find and use tce tables
1443			 * from first kernel, else allocate tce tables here
1444			 */
1445			if (!is_kdump_kernel()) {
1446				tbl = alloc_tce_table();
1447				if (!tbl)
1448					goto cleanup;
1449				info->tce_space = tbl;
1450			}
1451			calgary_found = 1;
1452		}
1453	}
1454
1455	printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1456	       calgary_found ? "found" : "not found");
1457
1458	if (calgary_found) {
1459		iommu_detected = 1;
1460		calgary_detected = 1;
1461		printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1462		printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1463		       specified_table_size);
1464
1465		x86_init.iommu.iommu_init = calgary_iommu_init;
1466	}
1467	return;
1468
1469cleanup:
1470	for (--bus; bus >= 0; --bus) {
1471		struct calgary_bus_info *info = &bus_info[bus];
1472
1473		if (info->tce_space)
1474			free_tce_table(info->tce_space);
1475	}
1476}
1477
1478static int __init calgary_parse_options(char *p)
1479{
1480	unsigned int bridge;
1481	size_t len;
1482	char* endp;
1483
1484	while (*p) {
1485		if (!strncmp(p, "64k", 3))
1486			specified_table_size = TCE_TABLE_SIZE_64K;
1487		else if (!strncmp(p, "128k", 4))
1488			specified_table_size = TCE_TABLE_SIZE_128K;
1489		else if (!strncmp(p, "256k", 4))
1490			specified_table_size = TCE_TABLE_SIZE_256K;
1491		else if (!strncmp(p, "512k", 4))
1492			specified_table_size = TCE_TABLE_SIZE_512K;
1493		else if (!strncmp(p, "1M", 2))
1494			specified_table_size = TCE_TABLE_SIZE_1M;
1495		else if (!strncmp(p, "2M", 2))
1496			specified_table_size = TCE_TABLE_SIZE_2M;
1497		else if (!strncmp(p, "4M", 2))
1498			specified_table_size = TCE_TABLE_SIZE_4M;
1499		else if (!strncmp(p, "8M", 2))
1500			specified_table_size = TCE_TABLE_SIZE_8M;
1501
1502		len = strlen("translate_empty_slots");
1503		if (!strncmp(p, "translate_empty_slots", len))
1504			translate_empty_slots = 1;
1505
1506		len = strlen("disable");
1507		if (!strncmp(p, "disable", len)) {
1508			p += len;
1509			if (*p == '=')
1510				++p;
1511			if (*p == '\0')
1512				break;
1513			bridge = simple_strtoul(p, &endp, 0);
1514			if (p == endp)
1515				break;
1516
1517			if (bridge < MAX_PHB_BUS_NUM) {
1518				printk(KERN_INFO "Calgary: disabling "
1519				       "translation for PHB %#x\n", bridge);
1520				bus_info[bridge].translation_disabled = 1;
1521			}
1522		}
1523
1524		p = strpbrk(p, ",");
1525		if (!p)
1526			break;
1527
1528		p++; /* skip ',' */
1529	}
1530	return 1;
1531}
1532__setup("calgary=", calgary_parse_options);
1533
1534static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1535{
1536	struct iommu_table *tbl;
1537	unsigned int npages;
1538	int i;
1539
1540	tbl = pci_iommu(dev->bus);
1541
1542	for (i = 0; i < 4; i++) {
1543		struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1544
1545		/* Don't give out TCEs that map MEM resources */
1546		if (!(r->flags & IORESOURCE_MEM))
1547			continue;
1548
1549		/* 0-based? we reserve the whole 1st MB anyway */
1550		if (!r->start)
1551			continue;
1552
1553		/* cover the whole region */
1554		npages = (r->end - r->start) >> PAGE_SHIFT;
1555		npages++;
1556
1557		iommu_range_reserve(tbl, r->start, npages);
1558	}
1559}
1560
1561static int __init calgary_fixup_tce_spaces(void)
1562{
1563	struct pci_dev *dev = NULL;
1564	struct calgary_bus_info *info;
1565
1566	if (no_iommu || swiotlb || !calgary_detected)
1567		return -ENODEV;
1568
1569	printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1570
1571	do {
1572		dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1573		if (!dev)
1574			break;
1575		if (!is_cal_pci_dev(dev->device))
1576			continue;
1577
1578		info = &bus_info[dev->bus->number];
1579		if (info->translation_disabled)
1580			continue;
1581
1582		if (!info->tce_space)
1583			continue;
1584
1585		calgary_fixup_one_tce_space(dev);
1586
1587	} while (1);
1588
1589	return 0;
1590}
1591
1592/*
1593 * We need to be call after pcibios_assign_resources (fs_initcall level)
1594 * and before device_initcall.
1595 */
1596rootfs_initcall(calgary_fixup_tce_spaces);