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/arch/x86/include/asm/user.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 63 lines | 27 code | 7 blank | 29 comment | 0 complexity | e38f9cb18e677fd3fa76d1806e6a888e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
 1#ifndef _ASM_X86_USER_H
 2#define _ASM_X86_USER_H
 3
 4#ifdef CONFIG_X86_32
 5# include "user_32.h"
 6#else
 7# include "user_64.h"
 8#endif
 9
10#include <asm/types.h>
11
12struct user_ymmh_regs {
13	/* 16 * 16 bytes for each YMMH-reg */
14	__u32 ymmh_space[64];
15};
16
17struct user_xsave_hdr {
18	__u64 xstate_bv;
19	__u64 reserved1[2];
20	__u64 reserved2[5];
21};
22
23/*
24 * The structure layout of user_xstateregs, used for exporting the
25 * extended register state through ptrace and core-dump (NT_X86_XSTATE note)
26 * interfaces will be same as the memory layout of xsave used by the processor
27 * (except for the bytes 464..511, which can be used by the software) and hence
28 * the size of this structure varies depending on the features supported by the
29 * processor and OS. The size of the structure that users need to use can be
30 * obtained by doing:
31 *     cpuid_count(0xd, 0, &eax, &ptrace_xstateregs_struct_size, &ecx, &edx);
32 * i.e., cpuid.(eax=0xd,ecx=0).ebx will be the size that user (debuggers, etc.)
33 * need to use.
34 *
35 * For now, only the first 8 bytes of the software usable bytes[464..471] will
36 * be used and will be set to OS enabled xstate mask (which is same as the
37 * 64bit mask returned by the xgetbv's xCR0).  Users (analyzing core dump
38 * remotely, etc.) can use this mask as well as the mask saved in the
39 * xstate_hdr bytes and interpret what states the processor/OS supports
40 * and what states are in modified/initialized conditions for the
41 * particular process/thread.
42 *
43 * Also when the user modifies certain state FP/SSE/etc through the
44 * ptrace interface, they must ensure that the xsave_hdr.xstate_bv
45 * bytes[512..519] of the memory layout are updated correspondingly.
46 * i.e., for example when FP state is modified to a non-init state,
47 * xsave_hdr.xstate_bv's bit 0 must be set to '1', when SSE is modified to
48 * non-init state, xsave_hdr.xstate_bv's bit 1 must to be set to '1', etc.
49 */
50#define USER_XSTATE_FX_SW_WORDS 6
51#define USER_XSTATE_XCR0_WORD	0
52
53struct user_xstateregs {
54	struct {
55		__u64 fpx_space[58];
56		__u64 xstate_fx_sw[USER_XSTATE_FX_SW_WORDS];
57	} i387;
58	struct user_xsave_hdr xsave_hdr;
59	struct user_ymmh_regs ymmh;
60	/* further processor state extensions go here */
61};
62
63#endif /* _ASM_X86_USER_H */