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/arch/sh/kernel/cpu/sh3/setup-sh7720.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 461 lines | 398 code | 45 blank | 18 comment | 0 complexity | 368b85491adcfb349f9b03899a0e6cbc MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * SH7720 Setup
  3 *
  4 *  Copyright (C) 2007  Markus Brunner, Mark Jonas
  5 *  Copyright (C) 2009  Paul Mundt
  6 *
  7 *  Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
  8 *
  9 *  Copyright (C) 2006  Paul Mundt
 10 *  Copyright (C) 2006  Jamie Lenehan
 11 *
 12 * This file is subject to the terms and conditions of the GNU General Public
 13 * License.  See the file "COPYING" in the main directory of this archive
 14 * for more details.
 15 */
 16#include <linux/platform_device.h>
 17#include <linux/init.h>
 18#include <linux/serial.h>
 19#include <linux/io.h>
 20#include <linux/serial_sci.h>
 21#include <linux/sh_timer.h>
 22#include <asm/rtc.h>
 23
 24static struct resource rtc_resources[] = {
 25	[0] = {
 26		.start	= 0xa413fec0,
 27		.end	= 0xa413fec0 + 0x28 - 1,
 28		.flags	= IORESOURCE_IO,
 29	},
 30	[1] = {
 31		/* Shared Period/Carry/Alarm IRQ */
 32		.start	= 20,
 33		.flags	= IORESOURCE_IRQ,
 34	},
 35};
 36
 37static struct sh_rtc_platform_info rtc_info = {
 38	.capabilities	= RTC_CAP_4_DIGIT_YEAR,
 39};
 40
 41static struct platform_device rtc_device = {
 42	.name		= "sh-rtc",
 43	.id		= -1,
 44	.num_resources	= ARRAY_SIZE(rtc_resources),
 45	.resource	= rtc_resources,
 46	.dev		= {
 47		.platform_data = &rtc_info,
 48	},
 49};
 50
 51static struct plat_sci_port scif0_platform_data = {
 52	.mapbase	= 0xa4430000,
 53	.flags		= UPF_BOOT_AUTOCONF,
 54	.type		= PORT_SCIF,
 55	.irqs		= { 80, 80, 80, 80 },
 56};
 57
 58static struct platform_device scif0_device = {
 59	.name		= "sh-sci",
 60	.id		= 0,
 61	.dev		= {
 62		.platform_data	= &scif0_platform_data,
 63	},
 64};
 65
 66static struct plat_sci_port scif1_platform_data = {
 67	.mapbase	= 0xa4438000,
 68	.flags		= UPF_BOOT_AUTOCONF,
 69	.type		= PORT_SCIF,
 70	.irqs           = { 81, 81, 81, 81 },
 71};
 72
 73static struct platform_device scif1_device = {
 74	.name		= "sh-sci",
 75	.id		= 1,
 76	.dev		= {
 77		.platform_data	= &scif1_platform_data,
 78	},
 79};
 80
 81static struct resource usb_ohci_resources[] = {
 82	[0] = {
 83		.start	= 0xA4428000,
 84		.end	= 0xA44280FF,
 85		.flags	= IORESOURCE_MEM,
 86	},
 87	[1] = {
 88		.start	= 67,
 89		.end	= 67,
 90		.flags	= IORESOURCE_IRQ,
 91	},
 92};
 93
 94static u64 usb_ohci_dma_mask = 0xffffffffUL;
 95static struct platform_device usb_ohci_device = {
 96	.name		= "sh_ohci",
 97	.id		= -1,
 98	.dev = {
 99		.dma_mask		= &usb_ohci_dma_mask,
100		.coherent_dma_mask	= 0xffffffff,
101	},
102	.num_resources	= ARRAY_SIZE(usb_ohci_resources),
103	.resource	= usb_ohci_resources,
104};
105
106static struct resource usbf_resources[] = {
107	[0] = {
108		.name	= "sh_udc",
109		.start	= 0xA4420000,
110		.end	= 0xA44200FF,
111		.flags	= IORESOURCE_MEM,
112	},
113	[1] = {
114		.name	= "sh_udc",
115		.start	= 65,
116		.end	= 65,
117		.flags	= IORESOURCE_IRQ,
118	},
119};
120
121static struct platform_device usbf_device = {
122	.name		= "sh_udc",
123	.id		= -1,
124	.dev = {
125		.dma_mask		= NULL,
126		.coherent_dma_mask	= 0xffffffff,
127	},
128	.num_resources	= ARRAY_SIZE(usbf_resources),
129	.resource	= usbf_resources,
130};
131
132static struct sh_timer_config cmt0_platform_data = {
133	.channel_offset = 0x10,
134	.timer_bit = 0,
135	.clockevent_rating = 125,
136	.clocksource_rating = 125,
137};
138
139static struct resource cmt0_resources[] = {
140	[0] = {
141		.start	= 0x044a0010,
142		.end	= 0x044a001b,
143		.flags	= IORESOURCE_MEM,
144	},
145	[1] = {
146		.start	= 104,
147		.flags	= IORESOURCE_IRQ,
148	},
149};
150
151static struct platform_device cmt0_device = {
152	.name		= "sh_cmt",
153	.id		= 0,
154	.dev = {
155		.platform_data	= &cmt0_platform_data,
156	},
157	.resource	= cmt0_resources,
158	.num_resources	= ARRAY_SIZE(cmt0_resources),
159};
160
161static struct sh_timer_config cmt1_platform_data = {
162	.channel_offset = 0x20,
163	.timer_bit = 1,
164};
165
166static struct resource cmt1_resources[] = {
167	[0] = {
168		.start	= 0x044a0020,
169		.end	= 0x044a002b,
170		.flags	= IORESOURCE_MEM,
171	},
172	[1] = {
173		.start	= 104,
174		.flags	= IORESOURCE_IRQ,
175	},
176};
177
178static struct platform_device cmt1_device = {
179	.name		= "sh_cmt",
180	.id		= 1,
181	.dev = {
182		.platform_data	= &cmt1_platform_data,
183	},
184	.resource	= cmt1_resources,
185	.num_resources	= ARRAY_SIZE(cmt1_resources),
186};
187
188static struct sh_timer_config cmt2_platform_data = {
189	.channel_offset = 0x30,
190	.timer_bit = 2,
191};
192
193static struct resource cmt2_resources[] = {
194	[0] = {
195		.start	= 0x044a0030,
196		.end	= 0x044a003b,
197		.flags	= IORESOURCE_MEM,
198	},
199	[1] = {
200		.start	= 104,
201		.flags	= IORESOURCE_IRQ,
202	},
203};
204
205static struct platform_device cmt2_device = {
206	.name		= "sh_cmt",
207	.id		= 2,
208	.dev = {
209		.platform_data	= &cmt2_platform_data,
210	},
211	.resource	= cmt2_resources,
212	.num_resources	= ARRAY_SIZE(cmt2_resources),
213};
214
215static struct sh_timer_config cmt3_platform_data = {
216	.channel_offset = 0x40,
217	.timer_bit = 3,
218};
219
220static struct resource cmt3_resources[] = {
221	[0] = {
222		.start	= 0x044a0040,
223		.end	= 0x044a004b,
224		.flags	= IORESOURCE_MEM,
225	},
226	[1] = {
227		.start	= 104,
228		.flags	= IORESOURCE_IRQ,
229	},
230};
231
232static struct platform_device cmt3_device = {
233	.name		= "sh_cmt",
234	.id		= 3,
235	.dev = {
236		.platform_data	= &cmt3_platform_data,
237	},
238	.resource	= cmt3_resources,
239	.num_resources	= ARRAY_SIZE(cmt3_resources),
240};
241
242static struct sh_timer_config cmt4_platform_data = {
243	.channel_offset = 0x50,
244	.timer_bit = 4,
245};
246
247static struct resource cmt4_resources[] = {
248	[0] = {
249		.start	= 0x044a0050,
250		.end	= 0x044a005b,
251		.flags	= IORESOURCE_MEM,
252	},
253	[1] = {
254		.start	= 104,
255		.flags	= IORESOURCE_IRQ,
256	},
257};
258
259static struct platform_device cmt4_device = {
260	.name		= "sh_cmt",
261	.id		= 4,
262	.dev = {
263		.platform_data	= &cmt4_platform_data,
264	},
265	.resource	= cmt4_resources,
266	.num_resources	= ARRAY_SIZE(cmt4_resources),
267};
268
269static struct sh_timer_config tmu0_platform_data = {
270	.channel_offset = 0x02,
271	.timer_bit = 0,
272	.clockevent_rating = 200,
273};
274
275static struct resource tmu0_resources[] = {
276	[0] = {
277		.start	= 0xa412fe94,
278		.end	= 0xa412fe9f,
279		.flags	= IORESOURCE_MEM,
280	},
281	[1] = {
282		.start	= 16,
283		.flags	= IORESOURCE_IRQ,
284	},
285};
286
287static struct platform_device tmu0_device = {
288	.name		= "sh_tmu",
289	.id		= 0,
290	.dev = {
291		.platform_data	= &tmu0_platform_data,
292	},
293	.resource	= tmu0_resources,
294	.num_resources	= ARRAY_SIZE(tmu0_resources),
295};
296
297static struct sh_timer_config tmu1_platform_data = {
298	.channel_offset = 0xe,
299	.timer_bit = 1,
300	.clocksource_rating = 200,
301};
302
303static struct resource tmu1_resources[] = {
304	[0] = {
305		.start	= 0xa412fea0,
306		.end	= 0xa412feab,
307		.flags	= IORESOURCE_MEM,
308	},
309	[1] = {
310		.start	= 17,
311		.flags	= IORESOURCE_IRQ,
312	},
313};
314
315static struct platform_device tmu1_device = {
316	.name		= "sh_tmu",
317	.id		= 1,
318	.dev = {
319		.platform_data	= &tmu1_platform_data,
320	},
321	.resource	= tmu1_resources,
322	.num_resources	= ARRAY_SIZE(tmu1_resources),
323};
324
325static struct sh_timer_config tmu2_platform_data = {
326	.channel_offset = 0x1a,
327	.timer_bit = 2,
328};
329
330static struct resource tmu2_resources[] = {
331	[0] = {
332		.start	= 0xa412feac,
333		.end	= 0xa412feb5,
334		.flags	= IORESOURCE_MEM,
335	},
336	[1] = {
337		.start	= 18,
338		.flags	= IORESOURCE_IRQ,
339	},
340};
341
342static struct platform_device tmu2_device = {
343	.name		= "sh_tmu",
344	.id		= 2,
345	.dev = {
346		.platform_data	= &tmu2_platform_data,
347	},
348	.resource	= tmu2_resources,
349	.num_resources	= ARRAY_SIZE(tmu2_resources),
350};
351
352static struct platform_device *sh7720_devices[] __initdata = {
353	&scif0_device,
354	&scif1_device,
355	&cmt0_device,
356	&cmt1_device,
357	&cmt2_device,
358	&cmt3_device,
359	&cmt4_device,
360	&tmu0_device,
361	&tmu1_device,
362	&tmu2_device,
363	&rtc_device,
364	&usb_ohci_device,
365	&usbf_device,
366};
367
368static int __init sh7720_devices_setup(void)
369{
370	return platform_add_devices(sh7720_devices,
371				    ARRAY_SIZE(sh7720_devices));
372}
373arch_initcall(sh7720_devices_setup);
374
375static struct platform_device *sh7720_early_devices[] __initdata = {
376	&scif0_device,
377	&scif1_device,
378	&cmt0_device,
379	&cmt1_device,
380	&cmt2_device,
381	&cmt3_device,
382	&cmt4_device,
383	&tmu0_device,
384	&tmu1_device,
385	&tmu2_device,
386};
387
388void __init plat_early_device_setup(void)
389{
390	early_platform_add_devices(sh7720_early_devices,
391				   ARRAY_SIZE(sh7720_early_devices));
392}
393
394enum {
395	UNUSED = 0,
396
397	/* interrupt sources */
398	TMU0, TMU1, TMU2, RTC,
399	WDT, REF_RCMI, SIM,
400	IRQ0, IRQ1, IRQ2, IRQ3,
401	USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
402	DMAC1, LCDC, SSL,
403	ADC, DMAC2, USBFI, CMT,
404	SCIF0, SCIF1,
405	PINT07, PINT815, TPU, IIC,
406	SIOF0, SIOF1, MMC, PCC,
407	USBHI, AFEIF,
408	H_UDI,
409};
410
411static struct intc_vect vectors[] __initdata = {
412	/* IRQ0->5 are handled in setup-sh3.c */
413	INTC_VECT(TMU0, 0x400),       INTC_VECT(TMU1, 0x420),
414	INTC_VECT(TMU2, 0x440),       INTC_VECT(RTC, 0x480),
415	INTC_VECT(RTC, 0x4a0),	      INTC_VECT(RTC, 0x4c0),
416	INTC_VECT(SIM, 0x4e0),	      INTC_VECT(SIM, 0x500),
417	INTC_VECT(SIM, 0x520),	      INTC_VECT(SIM, 0x540),
418	INTC_VECT(WDT, 0x560),        INTC_VECT(REF_RCMI, 0x580),
419	/* H_UDI cannot be masked */  INTC_VECT(TMU_SUNI, 0x6c0),
420	INTC_VECT(USBF_SPD, 0x6e0),   INTC_VECT(DMAC1, 0x800),
421	INTC_VECT(DMAC1, 0x820),      INTC_VECT(DMAC1, 0x840),
422	INTC_VECT(DMAC1, 0x860),      INTC_VECT(LCDC, 0x900),
423#if defined(CONFIG_CPU_SUBTYPE_SH7720)
424	INTC_VECT(SSL, 0x980),
425#endif
426	INTC_VECT(USBFI, 0xa20),      INTC_VECT(USBFI, 0xa40),
427	INTC_VECT(USBHI, 0xa60),
428	INTC_VECT(DMAC2, 0xb80),      INTC_VECT(DMAC2, 0xba0),
429	INTC_VECT(ADC, 0xbe0),        INTC_VECT(SCIF0, 0xc00),
430	INTC_VECT(SCIF1, 0xc20),      INTC_VECT(PINT07, 0xc80),
431	INTC_VECT(PINT815, 0xca0),    INTC_VECT(SIOF0, 0xd00),
432	INTC_VECT(SIOF1, 0xd20),      INTC_VECT(TPU, 0xd80),
433	INTC_VECT(TPU, 0xda0),        INTC_VECT(TPU, 0xdc0),
434	INTC_VECT(TPU, 0xde0),        INTC_VECT(IIC, 0xe00),
435	INTC_VECT(MMC, 0xe80),        INTC_VECT(MMC, 0xea0),
436	INTC_VECT(MMC, 0xec0),        INTC_VECT(MMC, 0xee0),
437	INTC_VECT(CMT, 0xf00),        INTC_VECT(PCC, 0xf60),
438	INTC_VECT(AFEIF, 0xfe0),
439};
440
441static struct intc_prio_reg prio_registers[] __initdata = {
442	{ 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
443	{ 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
444	{ 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
445	{ 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
446	{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
447	{ 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
448	{ 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
449	{ 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
450	{ 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
451	{ 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
452};
453
454static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
455		NULL, prio_registers, NULL);
456
457void __init plat_irq_setup(void)
458{
459	register_intc_controller(&intc_desc);
460	plat_irq_setup_sh3();
461}