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/arch/sh/kernel/cpu/sh4/setup-sh7750.c

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C | 436 lines | 361 code | 52 blank | 23 comment | 17 complexity | bca0766dfd08acd6a4e0a587e15dbfe0 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * SH7750/SH7751 Setup
  3 *
  4 *  Copyright (C) 2006  Paul Mundt
  5 *  Copyright (C) 2006  Jamie Lenehan
  6 *
  7 * This file is subject to the terms and conditions of the GNU General Public
  8 * License.  See the file "COPYING" in the main directory of this archive
  9 * for more details.
 10 */
 11#include <linux/platform_device.h>
 12#include <linux/init.h>
 13#include <linux/serial.h>
 14#include <linux/io.h>
 15#include <linux/sh_timer.h>
 16#include <linux/serial_sci.h>
 17
 18static struct resource rtc_resources[] = {
 19	[0] = {
 20		.start	= 0xffc80000,
 21		.end	= 0xffc80000 + 0x58 - 1,
 22		.flags	= IORESOURCE_IO,
 23	},
 24	[1] = {
 25		/* Shared Period/Carry/Alarm IRQ */
 26		.start	= 20,
 27		.flags	= IORESOURCE_IRQ,
 28	},
 29};
 30
 31static struct platform_device rtc_device = {
 32	.name		= "sh-rtc",
 33	.id		= -1,
 34	.num_resources	= ARRAY_SIZE(rtc_resources),
 35	.resource	= rtc_resources,
 36};
 37
 38static struct plat_sci_port scif0_platform_data = {
 39	.mapbase	= 0xffe00000,
 40	.flags		= UPF_BOOT_AUTOCONF,
 41	.type		= PORT_SCI,
 42	.irqs		= { 23, 23, 23, 0 },
 43};
 44
 45static struct platform_device scif0_device = {
 46	.name		= "sh-sci",
 47	.id		= 0,
 48	.dev		= {
 49		.platform_data	= &scif0_platform_data,
 50	},
 51};
 52
 53static struct plat_sci_port scif1_platform_data = {
 54	.mapbase	= 0xffe80000,
 55	.flags		= UPF_BOOT_AUTOCONF,
 56	.type		= PORT_SCIF,
 57	.irqs		= { 40, 40, 40, 40 },
 58};
 59
 60static struct platform_device scif1_device = {
 61	.name		= "sh-sci",
 62	.id		= 1,
 63	.dev		= {
 64		.platform_data	= &scif1_platform_data,
 65	},
 66};
 67
 68static struct sh_timer_config tmu0_platform_data = {
 69	.channel_offset = 0x04,
 70	.timer_bit = 0,
 71	.clockevent_rating = 200,
 72};
 73
 74static struct resource tmu0_resources[] = {
 75	[0] = {
 76		.start	= 0xffd80008,
 77		.end	= 0xffd80013,
 78		.flags	= IORESOURCE_MEM,
 79	},
 80	[1] = {
 81		.start	= 16,
 82		.flags	= IORESOURCE_IRQ,
 83	},
 84};
 85
 86static struct platform_device tmu0_device = {
 87	.name		= "sh_tmu",
 88	.id		= 0,
 89	.dev = {
 90		.platform_data	= &tmu0_platform_data,
 91	},
 92	.resource	= tmu0_resources,
 93	.num_resources	= ARRAY_SIZE(tmu0_resources),
 94};
 95
 96static struct sh_timer_config tmu1_platform_data = {
 97	.channel_offset = 0x10,
 98	.timer_bit = 1,
 99	.clocksource_rating = 200,
100};
101
102static struct resource tmu1_resources[] = {
103	[0] = {
104		.start	= 0xffd80014,
105		.end	= 0xffd8001f,
106		.flags	= IORESOURCE_MEM,
107	},
108	[1] = {
109		.start	= 17,
110		.flags	= IORESOURCE_IRQ,
111	},
112};
113
114static struct platform_device tmu1_device = {
115	.name		= "sh_tmu",
116	.id		= 1,
117	.dev = {
118		.platform_data	= &tmu1_platform_data,
119	},
120	.resource	= tmu1_resources,
121	.num_resources	= ARRAY_SIZE(tmu1_resources),
122};
123
124static struct sh_timer_config tmu2_platform_data = {
125	.channel_offset = 0x1c,
126	.timer_bit = 2,
127};
128
129static struct resource tmu2_resources[] = {
130	[0] = {
131		.start	= 0xffd80020,
132		.end	= 0xffd8002f,
133		.flags	= IORESOURCE_MEM,
134	},
135	[1] = {
136		.start	= 18,
137		.flags	= IORESOURCE_IRQ,
138	},
139};
140
141static struct platform_device tmu2_device = {
142	.name		= "sh_tmu",
143	.id		= 2,
144	.dev = {
145		.platform_data	= &tmu2_platform_data,
146	},
147	.resource	= tmu2_resources,
148	.num_resources	= ARRAY_SIZE(tmu2_resources),
149};
150
151/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
152#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
153	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
154	defined(CONFIG_CPU_SUBTYPE_SH7751R)
155
156static struct sh_timer_config tmu3_platform_data = {
157	.channel_offset = 0x04,
158	.timer_bit = 0,
159};
160
161static struct resource tmu3_resources[] = {
162	[0] = {
163		.start	= 0xfe100008,
164		.end	= 0xfe100013,
165		.flags	= IORESOURCE_MEM,
166	},
167	[1] = {
168		.start	= 72,
169		.flags	= IORESOURCE_IRQ,
170	},
171};
172
173static struct platform_device tmu3_device = {
174	.name		= "sh_tmu",
175	.id		= 3,
176	.dev = {
177		.platform_data	= &tmu3_platform_data,
178	},
179	.resource	= tmu3_resources,
180	.num_resources	= ARRAY_SIZE(tmu3_resources),
181};
182
183static struct sh_timer_config tmu4_platform_data = {
184	.channel_offset = 0x10,
185	.timer_bit = 1,
186};
187
188static struct resource tmu4_resources[] = {
189	[0] = {
190		.start	= 0xfe100014,
191		.end	= 0xfe10001f,
192		.flags	= IORESOURCE_MEM,
193	},
194	[1] = {
195		.start	= 76,
196		.flags	= IORESOURCE_IRQ,
197	},
198};
199
200static struct platform_device tmu4_device = {
201	.name		= "sh_tmu",
202	.id		= 4,
203	.dev = {
204		.platform_data	= &tmu4_platform_data,
205	},
206	.resource	= tmu4_resources,
207	.num_resources	= ARRAY_SIZE(tmu4_resources),
208};
209
210#endif
211
212static struct platform_device *sh7750_devices[] __initdata = {
213	&scif0_device,
214	&scif1_device,
215	&rtc_device,
216	&tmu0_device,
217	&tmu1_device,
218	&tmu2_device,
219#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
220	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
221	defined(CONFIG_CPU_SUBTYPE_SH7751R)
222	&tmu3_device,
223	&tmu4_device,
224#endif
225};
226
227static int __init sh7750_devices_setup(void)
228{
229	return platform_add_devices(sh7750_devices,
230				    ARRAY_SIZE(sh7750_devices));
231}
232arch_initcall(sh7750_devices_setup);
233
234static struct platform_device *sh7750_early_devices[] __initdata = {
235	&scif0_device,
236	&scif1_device,
237	&tmu0_device,
238	&tmu1_device,
239	&tmu2_device,
240#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
241	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
242	defined(CONFIG_CPU_SUBTYPE_SH7751R)
243	&tmu3_device,
244	&tmu4_device,
245#endif
246};
247
248void __init plat_early_device_setup(void)
249{
250	early_platform_add_devices(sh7750_early_devices,
251				   ARRAY_SIZE(sh7750_early_devices));
252}
253
254enum {
255	UNUSED = 0,
256
257	/* interrupt sources */
258	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
259	HUDI, GPIOI, DMAC,
260	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
261	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
262	TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
263
264	/* interrupt groups */
265	PCIC1,
266};
267
268static struct intc_vect vectors[] __initdata = {
269	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
270	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
271	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
272	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
273	INTC_VECT(RTC, 0x4c0),
274	INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
275	INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
276	INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
277	INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
278	INTC_VECT(WDT, 0x560),
279	INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
280};
281
282static struct intc_prio_reg prio_registers[] __initdata = {
283	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
284	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
285	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
286	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
287	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
288						 TMU4, TMU3,
289						 PCIC1, PCIC0_PCISERR } },
290};
291
292static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
293			 NULL, prio_registers, NULL);
294
295/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
296#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
297	defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
298	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
299	defined(CONFIG_CPU_SUBTYPE_SH7091)
300static struct intc_vect vectors_dma4[] __initdata = {
301	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
302	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
303	INTC_VECT(DMAC, 0x6c0),
304};
305
306static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
307			 vectors_dma4, NULL,
308			 NULL, prio_registers, NULL);
309#endif
310
311/* SH7750R and SH7751R both have 8-channel DMA controllers */
312#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
313static struct intc_vect vectors_dma8[] __initdata = {
314	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
315	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
316	INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
317	INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
318	INTC_VECT(DMAC, 0x6c0),
319};
320
321static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
322			 vectors_dma8, NULL,
323			 NULL, prio_registers, NULL);
324#endif
325
326/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
327#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
328	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
329	defined(CONFIG_CPU_SUBTYPE_SH7751R)
330static struct intc_vect vectors_tmu34[] __initdata = {
331	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
332};
333
334static struct intc_mask_reg mask_registers[] __initdata = {
335	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
336	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
337	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
338	    PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
339	    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
340	    PCIC1_PCIDMA3, PCIC0_PCISERR } },
341};
342
343static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
344			 vectors_tmu34, NULL,
345			 mask_registers, prio_registers, NULL);
346#endif
347
348/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
349static struct intc_vect vectors_irlm[] __initdata = {
350	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
351	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
352};
353
354static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
355			 NULL, prio_registers, NULL);
356
357/* SH7751 and SH7751R both have PCI */
358#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
359static struct intc_vect vectors_pci[] __initdata = {
360	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
361	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
362	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
363	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
364};
365
366static struct intc_group groups_pci[] __initdata = {
367	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
368		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
369};
370
371static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
372			 mask_registers, prio_registers, NULL);
373#endif
374
375#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
376	defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
377	defined(CONFIG_CPU_SUBTYPE_SH7091)
378void __init plat_irq_setup(void)
379{
380	/*
381	 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
382	 * see below..
383	 */
384	register_intc_controller(&intc_desc);
385	register_intc_controller(&intc_desc_dma4);
386}
387#endif
388
389#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
390void __init plat_irq_setup(void)
391{
392	register_intc_controller(&intc_desc);
393	register_intc_controller(&intc_desc_dma8);
394	register_intc_controller(&intc_desc_tmu34);
395}
396#endif
397
398#if defined(CONFIG_CPU_SUBTYPE_SH7751)
399void __init plat_irq_setup(void)
400{
401	register_intc_controller(&intc_desc);
402	register_intc_controller(&intc_desc_dma4);
403	register_intc_controller(&intc_desc_tmu34);
404	register_intc_controller(&intc_desc_pci);
405}
406#endif
407
408#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
409void __init plat_irq_setup(void)
410{
411	register_intc_controller(&intc_desc);
412	register_intc_controller(&intc_desc_dma8);
413	register_intc_controller(&intc_desc_tmu34);
414	register_intc_controller(&intc_desc_pci);
415}
416#endif
417
418#define INTC_ICR	0xffd00000UL
419#define INTC_ICR_IRLM   (1<<7)
420
421void __init plat_irq_setup_pins(int mode)
422{
423#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
424	BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
425	return;
426#endif
427
428	switch (mode) {
429	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
430		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
431		register_intc_controller(&intc_desc_irlm);
432		break;
433	default:
434		BUG();
435	}
436}