/arch/blackfin/mach-bf548/include/mach/defBF547.h

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  1. /*
    2. 

  2.  * Copyright 2008 Analog Devices Inc.
    3. 

  3.  *
    4. 

  4.  * Licensed under the ADI BSD license or the GPL-2 (or later)
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _DEF_BF547_H
    8. 

  8. #define _DEF_BF547_H
    9. 

  9. 

  10. /* Include all Core registers and bit definitions */
    11. 

  11. #include <asm/def_LPBlackfin.h>
    12. 

  12. 

  13. /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
    14. 

  14. 

  15. /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
    16. 

  16. #include "defBF54x_base.h"
    17. 

  17. 

  18. /* The following are the #defines needed by ADSP-BF547 that are not in the common header */
    19. 

  19. 

  20. /* Timer Registers */
    21. 

  21. 

  22. #define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
    23. 

  23. #define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
    24. 

  24. #define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
    25. 

  25. #define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
    26. 

  26. #define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
    27. 

  27. #define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
    28. 

  28. #define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
    29. 

  29. #define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
    30. 

  30. #define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
    31. 

  31. #define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
    32. 

  32. #define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
    33. 

  33. #define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
    34. 

  34. 

  35. /* Timer Group of 3 Registers */
    36. 

  36. 

  37. #define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
    38. 

  38. #define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
    39. 

  39. #define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
    40. 

  40. 

  41. /* SPORT0 Registers */
    42. 

  42. 

  43. #define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
    44. 

  44. #define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
    45. 

  45. #define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
    46. 

  46. #define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
    47. 

  47. #define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
    48. 

  48. #define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
    49. 

  49. #define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
    50. 

  50. #define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
    51. 

  51. #define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
    52. 

  52. #define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
    53. 

  53. #define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
    54. 

  54. #define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
    55. 

  55. #define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
    56. 

  56. #define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
    57. 

  57. #define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
    58. 

  58. #define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
    59. 

  59. #define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
    60. 

  60. #define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
    61. 

  61. #define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
    62. 

  62. #define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
    63. 

  63. #define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
    64. 

  64. #define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
    65. 

  65. 

  66. /* EPPI0 Registers */
    67. 

  67. 

  68. #define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
    69. 

  69. #define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
    70. 

  70. #define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
    71. 

  71. #define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
    72. 

  72. #define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
    73. 

  73. #define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
    74. 

  74. #define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
    75. 

  75. #define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
    76. 

  76. #define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
    77. 

  77. #define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
    78. 

  78. #define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
    79. 

  79. #define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
    80. 

  80. #define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
    81. 

  81. #define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
    82. 

  82. 

  83. /* UART2 Registers */
    84. 

  84. 

  85. #define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
    86. 

  86. #define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
    87. 

  87. #define                       UART2_GCTL  0xffc02108   /* Global Control Register */
    88. 

  88. #define                        UART2_LCR  0xffc0210c   /* Line Control Register */
    89. 

  89. #define                        UART2_MCR  0xffc02110   /* Modem Control Register */
    90. 

  90. #define                        UART2_LSR  0xffc02114   /* Line Status Register */
    91. 

  91. #define                        UART2_MSR  0xffc02118   /* Modem Status Register */
    92. 

  92. #define                        UART2_SCR  0xffc0211c   /* Scratch Register */
    93. 

  93. #define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
    94. 

  94. #define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
    95. 

  95. #define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
    96. 

  96. 

  97. /* Two Wire Interface Registers (TWI1) */
    98. 

  98. 

  99. #define                     TWI1_REGBASE  0xffc02200
    100. 

  100. #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
    101. 

  101. #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
    102. 

  102. #define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
    103. 

  103. #define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
    104. 

  104. #define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
    105. 

  105. #define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
    106. 

  106. #define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
    107. 

  107. #define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
    108. 

  108. #define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
    109. 

  109. #define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
    110. 

  110. #define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
    111. 

  111. #define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
    112. 

  112. #define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
    113. 

  113. #define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
    114. 

  114. #define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
    115. 

  115. #define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
    116. 

  116. 

  117. /* SPI2  Registers */
    118. 

  118. 

  119. #define                     SPI2_REGBASE  0xffc02400
    120. 

  120. #define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
    121. 

  121. #define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
    122. 

  122. #define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
    123. 

  123. #define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
    124. 

  124. #define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
    125. 

  125. #define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
    126. 

  126. #define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
    127. 

  127. 

  128. /* ATAPI Registers */
    129. 

  129. 

  130. #define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
    131. 

  131. #define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
    132. 

  132. #define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
    133. 

  133. #define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
    134. 

  134. #define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
    135. 

  135. #define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
    136. 

  136. #define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
    137. 

  137. #define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
    138. 

  138. #define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
    139. 

  139. #define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
    140. 

  140. #define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
    141. 

  141. #define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
    142. 

  142. #define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
    143. 

  143. #define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
    144. 

  144. #define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
    145. 

  145. #define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
    146. 

  146. #define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
    147. 

  147. #define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
    148. 

  148. #define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
    149. 

  149. #define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
    150. 

  150. #define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
    151. 

  151. #define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
    152. 

  152. #define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
    153. 

  153. #define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
    154. 

  154. #define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
    155. 

  155. 

  156. /* SDH Registers */
    157. 

  157. 

  158. #define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
    159. 

  159. #define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
    160. 

  160. #define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
    161. 

  161. #define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
    162. 

  162. #define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
    163. 

  163. #define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
    164. 

  164. #define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
    165. 

  165. #define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
    166. 

  166. #define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
    167. 

  167. #define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
    168. 

  168. #define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
    169. 

  169. #define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
    170. 

  170. #define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
    171. 

  171. #define                       SDH_STATUS  0xffc03934   /* SDH Status */
    172. 

  172. #define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
    173. 

  173. #define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
    174. 

  174. #define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
    175. 

  175. #define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
    176. 

  176. #define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
    177. 

  177. #define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
    178. 

  178. #define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
    179. 

  179. #define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
    180. 

  180. #define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
    181. 

  181. #define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
    182. 

  182. #define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
    183. 

  183. #define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
    184. 

  184. #define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
    185. 

  185. #define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
    186. 

  186. #define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
    187. 

  187. #define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
    188. 

  188. #define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
    189. 

  189. 

  190. /* HOST Port Registers */
    191. 

  191. 

  192. #define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
    193. 

  193. #define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
    194. 

  194. #define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
    195. 

  195. 

  196. /* USB Control Registers */
    197. 

  197. 

  198. #define                        USB_FADDR  0xffc03c00   /* Function address register */
    199. 

  199. #define                        USB_POWER  0xffc03c04   /* Power management register */
    200. 

  200. #define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
    201. 

  201. #define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
    202. 

  202. #define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
    203. 

  203. #define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
    204. 

  204. #define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
    205. 

  205. #define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
    206. 

  206. #define                        USB_FRAME  0xffc03c20   /* USB frame number */
    207. 

  207. #define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
    208. 

  208. #define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
    209. 

  209. #define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
    210. 

  210. #define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
    211. 

  211. 

  212. /* USB Packet Control Registers */
    213. 

  213. 

  214. #define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
    215. 

  215. #define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
    216. 

  216. #define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
    217. 

  217. #define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
    218. 

  218. #define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
    219. 

  219. #define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
    220. 

  220. #define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
    221. 

  221. #define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
    222. 

  222. #define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
    223. 

  223. #define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
    224. 

  224. #define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
    225. 

  225. #define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
    226. 

  226. #define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
    227. 

  227. 

  228. /* USB Endpoint FIFO Registers */
    229. 

  229. 

  230. #define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
    231. 

  231. #define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
    232. 

  232. #define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
    233. 

  233. #define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
    234. 

  234. #define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
    235. 

  235. #define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
    236. 

  236. #define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
    237. 

  237. #define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
    238. 

  238. 

  239. /* USB OTG Control Registers */
    240. 

  240. 

  241. #define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
    242. 

  242. #define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
    243. 

  243. #define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
    244. 

  244. 

  245. /* USB Phy Control Registers */
    246. 

  246. 

  247. #define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
    248. 

  248. #define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
    249. 

  249. #define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
    250. 

  250. #define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
    251. 

  251. #define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
    252. 

  252. 

  253. /* (APHY_CNTRL is for ADI usage only) */
    254. 

  254. 

  255. #define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
    256. 

  256. 

  257. /* (APHY_CALIB is for ADI usage only) */
    258. 

  258. 

  259. #define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
    260. 

  260. #define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
    261. 

  261. 

  262. /* (PHY_TEST is for ADI usage only) */
    263. 

  263. 

  264. #define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
    265. 

  265. #define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
    266. 

  266. #define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
    267. 

  267. 

  268. /* USB Endpoint 0 Control Registers */
    269. 

  269. 

  270. #define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
    271. 

  271. #define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
    272. 

  272. #define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
    273. 

  273. #define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
    274. 

  274. #define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
    275. 

  275. #define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
    276. 

  276. #define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
    277. 

  277. #define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
    278. 

  278. #define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
    279. 

  279. 

  280. /* USB Endpoint 1 Control Registers */
    281. 

  281. 

  282. #define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
    283. 

  283. #define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
    284. 

  284. #define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
    285. 

  285. #define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
    286. 

  286. #define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
    287. 

  287. #define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
    288. 

  288. #define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
    289. 

  289. #define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
    290. 

  290. #define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
    291. 

  291. #define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
    292. 

  292. 

  293. /* USB Endpoint 2 Control Registers */
    294. 

  294. 

  295. #define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
    296. 

  296. #define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
    297. 

  297. #define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
    298. 

  298. #define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
    299. 

  299. #define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
    300. 

  300. #define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
    301. 

  301. #define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
    302. 

  302. #define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
    303. 

  303. #define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
    304. 

  304. #define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
    305. 

  305. 

  306. /* USB Endpoint 3 Control Registers */
    307. 

  307. 

  308. #define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
    309. 

  309. #define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
    310. 

  310. #define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
    311. 

  311. #define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
    312. 

  312. #define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
    313. 

  313. #define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
    314. 

  314. #define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
    315. 

  315. #define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
    316. 

  316. #define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
    317. 

  317. #define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
    318. 

  318. 

  319. /* USB Endpoint 4 Control Registers */
    320. 

  320. 

  321. #define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
    322. 

  322. #define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
    323. 

  323. #define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
    324. 

  324. #define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
    325. 

  325. #define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
    326. 

  326. #define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
    327. 

  327. #define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
    328. 

  328. #define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
    329. 

  329. #define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
    330. 

  330. #define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
    331. 

  331. 

  332. /* USB Endpoint 5 Control Registers */
    333. 

  333. 

  334. #define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
    335. 

  335. #define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
    336. 

  336. #define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
    337. 

  337. #define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
    338. 

  338. #define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
    339. 

  339. #define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
    340. 

  340. #define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
    341. 

  341. #define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
    342. 

  342. #define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
    343. 

  343. #define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
    344. 

  344. 

  345. /* USB Endpoint 6 Control Registers */
    346. 

  346. 

  347. #define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
    348. 

  348. #define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
    349. 

  349. #define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
    350. 

  350. #define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
    351. 

  351. #define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
    352. 

  352. #define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
    353. 

  353. #define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
    354. 

  354. #define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
    355. 

  355. #define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
    356. 

  356. #define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
    357. 

  357. 

  358. /* USB Endpoint 7 Control Registers */
    359. 

  359. 

  360. #define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
    361. 

  361. #define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
    362. 

  362. #define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
    363. 

  363. #define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
    364. 

  364. #define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
    365. 

  365. #define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
    366. 

  366. #define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
    367. 

  367. #define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
    368. 

  368. #define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
    369. 

  369. #define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
    370. 

  370. #define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
    371. 

  371. #define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
    372. 

  372. 

  373. /* USB Channel 0 Config Registers */
    374. 

  374. 

  375. #define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
    376. 

  376. #define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
    377. 

  377. #define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
    378. 

  378. #define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
    379. 

  379. #define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
    380. 

  380. 

  381. /* USB Channel 1 Config Registers */
    382. 

  382. 

  383. #define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
    384. 

  384. #define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
    385. 

  385. #define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
    386. 

  386. #define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
    387. 

  387. #define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
    388. 

  388. 

  389. /* USB Channel 2 Config Registers */
    390. 

  390. 

  391. #define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
    392. 

  392. #define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
    393. 

  393. #define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
    394. 

  394. #define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
    395. 

  395. #define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
    396. 

  396. 

  397. /* USB Channel 3 Config Registers */
    398. 

  398. 

  399. #define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
    400. 

  400. #define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
    401. 

  401. #define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
    402. 

  402. #define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
    403. 

  403. #define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
    404. 

  404. 

  405. /* USB Channel 4 Config Registers */
    406. 

  406. 

  407. #define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
    408. 

  408. #define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
    409. 

  409. #define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
    410. 

  410. #define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
    411. 

  411. #define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
    412. 

  412. 

  413. /* USB Channel 5 Config Registers */
    414. 

  414. 

  415. #define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
    416. 

  416. #define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
    417. 

  417. #define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
    418. 

  418. #define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
    419. 

  419. #define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
    420. 

  420. 

  421. /* USB Channel 6 Config Registers */
    422. 

  422. 

  423. #define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
    424. 

  424. #define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
    425. 

  425. #define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
    426. 

  426. #define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
    427. 

  427. #define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
    428. 

  428. 

  429. /* USB Channel 7 Config Registers */
    430. 

  430. 

  431. #define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
    432. 

  432. #define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
    433. 

  433. #define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
    434. 

  434. #define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
    435. 

  435. #define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
    436. 

  436. 

  437. /* Keypad Registers */
    438. 

  438. 

  439. #define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
    440. 

  440. #define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
    441. 

  441. #define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
    442. 

  442. #define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
    443. 

  443. #define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
    444. 

  444. #define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
    445. 

  445. 

  446. /* Pixel Compositor (PIXC) Registers */
    447. 

  447. 

  448. #define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
    449. 

  449. #define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
    450. 

  450. #define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
    451. 

  451. #define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
    452. 

  452. #define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
    453. 

  453. #define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
    454. 

  454. #define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
    455. 

  455. #define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
    456. 

  456. #define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
    457. 

  457. #define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
    458. 

  458. #define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
    459. 

  459. #define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
    460. 

  460. #define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
    461. 

  461. #define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
    462. 

  462. #define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
    463. 

  463. #define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
    464. 

  464. #define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
    465. 

  465. #define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
    466. 

  466. #define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
    467. 

  467. 

  468. /* Handshake MDMA 0 Registers */
    469. 

  469. 

  470. #define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
    471. 

  471. #define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
    472. 

  472. #define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
    473. 

  473. #define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshold Register */
    474. 

  474. #define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
    475. 

  475. #define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
    476. 

  476. #define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
    477. 

  477. 

  478. /* Handshake MDMA 1 Registers */
    479. 

  479. 

  480. #define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
    481. 

  481. #define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
    482. 

  482. #define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
    483. 

  483. #define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshold Register */
    484. 

  484. #define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
    485. 

  485. #define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
    486. 

  486. #define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
    487. 

  487. 

  488. 

  489. /* ********************************************************** */
    490. 

  490. /*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
    491. 

  491. /*     and MULTI BIT READ MACROS                              */
    492. 

  492. /* ********************************************************** */
    493. 

  493. 

  494. /* Bit masks for PIXC_CTL */
    495. 

  495. 

  496. #define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
    497. 

  497. #define                  OVR_A_EN  0x2        /* Overlay A Enable */
    498. 

  498. #define                  OVR_B_EN  0x4        /* Overlay B Enable */
    499. 

  499. #define                  IMG_FORM  0x8        /* Image Data Format */
    500. 

  500. #define                  OVR_FORM  0x10       /* Overlay Data Format */
    501. 

  501. #define                  OUT_FORM  0x20       /* Output Data Format */
    502. 

  502. #define                   UDS_MOD  0x40       /* Resampling Mode */
    503. 

  503. #define                     TC_EN  0x80       /* Transparent Color Enable */
    504. 

  504. #define                  IMG_STAT  0x300      /* Image FIFO Status */
    505. 

  505. #define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
    506. 

  506. #define                    WM_LVL  0x3000     /* FIFO Watermark Level */
    507. 

  507. 

  508. /* Bit masks for PIXC_AHSTART */
    509. 

  509. 

  510. #define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
    511. 

  511. 

  512. /* Bit masks for PIXC_AHEND */
    513. 

  513. 

  514. #define                    A_HEND  0xfff      /* Horizontal End Coordinates */
    515. 

  515. 

  516. /* Bit masks for PIXC_AVSTART */
    517. 

  517. 

  518. #define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
    519. 

  519. 

  520. /* Bit masks for PIXC_AVEND */
    521. 

  521. 

  522. #define                    A_VEND  0x3ff      /* Vertical End Coordinates */
    523. 

  523. 

  524. /* Bit masks for PIXC_ATRANSP */
    525. 

  525. 

  526. #define                  A_TRANSP  0xf        /* Transparency Value */
    527. 

  527. 

  528. /* Bit masks for PIXC_BHSTART */
    529. 

  529. 

  530. #define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
    531. 

  531. 

  532. /* Bit masks for PIXC_BHEND */
    533. 

  533. 

  534. #define                    B_HEND  0xfff      /* Horizontal End Coordinates */
    535. 

  535. 

  536. /* Bit masks for PIXC_BVSTART */
    537. 

  537. 

  538. #define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
    539. 

  539. 

  540. /* Bit masks for PIXC_BVEND */
    541. 

  541. 

  542. #define                    B_VEND  0x3ff      /* Vertical End Coordinates */
    543. 

  543. 

  544. /* Bit masks for PIXC_BTRANSP */
    545. 

  545. 

  546. #define                  B_TRANSP  0xf        /* Transparency Value */
    547. 

  547. 

  548. /* Bit masks for PIXC_INTRSTAT */
    549. 

  549. 

  550. #define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
    551. 

  551. #define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
    552. 

  552. #define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
    553. 

  553. #define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
    554. 

  554. 

  555. /* Bit masks for PIXC_RYCON */
    556. 

  556. 

  557. #define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
    558. 

  558. #define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
    559. 

  559. #define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
    560. 

  560. #define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
    561. 

  561. 

  562. /* Bit masks for PIXC_GUCON */
    563. 

  563. 

  564. #define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
    565. 

  565. #define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
    566. 

  566. #define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
    567. 

  567. #define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
    568. 

  568. 

  569. /* Bit masks for PIXC_BVCON */
    570. 

  570. 

  571. #define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
    572. 

  572. #define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
    573. 

  573. #define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
    574. 

  574. #define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
    575. 

  575. 

  576. /* Bit masks for PIXC_CCBIAS */
    577. 

  577. 

  578. #define                       A14  0x3ff      /* A14 in the Bias Vector */
    579. 

  579. #define                       A24  0xffc00    /* A24 in the Bias Vector */
    580. 

  580. #define                       A34  0x3ff00000 /* A34 in the Bias Vector */
    581. 

  581. 

  582. /* Bit masks for PIXC_TC */
    583. 

  583. 

  584. #define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
    585. 

  585. #define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
    586. 

  586. #define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
    587. 

  587. 

  588. /* Bit masks for HOST_CONTROL */
    589. 

  589. 

  590. #define                   HOST_EN  0x1        /* Host Enable */
    591. 

  591. #define                  HOST_END  0x2        /* Host Endianess */
    592. 

  592. #define                 DATA_SIZE  0x4        /* Data Size */
    593. 

  593. #define                  HOST_RST  0x8        /* Host Reset */
    594. 

  594. #define                  HRDY_OVR  0x20       /* Host Ready Override */
    595. 

  595. #define                  INT_MODE  0x40       /* Interrupt Mode */
    596. 

  596. #define                     BT_EN  0x80       /* Bus Timeout Enable */
    597. 

  597. #define                       EHW  0x100      /* Enable Host Write */
    598. 

  598. #define                       EHR  0x200      /* Enable Host Read */
    599. 

  599. #define                       BDR  0x400      /* Burst DMA Requests */
    600. 

  600. 

  601. /* Bit masks for HOST_STATUS */
    602. 

  602. 

  603. #define                 DMA_READY  0x1        /* DMA Ready */
    604. 

  604. #define                  FIFOFULL  0x2        /* FIFO Full */
    605. 

  605. #define                 FIFOEMPTY  0x4        /* FIFO Empty */
    606. 

  606. #define              DMA_COMPLETE  0x8        /* DMA Complete */
    607. 

  607. #define                      HSHK  0x10       /* Host Handshake */
    608. 

  608. #define                 HSTIMEOUT  0x20       /* Host Timeout */
    609. 

  609. #define                      HIRQ  0x40       /* Host Interrupt Request */
    610. 

  610. #define                ALLOW_CNFG  0x80       /* Allow New Configuration */
    611. 

  611. #define                   DMA_DIR  0x100      /* DMA Direction */
    612. 

  612. #define                       BTE  0x200      /* Bus Timeout Enabled */
    613. 

  613. 

  614. /* Bit masks for HOST_TIMEOUT */
    615. 

  615. 

  616. #define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
    617. 

  617. 

  618. /* Bit masks for KPAD_CTL */
    619. 

  619. 

  620. #define                   KPAD_EN  0x1        /* Keypad Enable */
    621. 

  621. #define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
    622. 

  622. #define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
    623. 

  623. #define                KPAD_COLEN  0xe000     /* Column Enable Width */
    624. 

  624. 

  625. /* Bit masks for KPAD_PRESCALE */
    626. 

  626. 

  627. #define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
    628. 

  628. 

  629. /* Bit masks for KPAD_MSEL */
    630. 

  630. 

  631. #define                DBON_SCALE  0xff       /* Debounce Scale Value */
    632. 

  632. #define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
    633. 

  633. 

  634. /* Bit masks for KPAD_ROWCOL */
    635. 

  635. 

  636. #define                  KPAD_ROW  0xff       /* Rows Pressed */
    637. 

  637. #define                  KPAD_COL  0xff00     /* Columns Pressed */
    638. 

  638. 

  639. /* Bit masks for KPAD_STAT */
    640. 

  640. 

  641. #define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
    642. 

  642. #define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
    643. 

  643. #define              KPAD_PRESSED  0x8        /* Key press current status */
    644. 

  644. 

  645. /* Bit masks for KPAD_SOFTEVAL */
    646. 

  646. 

  647. #define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
    648. 

  648. 

  649. /* Bit masks for SDH_COMMAND */
    650. 

  650. 

  651. #define                   CMD_IDX  0x3f       /* Command Index */
    652. 

  652. #define                   CMD_RSP  0x40       /* Response */
    653. 

  653. #define                 CMD_L_RSP  0x80       /* Long Response */
    654. 

  654. #define                 CMD_INT_E  0x100      /* Command Interrupt */
    655. 

  655. #define                CMD_PEND_E  0x200      /* Command Pending */
    656. 

  656. #define                     CMD_E  0x400      /* Command Enable */
    657. 

  657. 

  658. /* Bit masks for SDH_PWR_CTL */
    659. 

  659. 

  660. #define                    PWR_ON  0x3        /* Power On */
    661. 

  661. #if 0
    662. 

  662. #define                       TBD  0x3c       /* TBD */
    663. 

  663. #endif
    664. 

  664. #define                 SD_CMD_OD  0x40       /* Open Drain Output */
    665. 

  665. #define                   ROD_CTL  0x80       /* Rod Control */
    666. 

  666. 

  667. /* Bit masks for SDH_CLK_CTL */
    668. 

  668. 

  669. #define                    CLKDIV  0xff       /* MC_CLK Divisor */
    670. 

  670. #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
    671. 

  671. #define                  PWR_SV_E  0x200      /* Power Save Enable */
    672. 

  672. #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
    673. 

  673. #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
    674. 

  674. 

  675. /* Bit masks for SDH_RESP_CMD */
    676. 

  676. 

  677. #define                  RESP_CMD  0x3f       /* Response Command */
    678. 

  678. 

  679. /* Bit masks for SDH_DATA_CTL */
    680. 

  680. 

  681. #define                     DTX_E  0x1        /* Data Transfer Enable */
    682. 

  682. #define                   DTX_DIR  0x2        /* Data Transfer Direction */
    683. 

  683. #define                  DTX_MODE  0x4        /* Data Transfer Mode */
    684. 

  684. #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
    685. 

  685. #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
    686. 

  686. 

  687. /* Bit masks for SDH_STATUS */
    688. 

  688. 

  689. #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
    690. 

  690. #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
    691. 

  691. #define               CMD_TIME_OUT  0x4        /* CMD Time Out */
    692. 

  692. #define               DAT_TIME_OUT  0x8        /* Data Time Out */
    693. 

  693. #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
    694. 

  694. #define                RX_OVERRUN  0x20       /* Receive Overrun */
    695. 

  695. #define              CMD_RESP_END  0x40       /* CMD Response End */
    696. 

  696. #define                  CMD_SENT  0x80       /* CMD Sent */
    697. 

  697. #define                   DAT_END  0x100      /* Data End */
    698. 

  698. #define             START_BIT_ERR  0x200      /* Start Bit Error */
    699. 

  699. #define               DAT_BLK_END  0x400      /* Data Block End */
    700. 

  700. #define                   CMD_ACT  0x800      /* CMD Active */
    701. 

  701. #define                    TX_ACT  0x1000     /* Transmit Active */
    702. 

  702. #define                    RX_ACT  0x2000     /* Receive Active */
    703. 

  703. #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
    704. 

  704. #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
    705. 

  705. #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
    706. 

  706. #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
    707. 

  707. #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
    708. 

  708. #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
    709. 

  709. #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
    710. 

  710. #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
    711. 

  711. 

  712. /* Bit masks for SDH_STATUS_CLR */
    713. 

  713. 

  714. #define         CMD_CRC_FAIL_STAT  0x1…
    715.