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/arch/blackfin/include/asm/mem_init.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 297 lines | 259 code | 22 blank | 16 comment | 27 complexity | 33c348749269f3890140d5063973267b MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
  3 *
  4 * Copyright 2004-2008 Analog Devices Inc.
  5 *
  6 * Licensed under the GPL-2 or later.
  7 */
  8
  9#if defined(EBIU_SDGCTL)
 10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
 11    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
 12    defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
 13    defined(CONFIG_MEM_GENERIC_BOARD) || \
 14    defined(CONFIG_MEM_MT48LC32M8A2_75) || \
 15    defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
 16    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
 17    defined(CONFIG_MEM_MT48LC32M8A2_75)
 18#if (CONFIG_SCLK_HZ > 119402985)
 19#define SDRAM_tRP       TRP_2
 20#define SDRAM_tRP_num   2
 21#define SDRAM_tRAS      TRAS_7
 22#define SDRAM_tRAS_num  7
 23#define SDRAM_tRCD      TRCD_2
 24#define SDRAM_tWR       TWR_2
 25#endif
 26#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
 27#define SDRAM_tRP       TRP_2
 28#define SDRAM_tRP_num   2
 29#define SDRAM_tRAS      TRAS_6
 30#define SDRAM_tRAS_num  6
 31#define SDRAM_tRCD      TRCD_2
 32#define SDRAM_tWR       TWR_2
 33#endif
 34#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
 35#define SDRAM_tRP       TRP_2
 36#define SDRAM_tRP_num   2
 37#define SDRAM_tRAS      TRAS_5
 38#define SDRAM_tRAS_num  5
 39#define SDRAM_tRCD      TRCD_2
 40#define SDRAM_tWR       TWR_2
 41#endif
 42#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
 43#define SDRAM_tRP       TRP_2
 44#define SDRAM_tRP_num   2
 45#define SDRAM_tRAS      TRAS_4
 46#define SDRAM_tRAS_num  4
 47#define SDRAM_tRCD      TRCD_2
 48#define SDRAM_tWR       TWR_2
 49#endif
 50#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
 51#define SDRAM_tRP       TRP_2
 52#define SDRAM_tRP_num   2
 53#define SDRAM_tRAS      TRAS_3
 54#define SDRAM_tRAS_num  3
 55#define SDRAM_tRCD      TRCD_2
 56#define SDRAM_tWR       TWR_2
 57#endif
 58#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
 59#define SDRAM_tRP       TRP_1
 60#define SDRAM_tRP_num   1
 61#define SDRAM_tRAS      TRAS_4
 62#define SDRAM_tRAS_num  4
 63#define SDRAM_tRCD      TRCD_1
 64#define SDRAM_tWR       TWR_2
 65#endif
 66#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
 67#define SDRAM_tRP       TRP_1
 68#define SDRAM_tRP_num   1
 69#define SDRAM_tRAS      TRAS_3
 70#define SDRAM_tRAS_num  3
 71#define SDRAM_tRCD      TRCD_1
 72#define SDRAM_tWR       TWR_2
 73#endif
 74#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
 75#define SDRAM_tRP       TRP_1
 76#define SDRAM_tRP_num   1
 77#define SDRAM_tRAS      TRAS_2
 78#define SDRAM_tRAS_num  2
 79#define SDRAM_tRCD      TRCD_1
 80#define SDRAM_tWR       TWR_2
 81#endif
 82#if (CONFIG_SCLK_HZ <= 29850746)
 83#define SDRAM_tRP       TRP_1
 84#define SDRAM_tRP_num   1
 85#define SDRAM_tRAS      TRAS_1
 86#define SDRAM_tRAS_num  1
 87#define SDRAM_tRCD      TRCD_1
 88#define SDRAM_tWR       TWR_2
 89#endif
 90#endif
 91
 92/*
 93 * The BF526-EZ-Board changed SDRAM chips between revisions,
 94 * so we use below timings to accommodate both.
 95 */
 96#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
 97#if (CONFIG_SCLK_HZ > 119402985)
 98#define SDRAM_tRP       TRP_2
 99#define SDRAM_tRP_num   2
100#define SDRAM_tRAS      TRAS_8
101#define SDRAM_tRAS_num  8
102#define SDRAM_tRCD      TRCD_2
103#define SDRAM_tWR       TWR_2
104#endif
105#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
106#define SDRAM_tRP       TRP_2
107#define SDRAM_tRP_num   2
108#define SDRAM_tRAS      TRAS_7
109#define SDRAM_tRAS_num  7
110#define SDRAM_tRCD      TRCD_2
111#define SDRAM_tWR       TWR_2
112#endif
113#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
114#define SDRAM_tRP       TRP_2
115#define SDRAM_tRP_num   2
116#define SDRAM_tRAS      TRAS_6
117#define SDRAM_tRAS_num  6
118#define SDRAM_tRCD      TRCD_2
119#define SDRAM_tWR       TWR_2
120#endif
121#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
122#define SDRAM_tRP       TRP_2
123#define SDRAM_tRP_num   2
124#define SDRAM_tRAS      TRAS_5
125#define SDRAM_tRAS_num  5
126#define SDRAM_tRCD      TRCD_2
127#define SDRAM_tWR       TWR_2
128#endif
129#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
130#define SDRAM_tRP       TRP_2
131#define SDRAM_tRP_num   2
132#define SDRAM_tRAS      TRAS_4
133#define SDRAM_tRAS_num  4
134#define SDRAM_tRCD      TRCD_2
135#define SDRAM_tWR       TWR_2
136#endif
137#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
138#define SDRAM_tRP       TRP_2
139#define SDRAM_tRP_num   2
140#define SDRAM_tRAS      TRAS_4
141#define SDRAM_tRAS_num  4
142#define SDRAM_tRCD      TRCD_1
143#define SDRAM_tWR       TWR_2
144#endif
145#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
146#define SDRAM_tRP       TRP_2
147#define SDRAM_tRP_num   2
148#define SDRAM_tRAS      TRAS_3
149#define SDRAM_tRAS_num  3
150#define SDRAM_tRCD      TRCD_1
151#define SDRAM_tWR       TWR_2
152#endif
153#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
154#define SDRAM_tRP       TRP_1
155#define SDRAM_tRP_num   1
156#define SDRAM_tRAS      TRAS_3
157#define SDRAM_tRAS_num  3
158#define SDRAM_tRCD      TRCD_1
159#define SDRAM_tWR       TWR_2
160#endif
161#if (CONFIG_SCLK_HZ <= 29850746)
162#define SDRAM_tRP       TRP_1
163#define SDRAM_tRP_num   1
164#define SDRAM_tRAS      TRAS_2
165#define SDRAM_tRAS_num  2
166#define SDRAM_tRCD      TRCD_1
167#define SDRAM_tWR       TWR_2
168#endif
169#endif
170
171#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
172    defined(CONFIG_MEM_MT48LC8M32B2B5_7)
173  /*SDRAM INFORMATION: */
174#define SDRAM_Tref  64		/* Refresh period in milliseconds   */
175#define SDRAM_NRA   4096	/* Number of row addresses in SDRAM */
176#define SDRAM_CL    CL_3
177#endif
178
179#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
180    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
181    defined(CONFIG_MEM_GENERIC_BOARD) || \
182    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
183    defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
184    defined(CONFIG_MEM_MT48LC32M8A2_75)
185  /*SDRAM INFORMATION: */
186#define SDRAM_Tref  64		/* Refresh period in milliseconds   */
187#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */
188#define SDRAM_CL    CL_3
189#endif
190
191#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
192  /*SDRAM INFORMATION: */
193#define SDRAM_Tref  64		/* Refresh period in milliseconds   */
194#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */
195#define SDRAM_CL    CL_2
196#endif
197
198
199#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
200/* Equation from section 17 (p17-46) of BF533 HRM */
201#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
202
203/* Enable SCLK Out */
204#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
205#else
206#define mem_SDRRC 	CONFIG_MEM_SDRRC
207#define mem_SDGCTL	CONFIG_MEM_SDGCTL
208#endif
209#endif
210
211
212#if defined(EBIU_DDRCTL0)
213#define MIN_DDR_SCLK(x)	(x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
214#define MAX_DDR_SCLK(x)	(x*(CONFIG_SCLK_HZ/1000/1000)/1000)
215#define DDR_CLK_HZ(x)	(1000*1000*1000/x)
216
217#if defined(CONFIG_MEM_MT46V32M16_6T)
218#define DDR_SIZE	DEVSZ_512
219#define DDR_WIDTH	DEVWD_16
220#define DDR_MAX_tCK	13
221
222#define DDR_tRC		DDR_TRC(MIN_DDR_SCLK(60))
223#define DDR_tRAS	DDR_TRAS(MIN_DDR_SCLK(42))
224#define DDR_tRP		DDR_TRP(MIN_DDR_SCLK(15))
225#define DDR_tRFC	DDR_TRFC(MIN_DDR_SCLK(72))
226#define DDR_tREFI	DDR_TREFI(MAX_DDR_SCLK(7800))
227
228#define DDR_tRCD	DDR_TRCD(MIN_DDR_SCLK(15))
229#define DDR_tWTR	DDR_TWTR(1)
230#define DDR_tMRD	DDR_TMRD(MIN_DDR_SCLK(12))
231#define DDR_tWR		DDR_TWR(MIN_DDR_SCLK(15))
232#endif
233
234#if defined(CONFIG_MEM_MT46V32M16_5B)
235#define DDR_SIZE	DEVSZ_512
236#define DDR_WIDTH	DEVWD_16
237#define DDR_MAX_tCK	13
238
239#define DDR_tRC		DDR_TRC(MIN_DDR_SCLK(55))
240#define DDR_tRAS	DDR_TRAS(MIN_DDR_SCLK(40))
241#define DDR_tRP		DDR_TRP(MIN_DDR_SCLK(15))
242#define DDR_tRFC	DDR_TRFC(MIN_DDR_SCLK(70))
243#define DDR_tREFI	DDR_TREFI(MAX_DDR_SCLK(7800))
244
245#define DDR_tRCD	DDR_TRCD(MIN_DDR_SCLK(15))
246#define DDR_tWTR	DDR_TWTR(2)
247#define DDR_tMRD	DDR_TMRD(MIN_DDR_SCLK(10))
248#define DDR_tWR		DDR_TWR(MIN_DDR_SCLK(15))
249#endif
250
251#if defined(CONFIG_MEM_GENERIC_BOARD)
252#define DDR_SIZE	DEVSZ_512
253#define DDR_WIDTH	DEVWD_16
254#define DDR_MAX_tCK	13
255
256#define DDR_tRCD	DDR_TRCD(3)
257#define DDR_tWTR	DDR_TWTR(2)
258#define DDR_tWR		DDR_TWR(2)
259#define DDR_tMRD	DDR_TMRD(2)
260#define DDR_tRP		DDR_TRP(3)
261#define DDR_tRAS	DDR_TRAS(7)
262#define DDR_tRC		DDR_TRC(10)
263#define DDR_tRFC	DDR_TRFC(12)
264#define DDR_tREFI	DDR_TREFI(1288)
265#endif
266
267#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
268# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
269#elif(CONFIG_SCLK_HZ <= 133333333)
270# define	DDR_CL		CL_2
271#else
272# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
273#endif
274
275#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
276#define mem_DDRCTL0	(DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
277#define mem_DDRCTL1	(DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
278			| DDR_tMRD | DDR_tWR | DDR_tRCD)
279#define mem_DDRCTL2	DDR_CL
280#else
281#define mem_DDRCTL0	CONFIG_MEM_DDRCTL0
282#define mem_DDRCTL1	CONFIG_MEM_DDRCTL1
283#define mem_DDRCTL2	CONFIG_MEM_DDRCTL2
284#endif
285#endif
286
287#if defined CONFIG_CLKIN_HALF
288#define CLKIN_HALF       1
289#else
290#define CLKIN_HALF       0
291#endif
292
293#if defined CONFIG_PLL_BYPASS
294#define PLL_BYPASS      1
295#else
296#define PLL_BYPASS       0
297#endif