/arch/blackfin/include/asm/mem_init.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35 · C++ Header · 297 lines · 259 code · 22 blank · 16 comment · 27 complexity · 33c348749269f3890140d5063973267b MD5 · raw file 

    

  1. /*
    2. 

  2.  * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
    3. 

  3.  *
    4. 

  4.  * Copyright 2004-2008 Analog Devices Inc.
    5. 

  5.  *
    6. 

  6.  * Licensed under the GPL-2 or later.
    7. 

  7.  */
    8. 

  8. 

  9. #if defined(EBIU_SDGCTL)
    10. 

  10. #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
    11. 

  11.     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
    12. 

  12.     defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
    13. 

  13.     defined(CONFIG_MEM_GENERIC_BOARD) || \
    14. 

  14.     defined(CONFIG_MEM_MT48LC32M8A2_75) || \
    15. 

  15.     defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
    16. 

  16.     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
    17. 

  17.     defined(CONFIG_MEM_MT48LC32M8A2_75)
    18. 

  18. #if (CONFIG_SCLK_HZ > 119402985)
    19. 

  19. #define SDRAM_tRP       TRP_2
    20. 

  20. #define SDRAM_tRP_num   2
    21. 

  21. #define SDRAM_tRAS      TRAS_7
    22. 

  22. #define SDRAM_tRAS_num  7
    23. 

  23. #define SDRAM_tRCD      TRCD_2
    24. 

  24. #define SDRAM_tWR       TWR_2
    25. 

  25. #endif
    26. 

  26. #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
    27. 

  27. #define SDRAM_tRP       TRP_2
    28. 

  28. #define SDRAM_tRP_num   2
    29. 

  29. #define SDRAM_tRAS      TRAS_6
    30. 

  30. #define SDRAM_tRAS_num  6
    31. 

  31. #define SDRAM_tRCD      TRCD_2
    32. 

  32. #define SDRAM_tWR       TWR_2
    33. 

  33. #endif
    34. 

  34. #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
    35. 

  35. #define SDRAM_tRP       TRP_2
    36. 

  36. #define SDRAM_tRP_num   2
    37. 

  37. #define SDRAM_tRAS      TRAS_5
    38. 

  38. #define SDRAM_tRAS_num  5
    39. 

  39. #define SDRAM_tRCD      TRCD_2
    40. 

  40. #define SDRAM_tWR       TWR_2
    41. 

  41. #endif
    42. 

  42. #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
    43. 

  43. #define SDRAM_tRP       TRP_2
    44. 

  44. #define SDRAM_tRP_num   2
    45. 

  45. #define SDRAM_tRAS      TRAS_4
    46. 

  46. #define SDRAM_tRAS_num  4
    47. 

  47. #define SDRAM_tRCD      TRCD_2
    48. 

  48. #define SDRAM_tWR       TWR_2
    49. 

  49. #endif
    50. 

  50. #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
    51. 

  51. #define SDRAM_tRP       TRP_2
    52. 

  52. #define SDRAM_tRP_num   2
    53. 

  53. #define SDRAM_tRAS      TRAS_3
    54. 

  54. #define SDRAM_tRAS_num  3
    55. 

  55. #define SDRAM_tRCD      TRCD_2
    56. 

  56. #define SDRAM_tWR       TWR_2
    57. 

  57. #endif
    58. 

  58. #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
    59. 

  59. #define SDRAM_tRP       TRP_1
    60. 

  60. #define SDRAM_tRP_num   1
    61. 

  61. #define SDRAM_tRAS      TRAS_4
    62. 

  62. #define SDRAM_tRAS_num  4
    63. 

  63. #define SDRAM_tRCD      TRCD_1
    64. 

  64. #define SDRAM_tWR       TWR_2
    65. 

  65. #endif
    66. 

  66. #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
    67. 

  67. #define SDRAM_tRP       TRP_1
    68. 

  68. #define SDRAM_tRP_num   1
    69. 

  69. #define SDRAM_tRAS      TRAS_3
    70. 

  70. #define SDRAM_tRAS_num  3
    71. 

  71. #define SDRAM_tRCD      TRCD_1
    72. 

  72. #define SDRAM_tWR       TWR_2
    73. 

  73. #endif
    74. 

  74. #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
    75. 

  75. #define SDRAM_tRP       TRP_1
    76. 

  76. #define SDRAM_tRP_num   1
    77. 

  77. #define SDRAM_tRAS      TRAS_2
    78. 

  78. #define SDRAM_tRAS_num  2
    79. 

  79. #define SDRAM_tRCD      TRCD_1
    80. 

  80. #define SDRAM_tWR       TWR_2
    81. 

  81. #endif
    82. 

  82. #if (CONFIG_SCLK_HZ <= 29850746)
    83. 

  83. #define SDRAM_tRP       TRP_1
    84. 

  84. #define SDRAM_tRP_num   1
    85. 

  85. #define SDRAM_tRAS      TRAS_1
    86. 

  86. #define SDRAM_tRAS_num  1
    87. 

  87. #define SDRAM_tRCD      TRCD_1
    88. 

  88. #define SDRAM_tWR       TWR_2
    89. 

  89. #endif
    90. 

  90. #endif
    91. 

  91. 

  92. /*
    93. 

  93.  * The BF526-EZ-Board changed SDRAM chips between revisions,
    94. 

  94.  * so we use below timings to accommodate both.
    95. 

  95.  */
    96. 

  96. #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
    97. 

  97. #if (CONFIG_SCLK_HZ > 119402985)
    98. 

  98. #define SDRAM_tRP       TRP_2
    99. 

  99. #define SDRAM_tRP_num   2
    100. 

  100. #define SDRAM_tRAS      TRAS_8
    101. 

  101. #define SDRAM_tRAS_num  8
    102. 

  102. #define SDRAM_tRCD      TRCD_2
    103. 

  103. #define SDRAM_tWR       TWR_2
    104. 

  104. #endif
    105. 

  105. #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
    106. 

  106. #define SDRAM_tRP       TRP_2
    107. 

  107. #define SDRAM_tRP_num   2
    108. 

  108. #define SDRAM_tRAS      TRAS_7
    109. 

  109. #define SDRAM_tRAS_num  7
    110. 

  110. #define SDRAM_tRCD      TRCD_2
    111. 

  111. #define SDRAM_tWR       TWR_2
    112. 

  112. #endif
    113. 

  113. #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
    114. 

  114. #define SDRAM_tRP       TRP_2
    115. 

  115. #define SDRAM_tRP_num   2
    116. 

  116. #define SDRAM_tRAS      TRAS_6
    117. 

  117. #define SDRAM_tRAS_num  6
    118. 

  118. #define SDRAM_tRCD      TRCD_2
    119. 

  119. #define SDRAM_tWR       TWR_2
    120. 

  120. #endif
    121. 

  121. #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
    122. 

  122. #define SDRAM_tRP       TRP_2
    123. 

  123. #define SDRAM_tRP_num   2
    124. 

  124. #define SDRAM_tRAS      TRAS_5
    125. 

  125. #define SDRAM_tRAS_num  5
    126. 

  126. #define SDRAM_tRCD      TRCD_2
    127. 

  127. #define SDRAM_tWR       TWR_2
    128. 

  128. #endif
    129. 

  129. #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
    130. 

  130. #define SDRAM_tRP       TRP_2
    131. 

  131. #define SDRAM_tRP_num   2
    132. 

  132. #define SDRAM_tRAS      TRAS_4
    133. 

  133. #define SDRAM_tRAS_num  4
    134. 

  134. #define SDRAM_tRCD      TRCD_2
    135. 

  135. #define SDRAM_tWR       TWR_2
    136. 

  136. #endif
    137. 

  137. #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
    138. 

  138. #define SDRAM_tRP       TRP_2
    139. 

  139. #define SDRAM_tRP_num   2
    140. 

  140. #define SDRAM_tRAS      TRAS_4
    141. 

  141. #define SDRAM_tRAS_num  4
    142. 

  142. #define SDRAM_tRCD      TRCD_1
    143. 

  143. #define SDRAM_tWR       TWR_2
    144. 

  144. #endif
    145. 

  145. #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
    146. 

  146. #define SDRAM_tRP       TRP_2
    147. 

  147. #define SDRAM_tRP_num   2
    148. 

  148. #define SDRAM_tRAS      TRAS_3
    149. 

  149. #define SDRAM_tRAS_num  3
    150. 

  150. #define SDRAM_tRCD      TRCD_1
    151. 

  151. #define SDRAM_tWR       TWR_2
    152. 

  152. #endif
    153. 

  153. #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
    154. 

  154. #define SDRAM_tRP       TRP_1
    155. 

  155. #define SDRAM_tRP_num   1
    156. 

  156. #define SDRAM_tRAS      TRAS_3
    157. 

  157. #define SDRAM_tRAS_num  3
    158. 

  158. #define SDRAM_tRCD      TRCD_1
    159. 

  159. #define SDRAM_tWR       TWR_2
    160. 

  160. #endif
    161. 

  161. #if (CONFIG_SCLK_HZ <= 29850746)
    162. 

  162. #define SDRAM_tRP       TRP_1
    163. 

  163. #define SDRAM_tRP_num   1
    164. 

  164. #define SDRAM_tRAS      TRAS_2
    165. 

  165. #define SDRAM_tRAS_num  2
    166. 

  166. #define SDRAM_tRCD      TRCD_1
    167. 

  167. #define SDRAM_tWR       TWR_2
    168. 

  168. #endif
    169. 

  169. #endif
    170. 

  170. 

  171. #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
    172. 

  172.     defined(CONFIG_MEM_MT48LC8M32B2B5_7)
    173. 

  173.   /*SDRAM INFORMATION: */
    174. 

  174. #define SDRAM_Tref  64		/* Refresh period in milliseconds   */
    175. 

  175. #define SDRAM_NRA   4096	/* Number of row addresses in SDRAM */
    176. 

  176. #define SDRAM_CL    CL_3
    177. 

  177. #endif
    178. 

  178. 

  179. #if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
    180. 

  180.     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
    181. 

  181.     defined(CONFIG_MEM_GENERIC_BOARD) || \
    182. 

  182.     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
    183. 

  183.     defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
    184. 

  184.     defined(CONFIG_MEM_MT48LC32M8A2_75)
    185. 

  185.   /*SDRAM INFORMATION: */
    186. 

  186. #define SDRAM_Tref  64		/* Refresh period in milliseconds   */
    187. 

  187. #define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */
    188. 

  188. #define SDRAM_CL    CL_3
    189. 

  189. #endif
    190. 

  190. 

  191. #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
    192. 

  192.   /*SDRAM INFORMATION: */
    193. 

  193. #define SDRAM_Tref  64		/* Refresh period in milliseconds   */
    194. 

  194. #define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */
    195. 

  195. #define SDRAM_CL    CL_2
    196. 

  196. #endif
    197. 

  197. 

  198. 

  199. #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
    200. 

  200. /* Equation from section 17 (p17-46) of BF533 HRM */
    201. 

  201. #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
    202. 

  202. 

  203. /* Enable SCLK Out */
    204. 

  204. #define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
    205. 

  205. #else
    206. 

  206. #define mem_SDRRC 	CONFIG_MEM_SDRRC
    207. 

  207. #define mem_SDGCTL	CONFIG_MEM_SDGCTL
    208. 

  208. #endif
    209. 

  209. #endif
    210. 

  210. 

  211. 

  212. #if defined(EBIU_DDRCTL0)
    213. 

  213. #define MIN_DDR_SCLK(x)	(x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
    214. 

  214. #define MAX_DDR_SCLK(x)	(x*(CONFIG_SCLK_HZ/1000/1000)/1000)
    215. 

  215. #define DDR_CLK_HZ(x)	(1000*1000*1000/x)
    216. 

  216. 

  217. #if defined(CONFIG_MEM_MT46V32M16_6T)
    218. 

  218. #define DDR_SIZE	DEVSZ_512
    219. 

  219. #define DDR_WIDTH	DEVWD_16
    220. 

  220. #define DDR_MAX_tCK	13
    221. 

  221. 

  222. #define DDR_tRC		DDR_TRC(MIN_DDR_SCLK(60))
    223. 

  223. #define DDR_tRAS	DDR_TRAS(MIN_DDR_SCLK(42))
    224. 

  224. #define DDR_tRP		DDR_TRP(MIN_DDR_SCLK(15))
    225. 

  225. #define DDR_tRFC	DDR_TRFC(MIN_DDR_SCLK(72))
    226. 

  226. #define DDR_tREFI	DDR_TREFI(MAX_DDR_SCLK(7800))
    227. 

  227. 

  228. #define DDR_tRCD	DDR_TRCD(MIN_DDR_SCLK(15))
    229. 

  229. #define DDR_tWTR	DDR_TWTR(1)
    230. 

  230. #define DDR_tMRD	DDR_TMRD(MIN_DDR_SCLK(12))
    231. 

  231. #define DDR_tWR		DDR_TWR(MIN_DDR_SCLK(15))
    232. 

  232. #endif
    233. 

  233. 

  234. #if defined(CONFIG_MEM_MT46V32M16_5B)
    235. 

  235. #define DDR_SIZE	DEVSZ_512
    236. 

  236. #define DDR_WIDTH	DEVWD_16
    237. 

  237. #define DDR_MAX_tCK	13
    238. 

  238. 

  239. #define DDR_tRC		DDR_TRC(MIN_DDR_SCLK(55))
    240. 

  240. #define DDR_tRAS	DDR_TRAS(MIN_DDR_SCLK(40))
    241. 

  241. #define DDR_tRP		DDR_TRP(MIN_DDR_SCLK(15))
    242. 

  242. #define DDR_tRFC	DDR_TRFC(MIN_DDR_SCLK(70))
    243. 

  243. #define DDR_tREFI	DDR_TREFI(MAX_DDR_SCLK(7800))
    244. 

  244. 

  245. #define DDR_tRCD	DDR_TRCD(MIN_DDR_SCLK(15))
    246. 

  246. #define DDR_tWTR	DDR_TWTR(2)
    247. 

  247. #define DDR_tMRD	DDR_TMRD(MIN_DDR_SCLK(10))
    248. 

  248. #define DDR_tWR		DDR_TWR(MIN_DDR_SCLK(15))
    249. 

  249. #endif
    250. 

  250. 

  251. #if defined(CONFIG_MEM_GENERIC_BOARD)
    252. 

  252. #define DDR_SIZE	DEVSZ_512
    253. 

  253. #define DDR_WIDTH	DEVWD_16
    254. 

  254. #define DDR_MAX_tCK	13
    255. 

  255. 

  256. #define DDR_tRCD	DDR_TRCD(3)
    257. 

  257. #define DDR_tWTR	DDR_TWTR(2)
    258. 

  258. #define DDR_tWR		DDR_TWR(2)
    259. 

  259. #define DDR_tMRD	DDR_TMRD(2)
    260. 

  260. #define DDR_tRP		DDR_TRP(3)
    261. 

  261. #define DDR_tRAS	DDR_TRAS(7)
    262. 

  262. #define DDR_tRC		DDR_TRC(10)
    263. 

  263. #define DDR_tRFC	DDR_TRFC(12)
    264. 

  264. #define DDR_tREFI	DDR_TREFI(1288)
    265. 

  265. #endif
    266. 

  266. 

  267. #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
    268. 

  268. # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
    269. 

  269. #elif(CONFIG_SCLK_HZ <= 133333333)
    270. 

  270. # define	DDR_CL		CL_2
    271. 

  271. #else
    272. 

  272. # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
    273. 

  273. #endif
    274. 

  274. 

  275. #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
    276. 

  276. #define mem_DDRCTL0	(DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
    277. 

  277. #define mem_DDRCTL1	(DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
    278. 

  278. 			| DDR_tMRD | DDR_tWR | DDR_tRCD)
    279. 

  279. #define mem_DDRCTL2	DDR_CL
    280. 

  280. #else
    281. 

  281. #define mem_DDRCTL0	CONFIG_MEM_DDRCTL0
    282. 

  282. #define mem_DDRCTL1	CONFIG_MEM_DDRCTL1
    283. 

  283. #define mem_DDRCTL2	CONFIG_MEM_DDRCTL2
    284. 

  284. #endif
    285. 

  285. #endif
    286. 

  286. 

  287. #if defined CONFIG_CLKIN_HALF
    288. 

  288. #define CLKIN_HALF       1
    289. 

  289. #else
    290. 

  290. #define CLKIN_HALF       0
    291. 

  291. #endif
    292. 

  292. 

  293. #if defined CONFIG_PLL_BYPASS
    294. 

  294. #define PLL_BYPASS      1
    295. 

  295. #else
    296. 

  296. #define PLL_BYPASS       0
    297. 

  297. #endif
    298.