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/arch/blackfin/mach-bf537/include/mach/irq.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 199 lines | 153 code | 18 blank | 28 comment | 0 complexity | e5edf4071d6d9849c108bba4a558b57a MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 * Copyright 2005-2008 Analog Devices Inc.
  3 *
  4 * Licensed under the GPL-2 or later
  5 */
  6
  7#ifndef _BF537_IRQ_H_
  8#define _BF537_IRQ_H_
  9
 10/*
 11 * Interrupt source definitions
 12 *            Event Source    Core Event Name
 13 * Core       Emulation               **
 14 * Events         (highest priority)  EMU         0
 15 *            Reset                   RST         1
 16 *            NMI                     NMI         2
 17 *            Exception               EVX         3
 18 *            Reserved                --          4
 19 *            Hardware Error          IVHW        5
 20 *            Core Timer              IVTMR       6
 21 *  .....
 22 *
 23 *            Softirq		      IVG14
 24 *            System Call    --
 25 *               (lowest priority)    IVG15
 26 */
 27
 28#define SYS_IRQS        39
 29#define NR_PERI_INTS    32
 30
 31/* The ABSTRACT IRQ definitions */
 32/** the first seven of the following are fixed, the rest you change if you need to **/
 33#define IRQ_EMU             0	/*Emulation */
 34#define IRQ_RST             1	/*reset */
 35#define IRQ_NMI             2	/*Non Maskable */
 36#define IRQ_EVX             3	/*Exception */
 37#define IRQ_UNUSED          4	/*- unused interrupt*/
 38#define IRQ_HWERR           5	/*Hardware Error */
 39#define IRQ_CORETMR         6	/*Core timer */
 40
 41#define IRQ_PLL_WAKEUP      7	/*PLL Wakeup Interrupt */
 42#define IRQ_DMA_ERROR       8	/*DMA Error (general) */
 43#define IRQ_GENERIC_ERROR   9	/*GENERIC Error Interrupt */
 44#define IRQ_RTC             10	/*RTC Interrupt */
 45#define IRQ_PPI             11	/*DMA0 Interrupt (PPI) */
 46#define IRQ_SPORT0_RX       12	/*DMA3 Interrupt (SPORT0 RX) */
 47#define IRQ_SPORT0_TX       13	/*DMA4 Interrupt (SPORT0 TX) */
 48#define IRQ_SPORT1_RX       14	/*DMA5 Interrupt (SPORT1 RX) */
 49#define IRQ_SPORT1_TX       15	/*DMA6 Interrupt (SPORT1 TX) */
 50#define IRQ_TWI             16	/*TWI Interrupt */
 51#define IRQ_SPI             17	/*DMA7 Interrupt (SPI) */
 52#define IRQ_UART0_RX        18	/*DMA8 Interrupt (UART0 RX) */
 53#define IRQ_UART0_TX        19	/*DMA9 Interrupt (UART0 TX) */
 54#define IRQ_UART1_RX        20	/*DMA10 Interrupt (UART1 RX) */
 55#define IRQ_UART1_TX        21	/*DMA11 Interrupt (UART1 TX) */
 56#define IRQ_CAN_RX          22	/*CAN Receive Interrupt */
 57#define IRQ_CAN_TX          23	/*CAN Transmit Interrupt */
 58#define IRQ_MAC_RX          24	/*DMA1 (Ethernet RX) Interrupt */
 59#define IRQ_MAC_TX          25	/*DMA2 (Ethernet TX) Interrupt */
 60#define IRQ_TIMER0            26	/*Timer 0 */
 61#define IRQ_TIMER1            27	/*Timer 1 */
 62#define IRQ_TIMER2            28	/*Timer 2 */
 63#define IRQ_TIMER3            29	/*Timer 3 */
 64#define IRQ_TIMER4            30	/*Timer 4 */
 65#define IRQ_TIMER5            31	/*Timer 5 */
 66#define IRQ_TIMER6            32	/*Timer 6 */
 67#define IRQ_TIMER7            33	/*Timer 7 */
 68#define IRQ_PROG_INTA       34	/* PF Ports F&G (PF15:0) Interrupt A */
 69#define IRQ_PORTG_INTB      35	/* PF Port G (PF15:0) Interrupt B */
 70#define IRQ_MEM_DMA0        36	/*(Memory DMA Stream 0) */
 71#define IRQ_MEM_DMA1        37	/*(Memory DMA Stream 1) */
 72#define IRQ_PROG_INTB	      38	/* PF Ports F (PF15:0) Interrupt B */
 73#define IRQ_WATCH           38	/*Watch Dog Timer */
 74
 75#define IRQ_PPI_ERROR       42	/*PPI Error Interrupt */
 76#define IRQ_CAN_ERROR       43	/*CAN Error Interrupt */
 77#define IRQ_MAC_ERROR       44	/*MAC Status/Error Interrupt */
 78#define IRQ_SPORT0_ERROR    45	/*SPORT0 Error Interrupt */
 79#define IRQ_SPORT1_ERROR    46	/*SPORT1 Error Interrupt */
 80#define IRQ_SPI_ERROR       47	/*SPI Error Interrupt */
 81#define IRQ_UART0_ERROR     48	/*UART Error Interrupt */
 82#define IRQ_UART1_ERROR     49	/*UART Error Interrupt */
 83
 84#define IRQ_PF0         50
 85#define IRQ_PF1         51
 86#define IRQ_PF2         52
 87#define IRQ_PF3         53
 88#define IRQ_PF4         54
 89#define IRQ_PF5         55
 90#define IRQ_PF6         56
 91#define IRQ_PF7         57
 92#define IRQ_PF8         58
 93#define IRQ_PF9         59
 94#define IRQ_PF10        60
 95#define IRQ_PF11        61
 96#define IRQ_PF12        62
 97#define IRQ_PF13        63
 98#define IRQ_PF14        64
 99#define IRQ_PF15        65
100
101#define IRQ_PG0         66
102#define IRQ_PG1         67
103#define IRQ_PG2         68
104#define IRQ_PG3         69
105#define IRQ_PG4         70
106#define IRQ_PG5         71
107#define IRQ_PG6         72
108#define IRQ_PG7         73
109#define IRQ_PG8         74
110#define IRQ_PG9         75
111#define IRQ_PG10        76
112#define IRQ_PG11        77
113#define IRQ_PG12        78
114#define IRQ_PG13        79
115#define IRQ_PG14        80
116#define IRQ_PG15        81
117
118#define IRQ_PH0         82
119#define IRQ_PH1         83
120#define IRQ_PH2         84
121#define IRQ_PH3         85
122#define IRQ_PH4         86
123#define IRQ_PH5         87
124#define IRQ_PH6         88
125#define IRQ_PH7         89
126#define IRQ_PH8         90
127#define IRQ_PH9         91
128#define IRQ_PH10        92
129#define IRQ_PH11        93
130#define IRQ_PH12        94
131#define IRQ_PH13        95
132#define IRQ_PH14        96
133#define IRQ_PH15        97
134
135#define GPIO_IRQ_BASE	IRQ_PF0
136
137#define IRQ_MAC_PHYINT		98 /* PHY_INT Interrupt */
138#define IRQ_MAC_MMCINT		99 /* MMC Counter Interrupt */
139#define IRQ_MAC_RXFSINT		100 /* RX Frame-Status Interrupt */
140#define IRQ_MAC_TXFSINT		101 /* TX Frame-Status Interrupt */
141#define IRQ_MAC_WAKEDET		102 /* Wake-Up Interrupt */
142#define IRQ_MAC_RXDMAERR	103 /* RX DMA Direction Error Interrupt */
143#define IRQ_MAC_TXDMAERR	104 /* TX DMA Direction Error Interrupt */
144#define IRQ_MAC_STMDONE		105 /* Station Mgt. Transfer Done Interrupt */
145
146#define NR_MACH_IRQS	(IRQ_MAC_STMDONE + 1)
147#define NR_IRQS		(NR_MACH_IRQS + NR_SPARE_IRQS)
148
149#define IVG7            7
150#define IVG8            8
151#define IVG9            9
152#define IVG10           10
153#define IVG11           11
154#define IVG12           12
155#define IVG13           13
156#define IVG14           14
157#define IVG15           15
158
159/* IAR0 BIT FIELDS*/
160#define IRQ_PLL_WAKEUP_POS  0
161#define IRQ_DMA_ERROR_POS   4
162#define IRQ_ERROR_POS       8
163#define IRQ_RTC_POS         12
164#define IRQ_PPI_POS         16
165#define IRQ_SPORT0_RX_POS   20
166#define IRQ_SPORT0_TX_POS   24
167#define IRQ_SPORT1_RX_POS   28
168
169/* IAR1 BIT FIELDS*/
170#define IRQ_SPORT1_TX_POS   0
171#define IRQ_TWI_POS         4
172#define IRQ_SPI_POS         8
173#define IRQ_UART0_RX_POS    12
174#define IRQ_UART0_TX_POS    16
175#define IRQ_UART1_RX_POS    20
176#define IRQ_UART1_TX_POS    24
177#define IRQ_CAN_RX_POS      28
178
179/* IAR2 BIT FIELDS*/
180#define IRQ_CAN_TX_POS      0
181#define IRQ_MAC_RX_POS      4
182#define IRQ_MAC_TX_POS      8
183#define IRQ_TIMER0_POS        12
184#define IRQ_TIMER1_POS        16
185#define IRQ_TIMER2_POS        20
186#define IRQ_TIMER3_POS        24
187#define IRQ_TIMER4_POS        28
188
189/* IAR3 BIT FIELDS*/
190#define IRQ_TIMER5_POS        0
191#define IRQ_TIMER6_POS        4
192#define IRQ_TIMER7_POS        8
193#define IRQ_PROG_INTA_POS   12
194#define IRQ_PORTG_INTB_POS   16
195#define IRQ_MEM_DMA0_POS    20
196#define IRQ_MEM_DMA1_POS    24
197#define IRQ_WATCH_POS       28
198
199#endif				/* _BF537_IRQ_H_ */