/arch/blackfin/mach-bf533/include/mach/irq.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35 · C++ Header · 150 lines · 88 code · 12 blank · 50 comment · 0 complexity · b8dc850cb2ef3ba73835129ad0a973c8 MD5 · raw file

  1. /*
  2. * Copyright 2005-2008 Analog Devices Inc.
  3. *
  4. * Licensed under the GPL-2 or later
  5. */
  6. #ifndef _BF533_IRQ_H_
  7. #define _BF533_IRQ_H_
  8. /*
  9. * Interrupt source definitions
  10. Event Source Core Event Name
  11. Core Emulation **
  12. Events (highest priority) EMU 0
  13. Reset RST 1
  14. NMI NMI 2
  15. Exception EVX 3
  16. Reserved -- 4
  17. Hardware Error IVHW 5
  18. Core Timer IVTMR 6 *
  19. PLL Wakeup Interrupt IVG7 7
  20. DMA Error (generic) IVG7 8
  21. PPI Error Interrupt IVG7 9
  22. SPORT0 Error Interrupt IVG7 10
  23. SPORT1 Error Interrupt IVG7 11
  24. SPI Error Interrupt IVG7 12
  25. UART Error Interrupt IVG7 13
  26. RTC Interrupt IVG8 14
  27. DMA0 Interrupt (PPI) IVG8 15
  28. DMA1 (SPORT0 RX) IVG9 16
  29. DMA2 (SPORT0 TX) IVG9 17
  30. DMA3 (SPORT1 RX) IVG9 18
  31. DMA4 (SPORT1 TX) IVG9 19
  32. DMA5 (PPI) IVG10 20
  33. DMA6 (UART RX) IVG10 21
  34. DMA7 (UART TX) IVG10 22
  35. Timer0 IVG11 23
  36. Timer1 IVG11 24
  37. Timer2 IVG11 25
  38. PF Interrupt A IVG12 26
  39. PF Interrupt B IVG12 27
  40. DMA8/9 Interrupt IVG13 28
  41. DMA10/11 Interrupt IVG13 29
  42. Watchdog Timer IVG13 30
  43. Softirq IVG14 31
  44. System Call --
  45. (lowest priority) IVG15 32 *
  46. */
  47. #define SYS_IRQS 31
  48. #define NR_PERI_INTS 24
  49. /* The ABSTRACT IRQ definitions */
  50. /** the first seven of the following are fixed, the rest you change if you need to **/
  51. #define IRQ_EMU 0 /*Emulation */
  52. #define IRQ_RST 1 /*reset */
  53. #define IRQ_NMI 2 /*Non Maskable */
  54. #define IRQ_EVX 3 /*Exception */
  55. #define IRQ_UNUSED 4 /*- unused interrupt*/
  56. #define IRQ_HWERR 5 /*Hardware Error */
  57. #define IRQ_CORETMR 6 /*Core timer */
  58. #define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
  59. #define IRQ_DMA_ERROR 8 /*DMA Error (general) */
  60. #define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
  61. #define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
  62. #define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
  63. #define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
  64. #define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
  65. #define IRQ_RTC 14 /*RTC Interrupt */
  66. #define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
  67. #define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
  68. #define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
  69. #define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
  70. #define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
  71. #define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
  72. #define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
  73. #define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
  74. #define IRQ_TIMER0 23 /*Timer 0 */
  75. #define IRQ_TIMER1 24 /*Timer 1 */
  76. #define IRQ_TIMER2 25 /*Timer 2 */
  77. #define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
  78. #define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
  79. #define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
  80. #define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
  81. #define IRQ_WATCH 30 /*Watch Dog Timer */
  82. #define IRQ_PF0 33
  83. #define IRQ_PF1 34
  84. #define IRQ_PF2 35
  85. #define IRQ_PF3 36
  86. #define IRQ_PF4 37
  87. #define IRQ_PF5 38
  88. #define IRQ_PF6 39
  89. #define IRQ_PF7 40
  90. #define IRQ_PF8 41
  91. #define IRQ_PF9 42
  92. #define IRQ_PF10 43
  93. #define IRQ_PF11 44
  94. #define IRQ_PF12 45
  95. #define IRQ_PF13 46
  96. #define IRQ_PF14 47
  97. #define IRQ_PF15 48
  98. #define GPIO_IRQ_BASE IRQ_PF0
  99. #define NR_MACH_IRQS (IRQ_PF15 + 1)
  100. #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
  101. #define IVG7 7
  102. #define IVG8 8
  103. #define IVG9 9
  104. #define IVG10 10
  105. #define IVG11 11
  106. #define IVG12 12
  107. #define IVG13 13
  108. #define IVG14 14
  109. #define IVG15 15
  110. /* IAR0 BIT FIELDS*/
  111. #define RTC_ERROR_POS 28
  112. #define UART_ERROR_POS 24
  113. #define SPORT1_ERROR_POS 20
  114. #define SPI_ERROR_POS 16
  115. #define SPORT0_ERROR_POS 12
  116. #define PPI_ERROR_POS 8
  117. #define DMA_ERROR_POS 4
  118. #define PLLWAKE_ERROR_POS 0
  119. /* IAR1 BIT FIELDS*/
  120. #define DMA7_UARTTX_POS 28
  121. #define DMA6_UARTRX_POS 24
  122. #define DMA5_SPI_POS 20
  123. #define DMA4_SPORT1TX_POS 16
  124. #define DMA3_SPORT1RX_POS 12
  125. #define DMA2_SPORT0TX_POS 8
  126. #define DMA1_SPORT0RX_POS 4
  127. #define DMA0_PPI_POS 0
  128. /* IAR2 BIT FIELDS*/
  129. #define WDTIMER_POS 28
  130. #define MEMDMA1_POS 24
  131. #define MEMDMA0_POS 20
  132. #define PFB_POS 16
  133. #define PFA_POS 12
  134. #define TIMER2_POS 8
  135. #define TIMER1_POS 4
  136. #define TIMER0_POS 0
  137. #endif /* _BF533_IRQ_H_ */