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/arch/arm/mach-at91/include/mach/at91sam9_smc.h

https://bitbucket.org/thekraven/iscream_thunderc-2.6.35
C++ Header | 76 lines | 55 code | 7 blank | 14 comment | 0 complexity | ef68eeaf8d22455365995ff3e9329247 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
 1/*
 2 * arch/arm/mach-at91/include/mach/at91sam9_smc.h
 3 *
 4 * Copyright (C) 2007 Andrew Victor
 5 * Copyright (C) 2007 Atmel Corporation.
 6 *
 7 * Static Memory Controllers (SMC) - System peripherals registers.
 8 * Based on AT91SAM9261 datasheet revision D.
 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91SAM9_SMC_H
17#define AT91SAM9_SMC_H
18
19#define AT91_SMC_SETUP(n)	(AT91_SMC + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
20#define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
21#define			AT91_SMC_NWESETUP_(x)	((x) << 0)
22#define		AT91_SMC_NCS_WRSETUP	(0x3f << 8)			/* NCS Setup Length in Write Access */
23#define			AT91_SMC_NCS_WRSETUP_(x)	((x) << 8)
24#define		AT91_SMC_NRDSETUP	(0x3f << 16)			/* NRD Setup Length */
25#define			AT91_SMC_NRDSETUP_(x)	((x) << 16)
26#define		AT91_SMC_NCS_RDSETUP	(0x3f << 24)			/* NCS Setup Length in Read Access */
27#define			AT91_SMC_NCS_RDSETUP_(x)	((x) << 24)
28
29#define AT91_SMC_PULSE(n)	(AT91_SMC + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
30#define		AT91_SMC_NWEPULSE	(0x7f <<  0)			/* NWE Pulse Length */
31#define			AT91_SMC_NWEPULSE_(x)	((x) << 0)
32#define		AT91_SMC_NCS_WRPULSE	(0x7f <<  8)			/* NCS Pulse Length in Write Access */
33#define			AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
34#define		AT91_SMC_NRDPULSE	(0x7f << 16)			/* NRD Pulse Length */
35#define			AT91_SMC_NRDPULSE_(x)	((x) << 16)
36#define		AT91_SMC_NCS_RDPULSE	(0x7f << 24)			/* NCS Pulse Length in Read Access */
37#define			AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
38
39#define AT91_SMC_CYCLE(n)	(AT91_SMC + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
40#define		AT91_SMC_NWECYCLE	(0x1ff << 0 )			/* Total Write Cycle Length */
41#define			AT91_SMC_NWECYCLE_(x)	((x) << 0)
42#define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
43#define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
44
45#define AT91_SMC_MODE(n)	(AT91_SMC + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
46#define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
47#define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
48#define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
49#define			AT91_SMC_EXNWMODE_DISABLE	(0 << 4)
50#define			AT91_SMC_EXNWMODE_FROZEN	(2 << 4)
51#define			AT91_SMC_EXNWMODE_READY		(3 << 4)
52#define		AT91_SMC_BAT		(1 <<  8)			/* Byte Access Type */
53#define			AT91_SMC_BAT_SELECT		(0 << 8)
54#define			AT91_SMC_BAT_WRITE		(1 << 8)
55#define		AT91_SMC_DBW		(3 << 12)			/* Data Bus Width */
56#define			AT91_SMC_DBW_8			(0 << 12)
57#define			AT91_SMC_DBW_16			(1 << 12)
58#define			AT91_SMC_DBW_32			(2 << 12)
59#define		AT91_SMC_TDF		(0xf << 16)			/* Data Float Time. */
60#define			AT91_SMC_TDF_(x)		((x) << 16)
61#define		AT91_SMC_TDFMODE	(1 << 20)			/* TDF Optimization - Enabled */
62#define		AT91_SMC_PMEN		(1 << 24)			/* Page Mode Enabled */
63#define		AT91_SMC_PS		(3 << 28)			/* Page Size */
64#define			AT91_SMC_PS_4			(0 << 28)
65#define			AT91_SMC_PS_8			(1 << 28)
66#define			AT91_SMC_PS_16			(2 << 28)
67#define			AT91_SMC_PS_32			(3 << 28)
68
69#if defined(AT91_SMC1)		/* The AT91SAM9263 has 2 Static Memory contollers */
70#define AT91_SMC1_SETUP(n)	(AT91_SMC1 + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
71#define AT91_SMC1_PULSE(n)	(AT91_SMC1 + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
72#define AT91_SMC1_CYCLE(n)	(AT91_SMC1 + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
73#define AT91_SMC1_MODE(n)	(AT91_SMC1 + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
74#endif
75
76#endif