/target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch

https://github.com/KFERMercer/OpenWrt · Patch · 260 lines · 238 code · 22 blank · 0 comment · 0 complexity · 874bba4b5f616328ded5c1fca4378c23 MD5 · raw file 

    

  1. --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
    2. 

  2. +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
    3. 

  3. @@ -53,6 +53,13 @@
    4. 

  4.  		};
    5. 

  5.  	};
    6. 

  6.  
    7. 

  7. +	gsw: gsw@0 {
    8. 

  8. +		compatible = "mediatek,mt753x";
    9. 

  9. +		mediatek,ethsys = <&ethsys>;
    10. 

  10. +		#address-cells = <1>;
    11. 

  11. +		#size-cells = <0>;
    12. 

  12. +	};
    13. 

  13. +
    14. 

  14.  	leds {
    15. 

  15.  		compatible = "gpio-leds";
    16. 

  16.  
    17. 

  17. @@ -146,6 +153,36 @@
    18. 

  18.  	};
    19. 

  19.  };
    20. 

  20.  
    21. 

  21. +&gsw {
    22. 

  22. +        mediatek,mdio = <&mdio>;
    23. 

  23. +        mediatek,portmap = "wllll";
    24. 

  24. +        mediatek,mdio_master_pinmux = <0>;
    25. 

  25. +        reset-gpios = <&pio 54 0>;
    26. 

  26. +        interrupt-parent = <&pio>;
    27. 

  27. +        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
    28. 

  28. +        status = "okay";
    29. 

  29. +
    30. 

  30. +        port5: port@5 {
    31. 

  31. +                compatible = "mediatek,mt753x-port";
    32. 

  32. +                reg = <5>;
    33. 

  33. +                phy-mode = "rgmii";
    34. 

  34. +                fixed-link {
    35. 

  35. +                        speed = <1000>;
    36. 

  36. +                        full-duplex;
    37. 

  37. +                };
    38. 

  38. +        };
    39. 

  39. +
    40. 

  40. +        port6: port@6 {
    41. 

  41. +                compatible = "mediatek,mt753x-port";
    42. 

  42. +                reg = <6>;
    43. 

  43. +                phy-mode = "sgmii";
    44. 

  44. +                fixed-link {
    45. 

  45. +                        speed = <2500>;
    46. 

  46. +                        full-duplex;
    47. 

  47. +                };
    48. 

  48. +        };
    49. 

  49. +};
    50. 

  50. +
    51. 

  51.  &i2c1 {
    52. 

  52.  	pinctrl-names = "default";
    53. 

  53.  	pinctrl-0 = <&i2c1_pins>;
    54. 

  54. --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
    55. 

  55. +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
    56. 

  56. @@ -1,7 +1,6 @@
    57. 

  57.  /*
    58. 

  58. - * Copyright (c) 2017 MediaTek Inc.
    59. 

  59. - * Author: Ming Huang <ming.huang@mediatek.com>
    60. 

  60. - *	   Sean Wang <sean.wang@mediatek.com>
    61. 

  61. + * Copyright (c) 2018 MediaTek Inc.
    62. 

  62. + * Author: Ryder Lee <ryder.lee@mediatek.com>
    63. 

  63.   *
    64. 

  64.   * SPDX-License-Identifier: (GPL-2.0 OR MIT)
    65. 

  65.   */
    66. 

  66. @@ -14,7 +13,7 @@
    67. 

  67.  #include "mt6380.dtsi"
    68. 

  68.  
    69. 

  69.  / {
    70. 

  70. -	model = "MediaTek MT7622 RFB1 board";
    71. 

  71. +	model = "MT7622_MT7531 RFB";
    72. 

  72.  	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
    73. 

  73.  
    74. 

  74.  	aliases {
    75. 

  75. @@ -23,7 +22,7 @@
    76. 

  76.  
    77. 

  77.  	chosen {
    78. 

  78.  		stdout-path = "serial0:115200n8";
    79. 

  79. -		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
    80. 

  80. +		bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
    81. 

  81.  	};
    82. 

  82.  
    83. 

  83.  	cpus {
    84. 

  84. @@ -40,23 +39,38 @@
    85. 

  85.  
    86. 

  86.  	gpio-keys {
    87. 

  87.  		compatible = "gpio-keys";
    88. 

  88. -		poll-interval = <100>;
    89. 

  89.  
    90. 

  90.  		factory {
    91. 

  91.  			label = "factory";
    92. 

  92.  			linux,code = <BTN_0>;
    93. 

  93. -			gpios = <&pio 0 0>;
    94. 

  94. +			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
    95. 

  95.  		};
    96. 

  96.  
    97. 

  97.  		wps {
    98. 

  98.  			label = "wps";
    99. 

  99.  			linux,code = <KEY_WPS_BUTTON>;
    100. 

  100. -			gpios = <&pio 102 0>;
    101. 

  101. +			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
    102. 

  102. +		};
    103. 

  103. +	};
    104. 

  104. +
    105. 

  105. +	leds {
    106. 

  106. +		compatible = "gpio-leds";
    107. 

  107. +
    108. 

  108. +		green {
    109. 

  109. +			label = "bpi-r64:pio:green";
    110. 

  110. +			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
    111. 

  111. +			default-state = "off";
    112. 

  112. +		};
    113. 

  113. +
    114. 

  114. +		red {
    115. 

  115. +			label = "bpi-r64:pio:red";
    116. 

  116. +			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
    117. 

  117. +			default-state = "off";
    118. 

  118.  		};
    119. 

  119.  	};
    120. 

  120.  
    121. 

  121.  	memory {
    122. 

  122. -		reg = <0 0x40000000 0 0x20000000>;
    123. 

  123. +		reg = <0 0x40000000 0 0x40000000>;
    124. 

  124.  	};
    125. 

  125.  
    126. 

  126.  	reg_1p8v: regulator-1p8v {
    127. 

  127. @@ -101,23 +115,82 @@
    128. 

  128.  };
    129. 

  129.  
    130. 

  130.  &eth {
    131. 

  131. -	pinctrl-names = "default";
    132. 

  132. -	pinctrl-0 = <&eth_pins>;
    133. 

  133.  	status = "okay";
    134. 

  134. +	gmac0: mac@0 {
    135. 

  135. +		compatible = "mediatek,eth-mac";
    136. 

  136. +		reg = <0>;
    137. 

  137. +		phy-mode = "2500base-x";
    138. 

  138. +
    139. 

  139. +		fixed-link {
    140. 

  140. +			speed = <2500>;
    141. 

  141. +			full-duplex;
    142. 

  142. +			pause;
    143. 

  143. +		};
    144. 

  144. +	};
    145. 

  145.  
    146. 

  146.  	gmac1: mac@1 {
    147. 

  147.  		compatible = "mediatek,eth-mac";
    148. 

  148.  		reg = <1>;
    149. 

  149. -		phy-handle = <&phy5>;
    150. 

  150. +		phy-mode = "rgmii";
    151. 

  151. +
    152. 

  152. +		fixed-link {
    153. 

  153. +			speed = <1000>;
    154. 

  154. +			full-duplex;
    155. 

  155. +			pause;
    156. 

  156. +		};
    157. 

  157.  	};
    158. 

  158.  
    159. 

  159. -	mdio-bus {
    160. 

  160. +	mdio: mdio-bus {
    161. 

  161.  		#address-cells = <1>;
    162. 

  162.  		#size-cells = <0>;
    163. 

  163.  
    164. 

  164. -		phy5: ethernet-phy@5 {
    165. 

  165. -			reg = <5>;
    166. 

  166. -			phy-mode = "sgmii";
    167. 

  167. +		switch@0 {
    168. 

  168. +			compatible = "mediatek,mt7531";
    169. 

  169. +			reg = <0>;
    170. 

  170. +			reset-gpios = <&pio 54 0>;
    171. 

  171. +
    172. 

  172. +			ports {
    173. 

  173. +				#address-cells = <1>;
    174. 

  174. +				#size-cells = <0>;
    175. 

  175. +
    176. 

  176. +				port@0 {
    177. 

  177. +					reg = <0>;
    178. 

  178. +					label = "lan1";
    179. 

  179. +				};
    180. 

  180. +
    181. 

  181. +				port@1 {
    182. 

  182. +					reg = <1>;
    183. 

  183. +					label = "lan2";
    184. 

  184. +				};
    185. 

  185. +
    186. 

  186. +				port@2 {
    187. 

  187. +					reg = <2>;
    188. 

  188. +					label = "lan3";
    189. 

  189. +				};
    190. 

  190. +
    191. 

  191. +				port@3 {
    192. 

  192. +					reg = <3>;
    193. 

  193. +					label = "lan4";
    194. 

  194. +				};
    195. 

  195. +
    196. 

  196. +				port@4 {
    197. 

  197. +					reg = <4>;
    198. 

  198. +					label = "wan";
    199. 

  199. +				};
    200. 

  200. +
    201. 

  201. +				port@6 {
    202. 

  202. +					reg = <6>;
    203. 

  203. +					label = "cpu";
    204. 

  204. +					ethernet = <&gmac0>;
    205. 

  205. +					phy-mode = "2500base-x";
    206. 

  206. +
    207. 

  207. +					fixed-link {
    208. 

  208. +						speed = <2500>;
    209. 

  209. +						full-duplex;
    210. 

  210. +						pause;
    211. 

  211. +					};
    212. 

  212. +				};
    213. 

  213. +			};
    214. 

  214.  		};
    215. 

  215.  	};
    216. 

  216.  };
    217. 

  217. @@ -185,15 +258,28 @@
    218. 

  218.  
    219. 

  219.  &pcie {
    220. 

  220.  	pinctrl-names = "default";
    221. 

  221. -	pinctrl-0 = <&pcie0_pins>;
    222. 

  222. +	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
    223. 

  223.  	status = "okay";
    224. 

  224.  
    225. 

  225.  	pcie@0,0 {
    226. 

  226.  		status = "okay";
    227. 

  227.  	};
    228. 

  228. +
    229. 

  229. +	pcie@1,0 {
    230. 

  230. +		status = "okay";
    231. 

  231. +	};
    232. 

  232.  };
    233. 

  233.  
    234. 

  234.  &pio {
    235. 

  235. +	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
    236. 

  236. +	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
    237. 

  237. +	 */
    238. 

  238. +	asm_sel {
    239. 

  239. +		gpio-hog;
    240. 

  240. +		gpios = <90 GPIO_ACTIVE_HIGH>;
    241. 

  241. +		output-high;
    242. 

  242. +	};
    243. 

  243. +
    244. 

  244.  	/* eMMC is shared pin with parallel NAND */
    245. 

  245.  	emmc_pins_default: emmc-pins-default {
    246. 

  246.  		mux {
    247. 

  247. @@ -460,11 +546,11 @@
    248. 

  248.  };
    249. 

  249.  
    250. 

  250.  &sata {
    251. 

  251. -	status = "okay";
    252. 

  252. +	status = "disable";
    253. 

  253.  };
    254. 

  254.  
    255. 

  255.  &sata_phy {
    256. 

  256. -	status = "okay";
    257. 

  257. +	status = "disable";
    258. 

  258.  };
    259. 

  259.  
    260. 

  260.  &spi0 {
    261.