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/open-vm-tools/lib/include/x86cpuid.h

https://bitbucket.org/nizard/open-vm-tools
C Header | 1466 lines | 985 code | 168 blank | 313 comment | 107 complexity | d9906aed8526086de680f68a42a6262e MD5 | raw file
Possible License(s): GPL-2.0, MPL-2.0-no-copyleft-exception, LGPL-2.1, BSD-3-Clause

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  1. /*********************************************************
    2. 

  2.  * Copyright (C) 1998-2012 VMware, Inc. All rights reserved.
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify it
    5. 

  5.  * under the terms of the GNU Lesser General Public License as published
    6. 

  6.  * by the Free Software Foundation version 2.1 and no later version.
    7. 

  7.  *
    8. 

  8.  * This program is distributed in the hope that it will be useful, but
    9. 

  9.  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
    10. 

  10.  * or FITNESS FOR A PARTICULAR PURPOSE.  See the Lesser GNU General Public
    11. 

  11.  * License for more details.
    12. 

  12.  *
    13. 

  13.  * You should have received a copy of the GNU Lesser General Public License
    14. 

  14.  * along with this program; if not, write to the Free Software Foundation, Inc.,
    15. 

  15.  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA.
    16. 

  16.  *
    17. 

  17.  *********************************************************/
    18. 

  18. 

  19. /*********************************************************
    20. 

  20.  * The contents of this file are subject to the terms of the Common
    21. 

  21.  * Development and Distribution License (the "License") version 1.0
    22. 

  22.  * and no later version.  You may not use this file except in
    23. 

  23.  * compliance with the License.
    24. 

  24.  *
    25. 

  25.  * You can obtain a copy of the License at
    26. 

  26.  *         http://www.opensource.org/licenses/cddl1.php
    27. 

  27.  *
    28. 

  28.  * See the License for the specific language governing permissions
    29. 

  29.  * and limitations under the License.
    30. 

  30.  *
    31. 

  31.  *********************************************************/
    32. 

  32. 

  33. #ifndef _X86CPUID_H_
    34. 

  34. #define _X86CPUID_H_
    35. 

  35. 

  36. /* http://www.sandpile.org/ia32/cpuid.htm */
    37. 

  37. 

  38. #define INCLUDE_ALLOW_USERLEVEL
    39. 

  39. #define INCLUDE_ALLOW_VMX
    40. 

  40. 

  41. #define INCLUDE_ALLOW_VMKERNEL
    42. 

  42. #define INCLUDE_ALLOW_MODULE
    43. 

  43. #define INCLUDE_ALLOW_DISTRIBUTE
    44. 

  44. #define INCLUDE_ALLOW_VMK_MODULE
    45. 

  45. #define INCLUDE_ALLOW_VMCORE
    46. 

  46. #define INCLUDE_ALLOW_VMMON
    47. 

  47. #include "includeCheck.h"
    48. 

  48. 

  49. #include "vm_basic_types.h"
    50. 

  50. #include "community_source.h"
    51. 

  51. #include "x86vendor.h"
    52. 

  52. #include "vm_assert.h"
    53. 

  53. 

  54. /*
    55. 

  55.  * The linux kernel's ptrace.h stupidly defines the bare
    56. 

  56.  * EAX/EBX/ECX/EDX, which wrecks havoc with our preprocessor tricks.
    57. 

  57.  */
    58. 

  58. #undef EAX
    59. 

  59. #undef EBX
    60. 

  60. #undef ECX
    61. 

  61. #undef EDX
    62. 

  62. 

  63. typedef struct CPUIDRegs {
    64. 

  64.    uint32 eax, ebx, ecx, edx;
    65. 

  65. } CPUIDRegs;
    66. 

  66. 

  67. typedef union CPUIDRegsUnion {
    68. 

  68.    uint32 array[4];
    69. 

  69.    CPUIDRegs regs;
    70. 

  70. } CPUIDRegsUnion;
    71. 

  71. 

  72. /*
    73. 

  73.  * Results of calling cpuid(eax, ecx) on all host logical CPU.
    74. 

  74.  */
    75. 

  75. #ifdef _MSC_VER
    76. 

  76. #pragma warning (disable :4200) // non-std extension: zero-sized array in struct
    77. 

  77. #endif
    78. 

  78. 

  79. typedef
    80. 

  80. #include "vmware_pack_begin.h"
    81. 

  81. struct CPUIDReply {
    82. 

  82.    /*
    83. 

  83.     * Unique host logical CPU identifier. It does not change across queries, so
    84. 

  84.     * we use it to correlate the replies of multiple queries.
    85. 

  85.     */
    86. 

  86.    uint64 tag;                // OUT
    87. 

  87. 

  88.    CPUIDRegs regs;            // OUT
    89. 

  89. }
    90. 

  90. #include "vmware_pack_end.h"
    91. 

  91. CPUIDReply;
    92. 

  92. 

  93. typedef
    94. 

  94. #include "vmware_pack_begin.h"
    95. 

  95. struct CPUIDQuery {
    96. 

  96.    uint32 eax;                // IN
    97. 

  97.    uint32 ecx;                // IN
    98. 

  98.    uint32 numLogicalCPUs;     // IN/OUT
    99. 

  99.    CPUIDReply logicalCPUs[0]; // OUT
    100. 

  100. }
    101. 

  101. #include "vmware_pack_end.h"
    102. 

  102. CPUIDQuery;
    103. 

  103. 

  104. /*
    105. 

  105.  * CPUID levels the monitor caches and ones that are not cached, but
    106. 

  106.  * have fields defined below (short name and actual value).
    107. 

  107.  * 
    108. 

  108.  * The first parameter defines whether the level has its default masks
    109. 

  109.  * generated from the values in this file.  Any level which is marked
    110. 

  110.  * as FALSE here *must* have all monitor support types set to NA.  A
    111. 

  111.  * static assert in lib/cpuidcompat/cpuidcompat.c will check this.
    112. 

  112.  */
    113. 

  113. 

  114. #define CPUID_CACHED_LEVELS                     \
    115. 

  115.    CPUIDLEVEL(TRUE,  0,  0)                     \
    116. 

  116.    CPUIDLEVEL(TRUE,  1,  1)                     \
    117. 

  117.    CPUIDLEVEL(FALSE, 5,  5)                     \
    118. 

  118.    CPUIDLEVEL(TRUE,  7,  7)                     \
    119. 

  119.    CPUIDLEVEL(FALSE, A,  0xA)                   \
    120. 

  120.    CPUIDLEVEL(TRUE,  D,  0xD)                   \
    121. 

  121.    CPUIDLEVEL(FALSE,400, 0x40000000)            \
    122. 

  122.    CPUIDLEVEL(FALSE,401, 0x40000001)            \
    123. 

  123.    CPUIDLEVEL(FALSE,402, 0x40000002)            \
    124. 

  124.    CPUIDLEVEL(FALSE,403, 0x40000003)            \
    125. 

  125.    CPUIDLEVEL(FALSE,404, 0x40000004)            \
    126. 

  126.    CPUIDLEVEL(FALSE,410, 0x40000010)            \
    127. 

  127.    CPUIDLEVEL(FALSE, 80, 0x80000000)            \
    128. 

  128.    CPUIDLEVEL(TRUE,  81, 0x80000001)            \
    129. 

  129.    CPUIDLEVEL(FALSE, 87, 0x80000007)            \
    130. 

  130.    CPUIDLEVEL(FALSE, 88, 0x80000008)            \
    131. 

  131.    CPUIDLEVEL(TRUE,  8A, 0x8000000A)
    132. 

  132. 

  133. #define CPUID_UNCACHED_LEVELS                   \
    134. 

  134.    CPUIDLEVEL(FALSE, 4, 4)                      \
    135. 

  135.    CPUIDLEVEL(FALSE, 6, 6)                      \
    136. 

  136.    CPUIDLEVEL(FALSE, B, 0xB)                    \
    137. 

  137.    CPUIDLEVEL(FALSE, 85, 0x80000005)            \
    138. 

  138.    CPUIDLEVEL(FALSE, 86, 0x80000006)            \
    139. 

  139.    CPUIDLEVEL(FALSE, 819, 0x80000019)           \
    140. 

  140.    CPUIDLEVEL(FALSE, 81A, 0x8000001A)           \
    141. 

  141.    CPUIDLEVEL(FALSE, 81B, 0x8000001B)           \
    142. 

  142.    CPUIDLEVEL(FALSE, 81C, 0x8000001C)           \
    143. 

  143.    CPUIDLEVEL(FALSE, 81D, 0x8000001D)           \
    144. 

  144.    CPUIDLEVEL(FALSE, 81E, 0x8000001E)
    145. 

  145. 

  146. #define CPUID_ALL_LEVELS                        \
    147. 

  147.    CPUID_CACHED_LEVELS                          \
    148. 

  148.    CPUID_UNCACHED_LEVELS
    149. 

  149. 

  150. /* Define cached CPUID levels in the form: CPUID_LEVEL_<ShortName> */
    151. 

  151. typedef enum {
    152. 

  152. #define CPUIDLEVEL(t, s, v) CPUID_LEVEL_##s,
    153. 

  153.    CPUID_CACHED_LEVELS
    154. 

  154. #undef CPUIDLEVEL
    155. 

  155.    CPUID_NUM_CACHED_LEVELS
    156. 

  156. } CpuidCachedLevel;
    157. 

  157. 

  158. /* Enum to translate between shorthand name and actual CPUID level value. */
    159. 

  159. enum {
    160. 

  160. #define CPUIDLEVEL(t, s, v) CPUID_LEVEL_VAL_##s = v,
    161. 

  161.    CPUID_ALL_LEVELS
    162. 

  162. #undef CPUIDLEVEL
    163. 

  163. };
    164. 

  164. 

  165. 

  166. /* Named feature leaves */
    167. 

  167. #define CPUID_MWAIT_FEATURES       5
    168. 

  168. #define CPUID_SVM_FEATURES         0x8000000a
    169. 

  169. 

  170. 

  171. /*
    172. 

  172.  * CPUID result registers
    173. 

  173.  */
    174. 

  174. 

  175. #define CPUID_REGS                              \
    176. 

  176.    CPUIDREG(EAX, eax)                           \
    177. 

  177.    CPUIDREG(EBX, ebx)                           \
    178. 

  178.    CPUIDREG(ECX, ecx)                           \
    179. 

  179.    CPUIDREG(EDX, edx)
    180. 

  180. 

  181. typedef enum {
    182. 

  182. #define CPUIDREG(uc, lc) CPUID_REG_##uc,
    183. 

  183.    CPUID_REGS
    184. 

  184. #undef CPUIDREG
    185. 

  185.    CPUID_NUM_REGS
    186. 

  186. } CpuidReg;
    187. 

  187. 

  188. #define CPUID_INTEL_VENDOR_STRING       "GenuntelineI"
    189. 

  189. #define CPUID_AMD_VENDOR_STRING         "AuthcAMDenti"
    190. 

  190. #define CPUID_CYRIX_VENDOR_STRING       "CyriteadxIns"
    191. 

  191. #define CPUID_VIA_VENDOR_STRING         "CentaulsaurH"
    192. 

  192. 

  193. #define CPUID_HYPERV_HYPERVISOR_VENDOR_STRING  "Microsoft Hv"
    194. 

  194. #define CPUID_KVM_HYPERVISOR_VENDOR_STRING     "KVMKVMKVM\0\0\0"
    195. 

  195. #define CPUID_VMWARE_HYPERVISOR_VENDOR_STRING  "VMwareVMware"
    196. 

  196. #define CPUID_XEN_HYPERVISOR_VENDOR_STRING     "XenVMMXenVMM"
    197. 

  197. 

  198. #define CPUID_INTEL_VENDOR_STRING_FIXED "GenuineIntel"
    199. 

  199. #define CPUID_AMD_VENDOR_STRING_FIXED   "AuthenticAMD"
    200. 

  200. #define CPUID_CYRIX_VENDOR_STRING_FIXED "CyrixInstead"
    201. 

  201. #define CPUID_VIA_VENDOR_STRING_FIXED   "CentaurHauls"
    202. 

  202. 

  203. /*
    204. 

  204.  * FIELD can be defined to process the CPUID information provided
    205. 

  205.  * in the following CPUID_FIELD_DATA macro.  The first parameter is
    206. 

  206.  * the CPUID level of the feature (must be defined in
    207. 

  207.  * CPUID_ALL_LEVELS, above.  The second parameter is the CPUID result
    208. 

  208.  * register in which the field is returned (defined in CPUID_REGS).
    209. 

  209.  * The third field is the vendor(s) this feature applies to.  "COMMON"
    210. 

  210.  * means all vendors apply.  UNKNOWN may not be used here.  The fourth
    211. 

  211.  * and fifth parameters are the bit position of the field and the
    212. 

  212.  * width, respectively.  The sixth is the text name of the field.
    213. 

  213.  *
    214. 

  214.  * The seventh parameters specifies the monitor support
    215. 

  215.  * characteristics for this field.  The value must be a valid
    216. 

  216.  * CpuidFieldSupported value (omitting CPUID_FIELD_SUPPORT_ for
    217. 

  217.  * convenience).  The meaning of those values are described below.
    218. 

  218.  *
    219. 

  219.  * The eighth parameter describes whether the feature is capable of
    220. 

  220.  * being used by usermode code (TRUE), or just CPL0 kernel code
    221. 

  221.  * (FALSE).
    222. 

  222.  *
    223. 

  223.  * FLAG is defined identically to FIELD, but its accessors are more
    224. 

  224.  * appropriate for 1-bit flags, and compile-time asserts enforce that
    225. 

  225.  * the size is 1 bit wide.
    226. 

  226.  */
    227. 

  227. 

  228. 

  229. /*
    230. 

  230.  * CpuidFieldSupported is made up of the following values:
    231. 

  231.  *
    232. 

  232.  *     NO: A feature/field that IS NOT SUPPORTED by the monitor.  Even
    233. 

  233.  *     if the host supports this feature, we will never expose it to
    234. 

  234.  *     the guest.
    235. 

  235.  *
    236. 

  236.  *     YES: A feature/field that IS SUPPORTED by the monitor.  If the
    237. 

  237.  *     host supports this feature, we will expose it to the guest.  If
    238. 

  238.  *     not, then we will not set the feature.
    239. 

  239.  *
    240. 

  240.  *     ANY: A feature/field that IS ALWAYS SUPPORTED by the monitor.
    241. 

  241.  *     Even if the host does not support the feature, the monitor can
    242. 

  242.  *     expose the feature to the guest.
    243. 

  243.  *
    244. 

  244.  *     NA: Only legal for levels not masked/tested by default (see
    245. 

  245.  *     above for this definition).  Such fields must always be marked
    246. 

  246.  *     as NA.
    247. 

  247.  *
    248. 

  248.  * These distinctions, when combined with the feature's CPL3
    249. 

  249.  * properties can be translated into a common CPUID mask string as
    250. 

  250.  * follows:
    251. 

  251.  *
    252. 

  252.  *     NO + CPL3 --> "R" (Reserved).  We don't support the feature,
    253. 

  253.  *     but we can't properly hide this from applications when using
    254. 

  254.  *     direct execution or HV with apps that do try/catch/fail, so we
    255. 

  255.  *     must still perform compatibility checks.
    256. 

  256.  *
    257. 

  257.  *     NO + !CPL3 --> "0" (Masked).  We can hide this from the guest.
    258. 

  258.  *
    259. 

  259.  *     YES --> "H" (Host).  We support the feature, so show it to the
    260. 

  260.  *     guest if the host has the feature.
    261. 

  261.  *
    262. 

  262.  *     ANY/NA --> "X" (Ignore).  By default, don't perform checks for
    263. 

  263.  *     this feature bit.  Per-GOS masks may choose to set this bit in
    264. 

  264.  *     the guest.  (e.g. the APIC feature bit is always set to 1.)
    265. 

  265.  *
    266. 

  266.  *     See lib/cpuidcompat/cpuidcompat.c for any possible overrides to
    267. 

  267.  *     these defaults.
    268. 

  268.  */
    269. 

  269. typedef enum {
    270. 

  270.    CPUID_FIELD_SUPPORTED_NO,
    271. 

  271.    CPUID_FIELD_SUPPORTED_YES,
    272. 

  272.    CPUID_FIELD_SUPPORTED_ANY,
    273. 

  273.    CPUID_FIELD_SUPPORTED_NA,
    274. 

  274.    CPUID_NUM_FIELD_SUPPORTEDS
    275. 

  275. } CpuidFieldSupported;
    276. 

  276. 

  277. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    278. 

  278. #define CPUID_FIELD_DATA_LEVEL_0                                               \
    279. 

  279. FIELD(  0,  0, EAX, COMMON,  0, 32, NUMLEVELS,                     ANY, FALSE) \
    280. 

  280. FIELD(  0,  0, EBX, COMMON,  0, 32, VENDOR1,                       YES, TRUE)  \
    281. 

  281. FIELD(  0,  0, ECX, COMMON,  0, 32, VENDOR3,                       YES, TRUE)  \
    282. 

  282. FIELD(  0,  0, EDX, COMMON,  0, 32, VENDOR2,                       YES, TRUE)
    283. 

  283.                                                         
    284. 

  284. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    285. 

  285. #define CPUID_FIELD_DATA_LEVEL_1                                               \
    286. 

  286. FIELD(  1,  0, EAX, COMMON,  0,  4, STEPPING,                      ANY, FALSE) \
    287. 

  287. FIELD(  1,  0, EAX, COMMON,  4,  4, MODEL,                         ANY, FALSE) \
    288. 

  288. FIELD(  1,  0, EAX, COMMON,  8,  4, FAMILY,                        YES, FALSE) \
    289. 

  289. FIELD(  1,  0, EAX, COMMON, 12,  2, TYPE,                          ANY, FALSE) \
    290. 

  290. FIELD(  1,  0, EAX, COMMON, 16,  4, EXTENDED_MODEL,                ANY, FALSE) \
    291. 

  291. FIELD(  1,  0, EAX, COMMON, 20,  8, EXTENDED_FAMILY,               YES, FALSE) \
    292. 

  292. FIELD(  1,  0, EBX, COMMON,  0,  8, BRAND_ID,                      ANY, FALSE) \
    293. 

  293. FIELD(  1,  0, EBX, COMMON,  8,  8, CLFL_SIZE,                     ANY, FALSE) \
    294. 

  294. FIELD(  1,  0, EBX, COMMON, 16,  8, LCPU_COUNT,                    ANY, FALSE) \
    295. 

  295. FIELD(  1,  0, EBX, COMMON, 24,  8, APICID,                        ANY, FALSE) \
    296. 

  296. FLAG(   1,  0, ECX, COMMON, 0,   1, SSE3,                          YES, TRUE)  \
    297. 

  297. FLAG(   1,  0, ECX, COMMON, 1,   1, PCLMULQDQ,                     YES, TRUE)  \
    298. 

  298. FLAG(   1,  0, ECX, INTEL,  2,   1, DTES64,                        NO,  FALSE) \
    299. 

  299. FLAG(   1,  0, ECX, COMMON, 3,   1, MWAIT,                         YES, FALSE) \
    300. 

  300. FLAG(   1,  0, ECX, INTEL,  4,   1, DSCPL,                         NO,  FALSE) \
    301. 

  301. FLAG(   1,  0, ECX, INTEL,  5,   1, VMX,                           YES, FALSE) \
    302. 

  302. FLAG(   1,  0, ECX, INTEL,  6,   1, SMX,                           NO,  FALSE) \
    303. 

  303. FLAG(   1,  0, ECX, INTEL,  7,   1, EIST,                          NO,  FALSE) \
    304. 

  304. FLAG(   1,  0, ECX, INTEL,  8,   1, TM2,                           NO,  FALSE) \
    305. 

  305. FLAG(   1,  0, ECX, COMMON, 9,   1, SSSE3,                         YES, TRUE)  \
    306. 

  306. FLAG(   1,  0, ECX, INTEL,  10,  1, CNXTID,                        NO,  FALSE) \
    307. 

  307. FLAG(   1,  0, ECX, INTEL,  11,  1, NDA11,                         NO,  FALSE) \
    308. 

  308. FLAG(   1,  0, ECX, COMMON, 12,  1, FMA,                           YES, TRUE)  \
    309. 

  309. FLAG(   1,  0, ECX, COMMON, 13,  1, CMPXCHG16B,                    YES, TRUE)  \
    310. 

  310. FLAG(   1,  0, ECX, INTEL,  14,  1, xTPR,                          NO,  FALSE) \
    311. 

  311. FLAG(   1,  0, ECX, INTEL,  15,  1, PDCM,                          NO,  FALSE) \
    312. 

  312. FLAG(   1,  0, ECX, INTEL,  17,  1, PCID,                          YES, FALSE) \
    313. 

  313. FLAG(   1,  0, ECX, INTEL,  18,  1, DCA,                           NO,  FALSE) \
    314. 

  314. FLAG(   1,  0, ECX, COMMON, 19,  1, SSE41,                         YES, TRUE)  \
    315. 

  315. FLAG(   1,  0, ECX, COMMON, 20,  1, SSE42,                         YES, TRUE)  \
    316. 

  316. FLAG(   1,  0, ECX, COMMON, 21,  1, x2APIC,                        ANY, FALSE) \
    317. 

  317. FLAG(   1,  0, ECX, INTEL,  22,  1, MOVBE,                         YES, TRUE)  \
    318. 

  318. FLAG(   1,  0, ECX, COMMON, 23,  1, POPCNT,                        YES, TRUE)  \
    319. 

  319. FLAG(   1,  0, ECX, COMMON, 24,  1, TSC_DEADLINE,                  NO,  FALSE) \
    320. 

  320. FLAG(   1,  0, ECX, COMMON, 25,  1, AES,                           YES, TRUE)  \
    321. 

  321. FLAG(   1,  0, ECX, COMMON, 26,  1, XSAVE,                         YES, FALSE) \
    322. 

  322. FLAG(   1,  0, ECX, COMMON, 27,  1, OSXSAVE,                       ANY, FALSE) \
    323. 

  323. FLAG(   1,  0, ECX, COMMON, 28,  1, AVX,                           YES, FALSE) \
    324. 

  324. FLAG(   1,  0, ECX, COMMON, 29,  1, F16C,                          YES, TRUE)  \
    325. 

  325. FLAG(   1,  0, ECX, COMMON, 30,  1, RDRAND,                        YES, TRUE)  \
    326. 

  326. FLAG(   1,  0, ECX, COMMON, 31,  1, HYPERVISOR,                    ANY, TRUE)  \
    327. 

  327. FLAG(   1,  0, EDX, COMMON, 0,   1, FPU,                           YES, TRUE)  \
    328. 

  328. FLAG(   1,  0, EDX, COMMON, 1,   1, VME,                           YES, FALSE) \
    329. 

  329. FLAG(   1,  0, EDX, COMMON, 2,   1, DE,                            YES, FALSE) \
    330. 

  330. FLAG(   1,  0, EDX, COMMON, 3,   1, PSE,                           YES, FALSE) \
    331. 

  331. FLAG(   1,  0, EDX, COMMON, 4,   1, TSC,                           YES, TRUE)  \
    332. 

  332. FLAG(   1,  0, EDX, COMMON, 5,   1, MSR,                           YES, FALSE) \
    333. 

  333. FLAG(   1,  0, EDX, COMMON, 6,   1, PAE,                           YES, FALSE) \
    334. 

  334. FLAG(   1,  0, EDX, COMMON, 7,   1, MCE,                           YES, FALSE) \
    335. 

  335. FLAG(   1,  0, EDX, COMMON, 8,   1, CX8,                           YES, TRUE)  \
    336. 

  336. FLAG(   1,  0, EDX, COMMON, 9,   1, APIC,                          ANY, FALSE) \
    337. 

  337. FLAG(   1,  0, EDX, COMMON, 11,  1, SEP,                           YES, TRUE)  \
    338. 

  338. FLAG(   1,  0, EDX, COMMON, 12,  1, MTRR,                          YES, FALSE) \
    339. 

  339. FLAG(   1,  0, EDX, COMMON, 13,  1, PGE,                           YES, FALSE) \
    340. 

  340. FLAG(   1,  0, EDX, COMMON, 14,  1, MCA,                           YES, FALSE) \
    341. 

  341. FLAG(   1,  0, EDX, COMMON, 15,  1, CMOV,                          YES, TRUE)  \
    342. 

  342. FLAG(   1,  0, EDX, COMMON, 16,  1, PAT,                           YES, FALSE) \
    343. 

  343. FLAG(   1,  0, EDX, COMMON, 17,  1, PSE36,                         YES, FALSE) \
    344. 

  344. FLAG(   1,  0, EDX, INTEL,  18,  1, PSN,                           YES, FALSE) \
    345. 

  345. FLAG(   1,  0, EDX, COMMON, 19,  1, CLFSH,                         YES, TRUE)  \
    346. 

  346. FLAG(   1,  0, EDX, INTEL,  21,  1, DS,                            YES, FALSE) \
    347. 

  347. FLAG(   1,  0, EDX, INTEL,  22,  1, ACPI,                          ANY, FALSE) \
    348. 

  348. FLAG(   1,  0, EDX, COMMON, 23,  1, MMX,                           YES, TRUE)  \
    349. 

  349. FLAG(   1,  0, EDX, COMMON, 24,  1, FXSR,                          YES, TRUE)  \
    350. 

  350. FLAG(   1,  0, EDX, COMMON, 25,  1, SSE,                           YES, TRUE)  \
    351. 

  351. FLAG(   1,  0, EDX, COMMON, 26,  1, SSE2,                          YES, TRUE)  \
    352. 

  352. FLAG(   1,  0, EDX, INTEL,  27,  1, SS,                            YES, FALSE) \
    353. 

  353. FLAG(   1,  0, EDX, COMMON, 28,  1, HTT,                           ANY, FALSE) \
    354. 

  354. FLAG(   1,  0, EDX, INTEL,  29,  1, TM,                            NO,  FALSE) \
    355. 

  355. FLAG(   1,  0, EDX, INTEL,  30,  1, IA64,                          NO,  FALSE) \
    356. 

  356. FLAG(   1,  0, EDX, INTEL,  31,  1, PBE,                           NO,  FALSE)
    357. 

  357. 

  358. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    359. 

  359. #define CPUID_FIELD_DATA_LEVEL_4                                               \
    360. 

  360. FIELD(  4,  0, EAX, INTEL,   0,  5, LEAF4_CACHE_TYPE,              NA,  FALSE) \
    361. 

  361. FIELD(  4,  0, EAX, INTEL,   5,  3, LEAF4_CACHE_LEVEL,             NA,  FALSE) \
    362. 

  362. FLAG(   4,  0, EAX, INTEL,   8,  1, LEAF4_CACHE_SELF_INIT,         NA,  FALSE) \
    363. 

  363. FLAG(   4,  0, EAX, INTEL,   9,  1, LEAF4_CACHE_FULLY_ASSOC,       NA,  FALSE) \
    364. 

  364. FIELD(  4,  0, EAX, INTEL,  14, 12, LEAF4_CACHE_NUMHT_SHARING,     NA,  FALSE) \
    365. 

  365. FIELD(  4,  0, EAX, INTEL,  26,  6, LEAF4_CORE_COUNT,              NA,  FALSE) \
    366. 

  366. FIELD(  4,  0, EBX, INTEL,   0, 12, LEAF4_CACHE_LINE,              NA,  FALSE) \
    367. 

  367. FIELD(  4,  0, EBX, INTEL,  12, 10, LEAF4_CACHE_PART,              NA,  FALSE) \
    368. 

  368. FIELD(  4,  0, EBX, INTEL,  22, 10, LEAF4_CACHE_WAYS,              NA,  FALSE) \
    369. 

  369. FIELD(  4,  0, ECX, INTEL,   0, 32, LEAF4_CACHE_SETS,              NA,  FALSE) \
    370. 

  370. FLAG(   4,  0, EDX, INTEL,   0,  1, LEAF4_CACHE_WBINVD_NOT_GUARANTEED, NA,  FALSE) \
    371. 

  371. FLAG(   4,  0, EDX, INTEL,   1,  1, LEAF4_CACHE_IS_INCLUSIVE,      NA,  FALSE) \
    372. 

  372. FLAG(   4,  0, EDX, INTEL,   2,  1, LEAF4_CACHE_COMPLEX_INDEXING,  NA,  FALSE)
    373. 

  373. 

  374. /*     LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    375. 

  375. #define CPUID_FIELD_DATA_LEVEL_5                                               \
    376. 

  376. FIELD(  5,  0, EAX, COMMON,  0, 16, MWAIT_MIN_SIZE,                NA,  FALSE) \
    377. 

  377. FIELD(  5,  0, EBX, COMMON,  0, 16, MWAIT_MAX_SIZE,                NA,  FALSE) \
    378. 

  378. FLAG(   5,  0, ECX, COMMON,  0,  1, MWAIT_EXTENSIONS,              NA,  FALSE) \
    379. 

  379. FLAG(   5,  0, ECX, COMMON,  1,  1, MWAIT_INTR_BREAK,              NA,  FALSE) \
    380. 

  380. FIELD(  5,  0, EDX, INTEL,   0,  4, MWAIT_C0_SUBSTATE,             NA,  FALSE) \
    381. 

  381. FIELD(  5,  0, EDX, INTEL,   4,  4, MWAIT_C1_SUBSTATE,             NA,  FALSE) \
    382. 

  382. FIELD(  5,  0, EDX, INTEL,   8,  4, MWAIT_C2_SUBSTATE,             NA,  FALSE) \
    383. 

  383. FIELD(  5,  0, EDX, INTEL,  12,  4, MWAIT_C3_SUBSTATE,             NA,  FALSE) \
    384. 

  384. FIELD(  5,  0, EDX, INTEL,  16,  4, MWAIT_C4_SUBSTATE,             NA,  FALSE)
    385. 

  385. 

  386. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    387. 

  387. #define CPUID_FIELD_DATA_LEVEL_6                                               \
    388. 

  388. FLAG(   6,  0, EAX, INTEL,   0,  1, THERMAL_SENSOR,                NA,  FALSE) \
    389. 

  389. FLAG(   6,  0, EAX, INTEL,   1,  1, TURBO_MODE,                    NA,  FALSE) \
    390. 

  390. FLAG(   6,  0, EAX, INTEL,   2,  1, APIC_INVARIANT,                NA,  FALSE) \
    391. 

  391. FIELD(  6,  0, EBX, INTEL,   0,  4, NUM_INTR_THRESHOLDS,           NA,  FALSE) \
    392. 

  392. FLAG(   6,  0, ECX, INTEL,   0,  1, HW_COORD_FEEDBACK,             NA,  FALSE) \
    393. 

  393. FLAG(   6,  0, ECX, INTEL,   3,  1, ENERGY_PERF_BIAS,              NA,  FALSE)
    394. 

  394. 

  395. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    396. 

  396. #define CPUID_FIELD_DATA_LEVEL_7                                               \
    397. 

  397. FLAG(   7,  0, EBX, INTEL,   0,  1, FSGSBASE,                      YES, FALSE) \
    398. 

  398. FLAG(   7,  0, EBX, AMD,     3,  1, BMI1,                          YES, TRUE ) \
    399. 

  399. FLAG(   7,  0, EBX, INTEL,   4,  1, HLE,                           YES, TRUE)  \
    400. 

  400. FLAG(   7,  0, EBX, INTEL,   7,  1, SMEP,                          YES, FALSE) \
    401. 

  401. FLAG(   7,  0, EBX, INTEL,   9,  1, ENFSTRG,                       YES, FALSE) \
    402. 

  402. FLAG(   7,  0, EBX, INTEL,  10,  1, INVPCID,                       NO,  FALSE) \
    403. 

  403. FLAG(   7,  0, EBX, INTEL,  11,  1, RTM,                           NO,  TRUE)
    404. 

  404. 

  405. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    406. 

  406. #define CPUID_FIELD_DATA_LEVEL_A                                               \
    407. 

  407. FIELD(  A,  0, EAX, INTEL,   0,  8, PMC_VERSION,                   NA,  FALSE) \
    408. 

  408. FIELD(  A,  0, EAX, INTEL,   8,  8, PMC_NUM_GEN,                   NA,  FALSE) \
    409. 

  409. FIELD(  A,  0, EAX, INTEL,  16,  8, PMC_WIDTH_GEN,                 NA,  FALSE) \
    410. 

  410. FIELD(  A,  0, EAX, INTEL,  24,  8, PMC_EBX_LENGTH,                NA,  FALSE) \
    411. 

  411. FLAG(   A,  0, EBX, INTEL,   0,  1, PMC_CORE_CYCLES,               NA,  FALSE) \
    412. 

  412. FLAG(   A,  0, EBX, INTEL,   1,  1, PMC_INSTR_RETIRED,             NA,  FALSE) \
    413. 

  413. FLAG(   A,  0, EBX, INTEL,   2,  1, PMC_REF_CYCLES,                NA,  FALSE) \
    414. 

  414. FLAG(   A,  0, EBX, INTEL,   3,  1, PMC_LAST_LVL_CREF,             NA,  FALSE) \
    415. 

  415. FLAG(   A,  0, EBX, INTEL,   4,  1, PMC_LAST_LVL_CMISS,            NA,  FALSE) \
    416. 

  416. FLAG(   A,  0, EBX, INTEL,   5,  1, PMC_BR_INST_RETIRED,           NA,  FALSE) \
    417. 

  417. FLAG(   A,  0, EBX, INTEL,   6,  1, PMC_BR_MISS_RETIRED,           NA,  FALSE) \
    418. 

  418. FIELD(  A,  0, EDX, INTEL,   0,  5, PMC_NUM_FIXED,                 NA,  FALSE) \
    419. 

  419. FIELD(  A,  0, EDX, INTEL,   5,  8, PMC_WIDTH_FIXED,               NA,  FALSE)
    420. 

  420. 

  421. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    422. 

  422. #define CPUID_FIELD_DATA_LEVEL_B                                               \
    423. 

  423. FIELD(  B,  0, EAX, INTEL,   0,  5, TOPOLOGY_MASK_WIDTH,           NA,  FALSE) \
    424. 

  424. FIELD(  B,  0, EBX, INTEL,   0, 16, TOPOLOGY_CPUS_SHARING_LEVEL,   NA,  FALSE) \
    425. 

  425. FIELD(  B,  0, ECX, INTEL,   0,  8, TOPOLOGY_LEVEL_NUMBER,         NA,  FALSE) \
    426. 

  426. FIELD(  B,  0, ECX, INTEL,   8,  8, TOPOLOGY_LEVEL_TYPE,           NA,  FALSE) \
    427. 

  427. FIELD(  B,  0, EDX, INTEL,   0, 32, TOPOLOGY_X2APIC_ID,            NA,  FALSE)
    428. 

  428. 

  429. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    430. 

  430. #define CPUID_FIELD_DATA_LEVEL_D                                               \
    431. 

  431. FLAG(   D,  0, EAX, COMMON,  0,  1, XCR0_MASTER_LEGACY_FP,         YES, FALSE) \
    432. 

  432. FLAG(   D,  0, EAX, COMMON,  1,  1, XCR0_MASTER_SSE,               YES, FALSE) \
    433. 

  433. FLAG(   D,  0, EAX, COMMON,  2,  1, XCR0_MASTER_YMM_H,             YES, FALSE) \
    434. 

  434. FIELD(  D,  0, EAX, COMMON,  3, 29, XCR0_MASTER_LOWER,             NO,  FALSE) \
    435. 

  435. FIELD(  D,  0, EBX, COMMON,  0, 32, XSAVE_ENABLED_SIZE,            ANY, FALSE) \
    436. 

  436. FIELD(  D,  0, ECX, COMMON,  0, 32, XSAVE_MAX_SIZE,                YES, FALSE) \
    437. 

  437. FIELD(  D,  0, EDX, COMMON,  0, 29, XCR0_MASTER_UPPER,             NO,  FALSE) \
    438. 

  438. FLAG(   D,  0, EDX, AMD,     30, 1, XCR0_MASTER_LWP,               NO,  FALSE) \
    439. 

  439. FLAG(   D,  0, EDX, COMMON,  31, 1, XCR0_MASTER_EXTENDED_XSAVE,    NO,  FALSE) \
    440. 

  440. FLAG(   D,  1, EAX, COMMON,  0,  1, XSAVEOPT,                      NO,  FALSE) \
    441. 

  441. FIELD(  D,  2, EAX, COMMON,  0, 32, XSAVE_YMM_SIZE,                YES, FALSE) \
    442. 

  442. FIELD(  D,  2, EBX, COMMON,  0, 32, XSAVE_YMM_OFFSET,              YES, FALSE) \
    443. 

  443. FIELD(  D,  2, ECX, COMMON,  0, 32, XSAVE_YMM_RSVD1,               YES, FALSE) \
    444. 

  444. FIELD(  D,  2, EDX, COMMON,  0, 32, XSAVE_YMM_RSVD2,               YES, FALSE) \
    445. 

  445. FIELD(  D, 62, EAX, AMD,     0, 32, XSAVE_LWP_SIZE,                NO,  FALSE) \
    446. 

  446. FIELD(  D, 62, EBX, AMD,     0, 32, XSAVE_LWP_OFFSET,              NO,  FALSE) \
    447. 

  447. FIELD(  D, 62, ECX, AMD,     0, 32, XSAVE_LWP_RSVD1,               NO,  FALSE) \
    448. 

  448. FIELD(  D, 62, EDX, AMD,     0, 32, XSAVE_LWP_RSVD2,               NO,  FALSE)
    449. 

  449. 

  450. 

  451. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    452. 

  452. #define CPUID_FIELD_DATA_LEVEL_400                                             \
    453. 

  453. FIELD(400,  0, EAX, COMMON,  0, 32, NUM_HYP_LEVELS,                NA,  FALSE) \
    454. 

  454. FIELD(400,  0, EBX, COMMON,  0, 32, HYPERVISOR1,                   NA,  FALSE) \
    455. 

  455. FIELD(400,  0, ECX, COMMON,  0, 32, HYPERVISOR2,                   NA,  FALSE) \
    456. 

  456. FIELD(400,  0, EDX, COMMON,  0, 32, HYPERVISOR3,                   NA,  FALSE)
    457. 

  457. 

  458. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    459. 

  459. #define CPUID_FIELD_DATA_LEVEL_410                                             \
    460. 

  460. FIELD(410,  0, EAX, COMMON,  0, 32, TSC_HZ,                        NA,  FALSE) \
    461. 

  461. FIELD(410,  0, EBX, COMMON,  0, 32, ACPIBUS_HZ,                    NA,  FALSE)
    462. 

  462. 

  463. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    464. 

  464. #define CPUID_FIELD_DATA_LEVEL_80                                              \
    465. 

  465. FIELD( 80,  0, EAX, COMMON,  0, 32, NUM_EXT_LEVELS,                NA,  FALSE) \
    466. 

  466. FIELD( 80,  0, EBX, AMD,     0, 32, LEAF80_VENDOR1,                NA,  FALSE) \
    467. 

  467. FIELD( 80,  0, ECX, AMD,     0, 32, LEAF80_VENDOR3,                NA,  FALSE) \
    468. 

  468. FIELD( 80,  0, EDX, AMD,     0, 32, LEAF80_VENDOR2,                NA,  FALSE)
    469. 

  469. 

  470. #define CPUID_81_ECX_17
    471. 

  471. 

  472.                                                         
    473. 

  473. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    474. 

  474. #define CPUID_FIELD_DATA_LEVEL_81                                              \
    475. 

  475. FIELD( 81,  0, EAX, INTEL,   0, 32, UNKNOWN81EAX,                  ANY, FALSE) \
    476. 

  476. FIELD( 81,  0, EAX, AMD,     0,  4, LEAF81_STEPPING,               ANY, FALSE) \
    477. 

  477. FIELD( 81,  0, EAX, AMD,     4,  4, LEAF81_MODEL,                  ANY, FALSE) \
    478. 

  478. FIELD( 81,  0, EAX, AMD,     8,  4, LEAF81_FAMILY,                 ANY, FALSE) \
    479. 

  479. FIELD( 81,  0, EAX, AMD,    12,  2, LEAF81_TYPE,                   ANY, FALSE) \
    480. 

  480. FIELD( 81,  0, EAX, AMD,    16,  4, LEAF81_EXTENDED_MODEL,         ANY, FALSE) \
    481. 

  481. FIELD( 81,  0, EAX, AMD,    20,  8, LEAF81_EXTENDED_FAMILY,        ANY, FALSE) \
    482. 

  482. FIELD( 81,  0, EBX, INTEL,   0, 32, UNKNOWN81EBX,                  ANY, FALSE) \
    483. 

  483. FIELD( 81,  0, EBX, AMD,     0, 16, LEAF81_BRAND_ID,               ANY, FALSE) \
    484. 

  484. FIELD( 81,  0, EBX, AMD,    16, 16, UNDEF,                         ANY, FALSE) \
    485. 

  485. FLAG(  81,  0, ECX, COMMON,  0,  1, LAHF64,                        YES, TRUE)  \
    486. 

  486. FLAG(  81,  0, ECX, AMD,     1,  1, CMPLEGACY,                     ANY, FALSE) \
    487. 

  487. FLAG(  81,  0, ECX, AMD,     2,  1, SVM,                           YES, FALSE) \
    488. 

  488. FLAG(  81,  0, ECX, AMD,     3,  1, EXTAPICSPC,                    YES, FALSE) \
    489. 

  489. FLAG(  81,  0, ECX, AMD,     4,  1, CR8AVAIL,                      YES, FALSE) \
    490. 

  490. FLAG(  81,  0, ECX, AMD,     5,  1, ABM,                           YES, TRUE)  \
    491. 

  491. FLAG(  81,  0, ECX, AMD,     6,  1, SSE4A,                         YES, TRUE)  \
    492. 

  492. FLAG(  81,  0, ECX, AMD,     7,  1, MISALIGNED_SSE,                YES, TRUE)  \
    493. 

  493. FLAG(  81,  0, ECX, AMD,     8,  1, 3DNPREFETCH,                   YES, TRUE)  \
    494. 

  494. FLAG(  81,  0, ECX, AMD,     9,  1, OSVW,                          ANY, FALSE) \
    495. 

  495. FLAG(  81,  0, ECX, AMD,    10,  1, IBS,                           NO,  FALSE) \
    496. 

  496. FLAG(  81,  0, ECX, AMD,    11,  1, XOP,                           YES, TRUE)  \
    497. 

  497. FLAG(  81,  0, ECX, AMD,    12,  1, SKINIT,                        NO,  FALSE) \
    498. 

  498. FLAG(  81,  0, ECX, AMD,    13,  1, WATCHDOG,                      NO,  FALSE) \
    499. 

  499. FLAG(  81,  0, ECX, AMD,    15,  1, LWP,                           NO,  FALSE) \
    500. 

  500. FLAG(  81,  0, ECX, AMD,    16,  1, FMA4,                          YES, TRUE)  \
    501. 

  501. CPUID_81_ECX_17 \
    502. 

  502. FLAG(  81,  0, ECX, AMD,    19,  1, NODEID_MSR,                    NO,  FALSE) \
    503. 

  503. FLAG(  81,  0, ECX, AMD,    21,  1, TBM,                           YES, TRUE)  \
    504. 

  504. FLAG(  81,  0, ECX, AMD,    22,  1, TOPOLOGY,                      NO,  FALSE) \
    505. 

  505. FLAG(  81,  0, EDX, AMD,     0,  1, LEAF81_FPU,                    YES, TRUE)  \
    506. 

  506. FLAG(  81,  0, EDX, AMD,     1,  1, LEAF81_VME,                    YES, FALSE) \
    507. 

  507. FLAG(  81,  0, EDX, AMD,     2,  1, LEAF81_DE,                     YES, FALSE) \
    508. 

  508. FLAG(  81,  0, EDX, AMD,     3,  1, LEAF81_PSE,                    YES, FALSE) \
    509. 

  509. FLAG(  81,  0, EDX, AMD,     4,  1, LEAF81_TSC,                    YES, TRUE)  \
    510. 

  510. FLAG(  81,  0, EDX, AMD,     5,  1, LEAF81_MSR,                    YES, FALSE) \
    511. 

  511. FLAG(  81,  0, EDX, AMD,     6,  1, LEAF81_PAE,                    YES, FALSE) \
    512. 

  512. FLAG(  81,  0, EDX, AMD,     7,  1, LEAF81_MCE,                    YES, FALSE) \
    513. 

  513. FLAG(  81,  0, EDX, AMD,     8,  1, LEAF81_CX8,                    YES, TRUE)  \
    514. 

  514. FLAG(  81,  0, EDX, AMD,     9,  1, LEAF81_APIC,                   ANY, FALSE) \
    515. 

  515. FLAG(  81,  0, EDX, COMMON, 11,  1, SYSC,                          ANY, TRUE)  \
    516. 

  516. FLAG(  81,  0, EDX, AMD,    12,  1, LEAF81_MTRR,                   YES, FALSE) \
    517. 

  517. FLAG(  81,  0, EDX, AMD,    13,  1, LEAF81_PGE,                    YES, FALSE) \
    518. 

  518. FLAG(  81,  0, EDX, AMD,    14,  1, LEAF81_MCA,                    YES, FALSE) \
    519. 

  519. FLAG(  81,  0, EDX, AMD,    15,  1, LEAF81_CMOV,                   YES, TRUE)  \
    520. 

  520. FLAG(  81,  0, EDX, AMD,    16,  1, LEAF81_PAT,                    YES, FALSE) \
    521. 

  521. FLAG(  81,  0, EDX, AMD,    17,  1, LEAF81_PSE36,                  YES, FALSE) \
    522. 

  522. FLAG(  81,  0, EDX, COMMON, 20,  1, NX,                            YES, FALSE) \
    523. 

  523. FLAG(  81,  0, EDX, AMD,    22,  1, MMXEXT,                        YES, TRUE)  \
    524. 

  524. FLAG(  81,  0, EDX, AMD,    23,  1, LEAF81_MMX,                    YES, TRUE)  \
    525. 

  525. FLAG(  81,  0, EDX, AMD,    24,  1, LEAF81_FXSR,                   YES, TRUE)  \
    526. 

  526. FLAG(  81,  0, EDX, AMD,    25,  1, FFXSR,                         YES, FALSE) \
    527. 

  527. FLAG(  81,  0, EDX, COMMON, 26,  1, PDPE1GB,                       YES, FALSE) \
    528. 

  528. FLAG(  81,  0, EDX, COMMON, 27,  1, RDTSCP,                        YES, TRUE)  \
    529. 

  529. FLAG(  81,  0, EDX, COMMON, 29,  1, LM,                            YES, FALSE) \
    530. 

  530. FLAG(  81,  0, EDX, AMD,    30,  1, 3DNOWPLUS,                     YES, TRUE)  \
    531. 

  531. FLAG(  81,  0, EDX, AMD,    31,  1, 3DNOW,                         YES, TRUE)
    532. 

  532. 

  533. #define CPUID_8A_EDX_11 \
    534. 

  534. FLAG(  8A,  0, EDX, AMD,    11,  1, SVMEDX_RSVD1,                      NO,  FALSE)
    535. 

  535. #define CPUID_8A_EDX_13_31 \
    536. 

  536. FIELD( 8A,  0, EDX, AMD,    13, 19, SVMEDX_RSVD2,                      NO,  FALSE)
    537. 

  537. 

  538. /*    LEVEL, REG, VENDOR, POS, SIZE, NAME,                   MON SUPP, CPL3 */
    539. 

  539. #define CPUID_FIELD_DATA_LEVEL_8x                                              \
    540. 

  540. FIELD( 85,  0, EAX, AMD,     0,  8, ITLB_ENTRIES_2M4M_PGS,         NA,  FALSE) \
    541. 

  541. FIELD( 85,  0, EAX, AMD,     8,  8, ITLB_ASSOC_2M4M_PGS,           NA,  FALSE) \
    542. 

  542. FIELD( 85,  0, EAX, AMD,    16,  8, DTLB_ENTRIES_2M4M_PGS,         NA,  FALSE) \
    543. 

  543. FIELD( 85,  0, EAX, AMD,    24,  8, DTLB_ASSOC_2M4M_PGS,           NA,  FALSE) \
    544. 

  544. FIELD( 85,  0, EBX, AMD,     0,  8, ITLB_ENTRIES_4K_PGS,           NA,  FALSE) \
    545. 

  545. FIELD( 85,  0, EBX, AMD,     8,  8, ITLB_ASSOC_4K_PGS,             NA,  FALSE) \
    546. 

  546. FIELD( 85,  0, EBX, AMD,    16,  8, DTLB_ENTRIES_4K_PGS,           NA,  FALSE) \
    547. 

  547. FIELD( 85,  0, EBX, AMD,    24,  8, DTLB_ASSOC_4K_PGS,             NA,  FALSE) \
    548. 

  548. FIELD( 85,  0, ECX, AMD,     0,  8, L1_DCACHE_LINE_SIZE,           NA,  FALSE) \
    549. 

  549. FIELD( 85,  0, ECX, AMD,     8,  8, L1_DCACHE_LINES_PER_TAG,       NA,  FALSE) \
    550. 

  550. FIELD( 85,  0, ECX, AMD,    16,  8, L1_DCACHE_ASSOC,               NA,  FALSE) \
    551. 

  551. FIELD( 85,  0, ECX, AMD,    24,  8, L1_DCACHE_SIZE,                NA,  FALSE) \
    552. 

  552. FIELD( 85,  0, EDX, AMD,     0,  8, L1_ICACHE_LINE_SIZE,           NA,  FALSE) \
    553. 

  553. FIELD( 85,  0, EDX, AMD,     8,  8, L1_ICACHE_LINES_PER_TAG,       NA,  FALSE) \
    554. 

  554. FIELD( 85,  0, EDX, AMD,    16,  8, L1_ICACHE_ASSOC,               NA,  FALSE) \
    555. 

  555. FIELD( 85,  0, EDX, AMD,    24,  8, L1_ICACHE_SIZE,                NA,  FALSE) \
    556. 

  556. FIELD( 86,  0, EAX, AMD,     0, 12, L2_ITLB_ENTRIES_2M4M_PGS,      NA,  FALSE) \
    557. 

  557. FIELD( 86,  0, EAX, AMD,    12,  4, L2_ITLB_ASSOC_2M4M_PGS,        NA,  FALSE) \
    558. 

  558. FIELD( 86,  0, EAX, AMD,    16, 12, L2_DTLB_ENTRIES_2M4M_PGS,      NA,  FALSE) \
    559. 

  559. FIELD( 86,  0, EAX, AMD,    28,  4, L2_DTLB_ASSOC_2M4M_PGS,        NA,  FALSE) \
    560. 

  560. FIELD( 86,  0, EBX, AMD,     0, 12, L2_ITLB_ENTRIES_4K_PGS,        NA,  FALSE) \
    561. 

  561. FIELD( 86,  0, EBX, AMD,    12,  4, L2_ITLB_ASSOC_4K_PGS,          NA,  FALSE) \
    562. 

  562. FIELD( 86,  0, EBX, AMD,    16, 12, L2_DTLB_ENTRIES_4K_PGS,        NA,  FALSE) \
    563. 

  563. FIELD( 86,  0, EBX, AMD,    28,  4, L2_DTLB_ASSOC_4K_PGS,          NA,  FALSE) \
    564. 

  564. FIELD( 86,  0, ECX, AMD,     0,  8, L2CACHE_LINE,                  NA,  FALSE) \
    565. 

  565. FIELD( 86,  0, ECX, AMD,     8,  4, L2CACHE_LINE_PER_TAG,          NA,  FALSE) \
    566. 

  566. FIELD( 86,  0, ECX, AMD,    12,  4, L2CACHE_WAYS,                  NA,  FALSE) \
    567. 

  567. FIELD( 86,  0, ECX, AMD,    16, 16, L2CACHE_SIZE,                  NA,  FALSE) \
    568. 

  568. FIELD( 86,  0, EDX, AMD,     0,  8, L3CACHE_LINE,                  NA,  FALSE) \
    569. 

  569. FIELD( 86,  0, EDX, AMD,     8,  4, L3CACHE_LINE_PER_TAG,          NA,  FALSE) \
    570. 

  570. FIELD( 86,  0, EDX, AMD,    12,  4, L3CACHE_WAYS,                  NA,  FALSE) \
    571. 

  571. FIELD( 86,  0, EDX, AMD,    18, 14, L3CACHE_SIZE,                  NA,  FALSE) \
    572. 

  572. FLAG(  87,  0, EDX, AMD,     0,  1, TS,                            NA,  FALSE) \
    573. 

  573. FLAG(  87,  0, EDX, AMD,     1,  1, FID,                           NA,  FALSE) \
    574. 

  574. FLAG(  87,  0, EDX, AMD,     2,  1, VID,                           NA,  FALSE) \
    575. 

  575. FLAG(  87,  0, EDX, AMD,     3,  1, TTP,                           NA,  FALSE) \
    576. 

  576. FLAG(  87,  0, EDX, AMD,     4,  1, LEAF87_TM,                     NA,  FALSE) \
    577. 

  577. FLAG(  87,  0, EDX, AMD,     5,  1, STC,                           NA,  FALSE) \
    578. 

  578. FLAG(  87,  0, EDX, AMD,     6,  1, 100MHZSTEPS,                   NA,  FALSE) \
    579. 

  579. FLAG(  87,  0, EDX, AMD,     7,  1, HWPSTATE,                      NA,  FALSE) \
    580. 

  580. FLAG(  87,  0, EDX, COMMON,  8,  1, TSC_INVARIANT,                 NA,  FALSE) \
    581. 

  581. FLAG(  87,  0, EDX, COMMON,  9,  1, CORE_PERF_BOOST,               NA,  FALSE) \
    582. 

  582. FIELD( 88,  0, EAX, COMMON,  0,  8, PHYS_BITS,                     NA,  FALSE) \
    583. 

  583. FIELD( 88,  0, EAX, COMMON,  8,  8, VIRT_BITS,                     NA,  FALSE) \
    584. 

  584. FIELD( 88,  0, EAX, COMMON, 16,  8, GUEST_PHYS_ADDR_SZ,            NA,  FALSE) \
    585. 

  585. FIELD( 88,  0, ECX, AMD,     0,  8, LEAF88_CORE_COUNT,             NA,  FALSE) \
    586. 

  586. FIELD( 88,  0, ECX, AMD,    12,  4, APICID_COREID_SIZE,            NA,  FALSE) \
    587. 

  587. FIELD( 8A,  0, EAX, AMD,     0,  8, SVM_REVISION,                  YES, FALSE) \
    588. 

  588. FLAG(  8A,  0, EAX, AMD,     8,  1, SVM_HYPERVISOR,                NO,  FALSE) \
    589. 

  589. FIELD( 8A,  0, EAX, AMD,     9, 23, SVMEAX_RSVD,                   NO,  FALSE) \
    590. 

  590. FIELD( 8A,  0, EBX, AMD,     0, 32, SVM_NUM_ASIDS,                 YES, FALSE) \
    591. 

  591. FIELD( 8A,  0, ECX, AMD,     0, 32, SVMECX_RSVD,                   NO,  FALSE) \
    592. 

  592. FLAG(  8A,  0, EDX, AMD,     0,  1, SVM_NPT,                       YES, FALSE) \
    593. 

  593. FLAG(  8A,  0, EDX, AMD,     1,  1, SVM_LBR,                       NO,  FALSE) \
    594. 

  594. FLAG(  8A,  0, EDX, AMD,     2,  1, SVM_LOCK,                      ANY, FALSE) \
    595. 

  595. FLAG(  8A,  0, EDX, AMD,     3,  1, SVM_NRIP,                      YES, FALSE) \
    596. 

  596. FLAG(  8A,  0, EDX, AMD,     4,  1, SVM_TSC_RATE_MSR,              NO,  FALSE) \
    597. 

  597. FLAG(  8A,  0, EDX, AMD,     5,  1, SVM_VMCB_CLEAN,                YES, FALSE) \
    598. 

  598. FLAG(  8A,  0, EDX, AMD,     6,  1, SVM_FLUSH_BY_ASID,             YES, FALSE) \
    599. 

  599. FLAG(  8A,  0, EDX, AMD,     7,  1, SVM_DECODE_ASSISTS,            YES, FALSE) \
    600. 

  600. FIELD( 8A,  0, EDX, AMD,     8,  2, SVMEDX_RSVD0,                  NO,  FALSE) \
    601. 

  601. FLAG(  8A,  0, EDX, AMD,    10,  1, SVM_PAUSE_FILTER,              NO,  FALSE) \
    602. 

  602. CPUID_8A_EDX_11 \
    603. 

  603. FLAG(  8A,  0, EDX, AMD,    12,  1, SVM_PAUSE_THRESHOLD,           NO,  FALSE) \
    604. 

  604. CPUID_8A_EDX_13_31
    605. 

  605. 

  606. /*    LEVEL, SUB-LEVEL, REG, VENDOR, POS, SIZE, NAME,        MON SUPP, CPL3 */
    607. 

  607. #define CPUID_FIELD_DATA_LEVEL_81x                                             \
    608. 

  608. FIELD(819,  0, EAX, AMD,     0, 12, L1_ITLB_ENTRIES_1G_PGS,        NA,  FALSE) \
    609. 

  609. FIELD(819,  0, EAX, AMD,    12,  4, L1_ITLB_ASSOC_1G_PGS,          NA,  FALSE) \
    610. 

  610. FIELD(819,  0, EAX, AMD,    16, 12, L1_DTLB_ENTRIES_1G_PGS,        NA,  FALSE) \
    611. 

  611. FIELD(819,  0, EAX, AMD,    28,  4, L1_DTLB_ASSOC_1G_PGS,          NA,  FALSE) \
    612. 

  612. FIELD(819,  0, EBX, AMD,     0, 12, L2_ITLB_ENTRIES_1G_PGS,        NA,  FALSE) \
    613. 

  613. FIELD(819,  0, EBX, AMD,    12,  4, L2_ITLB_ASSOC_1G_PGS,          NA,  FALSE) \
    614. 

  614. FIELD(819,  0, EBX, AMD,    16, 12, L2_DTLB_ENTRIES_1G_PGS,        NA,  FALSE) \
    615. 

  615. FIELD(819,  0, EBX, AMD,    28,  4, L2_DTLB_ASSOC_1G_PGS,          NA,  FALSE) \
    616. 

  616. FLAG( 81A,  0, EAX, AMD,     0,  1, FP128,                         NA,  FALSE) \
    617. 

  617. FLAG( 81A,  0, EAX, AMD,     1,  1, MOVU,                          NA,  FALSE) \
    618. 

  618. FLAG( 81B,  0, EAX, AMD,     0,  1, IBS_FFV,                       NA,  FALSE) \
    619. 

  619. FLAG( 81B,  0, EAX, AMD,     1,  1, IBS_FETCHSAM,                  NA,  FALSE) \
    620. 

  620. FLAG( 81B,  0, EAX, AMD,     2,  1, IBS_OPSAM,                     NA,  FALSE) \
    621. 

  621. FLAG( 81B,  0, EAX, AMD,     3,  1, RW_OPCOUNT,                    NA,  FALSE) \
    622. 

  622. FLAG( 81B,  0, EAX, AMD,     4,  1, OPCOUNT,                       NA,  FALSE) \
    623. 

  623. FLAG( 81B,  0, EAX, AMD,     5,  1, BRANCH_TARGET_ADDR,            NA,  FALSE) \
    624. 

  624. FLAG( 81B,  0, EAX, AMD,     6,  1, OPCOUNT_EXT,                   NA,  FALSE) \
    625. 

  625. FLAG( 81B,  0, EAX, AMD,     7,  1, RIP_INVALID_CHECK,             NA,  FALSE) \
    626. 

  626. FLAG( 81C,  0, EAX, AMD,     0,  1, LWP_AVAIL,                     NA,  FALSE) \
    627. 

  627. FLAG( 81C,  0, EAX, AMD,     1,  1, LWP_VAL_AVAIL,                 NA,  FALSE) \
    628. 

  628. FLAG( 81C,  0, EAX, AMD,     2,  1, LWP_IRE_AVAIL,                 NA,  FALSE) \
    629. 

  629. FLAG( 81C,  0, EAX, AMD,     3,  1, LWP_BRE_AVAIL,                 NA,  FALSE) \
    630. 

  630. FLAG( 81C,  0, EAX, AMD,     4,  1, LWP_DME_AVAIL,                 NA,  FALSE) \
    631. 

  631. FLAG( 81C,  0, EAX, AMD,     5,  1, LWP_CNH_AVAIL,                 NA,  FALSE) \
    632. 

  632. FLAG( 81C,  0, EAX, AMD,     6,  1, LWP_RNH_AVAIL,                 NA,  FALSE) \
    633. 

  633. FLAG( 81C,  0, EAX, AMD,    31,  1, LWP_INT_AVAIL,                 NA,  FALSE) \
    634. 

  634. FIELD(81C,  0, EBX, AMD,     0,  8, LWP_CB_SIZE,                   NA,  FALSE) \
    635. 

  635. FIELD(81C,  0, EBX, AMD,     8,  8, LWP_EVENT_SIZE,                NA,  FALSE) \
    636. 

  636. FIELD(81C,  0, EBX, AMD,    16,  8, LWP_MAX_EVENTS,                NA,  FALSE) \
    637. 

  637. FIELD(81C,  0, EBX, AMD,    24,  8, LWP_EVENT_OFFSET,              NA,  FALSE) \
    638. 

  638. FIELD(81C,  0, ECX, AMD,     0,  4, LWP_LATENCY_MAX,               NA,  FALSE) \
    639. 

  639. FLAG( 81C,  0, ECX, AMD,     5,  1, LWP_DATA_ADDR_VALID,           NA,  FALSE) \
    640. 

  640. FIELD(81C,  0, ECX, AMD,     6,  3, LWP_LATENCY_ROUND,             NA,  FALSE) \
    641. 

  641. FIELD(81C,  0, ECX, AMD,     9,  7, LWP_VERSION,                   NA,  FALSE) \
    642. 

  642. FIELD(81C,  0, ECX, AMD,    16,  8, LWP_MIN_BUF_SIZE,              NA,  FALSE) \
    643. 

  643. FLAG( 81C,  0, ECX, AMD,    28,  1, LWP_BRANCH_PRED,               NA,  FALSE) \
    644. 

  644. FLAG( 81C,  0, ECX, AMD,    29,  1, LWP_IP_FILTERING,              NA,  FALSE) \
    645. 

  645. FLAG( 81C,  0, ECX, AMD,    30,  1, LWP_CACHE_LEVEL,               NA,  FALSE) \
    646. 

  646. FLAG( 81C,  0, ECX, AMD,    31,  1, LWP_CACHE_LATENCY,             NA,  FALSE) \
    647. 

  647. FLAG( 81C,  0, EDX, AMD,     0,  1, LWP_SUPPORTED,                 NA,  FALSE) \
    648. 

  648. FLAG( 81C,  0, EDX, AMD,     1,  1, LWP_VAL_SUPPORTED,             NA,  FALSE) \
    649. 

  649. FLAG( 81C,  0, EDX, AMD,     2,  1, LWP_IRE_SUPPORTED,             NA,  FALSE) \
    650. 

  650. FLAG( 81C,  0, EDX, AMD,     3,  1, LWP_BRE_SUPPORTED,             NA,  FALSE) \
    651. 

  651. FLAG( 81C,  0, EDX, AMD,     4,  1, LWP_DME_SUPPORTED,             NA,  FALSE) \
    652. 

  652. FLAG( 81C,  0, EDX, AMD,     5,  1, LWP_CNH_SUPPORTED,             NA,  FALSE) \
    653. 

  653. FLAG( 81C,  0, EDX, AMD,     6,  1, LWP_RNH_SUPPORTED,             NA,  FALSE) \
    654. 

  654. FLAG( 81C,  0, EDX, AMD,    31,  1, LWP_INT_SUPPORTED,             NA,  FALSE) \
    655. 

  655. FIELD(81D,  0, EAX, AMD,     0,  5, LEAF81D_CACHE_TYPE,            NA,  FALSE) \
    656. 

  656. FIELD(81D,  0, EAX, AMD,     5,  3, LEAF81D_CACHE_LEVEL,           NA,  FALSE) \
    657. 

  657. FLAG( 81D,  0, EAX, AMD,     8,  1, LEAF81D_CACHE_SELF_INIT,       NA,  FALSE) \
    658. 

  658. FLAG( 81D,  0, EAX, AMD,     9,  1, LEAF81D_CACHE_FULLY_ASSOC,     NA,  FALSE) \
    659. 

  659. FIELD(81D,  0, EAX, AMD,    14, 12, LEAF81D_NUM_SHARING_CACHE,     NA,  FALSE) \
    660. 

  660. FIELD(81D,  0, EBX, AMD,     0, 12, LEAF81D_CACHE_LINE_SIZE,       NA,  FALSE) \
    661. 

  661. FIELD(81D,  0, EBX, AMD,    12, 10, LEAF81D_CACHE_PHYS_PARTITIONS, NA,  FALSE) \
    662. 

  662. FIELD(81D,  0, EBX, AMD,    22, 10, LEAF81D_CACHE_WAYS,            NA,  FALSE) \
    663. 

  663. FIELD(81D,  0, ECX, AMD,     0, 32, LEAF81D_CACHE_NUM_SETS,        NA,  FALSE) \
    664. 

  664. FLAG( 81D,  0, EDX, AMD,     0,  1, LEAF81D_CACHE_WBINVD,          NA,  FALSE) \
    665. 

  665. FLAG( 81D,  0, EDX, AMD,     1,  1, LEAF81D_CACHE_INCLUSIVE,       NA,  FALSE) \
    666. 

  666. FIELD(81E,  0, EAX, AMD,     0, 32, EXTENDED_APICID,               NA,  FALSE) \
    667. 

  667. FIELD(81E,  0, EBX, AMD,     0,  8, COMPUTE_UNIT_ID,               NA,  FALSE) \
    668. 

  668. FIELD(81E,  0, EBX, AMD,     8,  2, CORES_PER_COMPUTE_UNIT,        NA,  FALSE) \
    669. 

  669. FIELD(81E,  0, ECX, AMD,     0,  8, NODEID_VAL,                    NA,  FALSE) \
    670. 

  670. FIELD(81E,  0, ECX, AMD,     8,  3, NODES_PER_PKG,                 NA,  FALSE)
    671. 

  671. 

  672. #define INTEL_CPUID_FIELD_DATA
    673. 

  673. 

  674. #define AMD_CPUID_FIELD_DATA
    675. 

  675. 

  676. #define CPUID_FIELD_DATA                                              \
    677. 

  677.    CPUID_FIELD_DATA_LEVEL_0                                           \
    678. 

  678.    CPUID_FIELD_DATA_LEVEL_1                                           \
    679. 

  679.    CPUID_FIELD_DATA_LEVEL_4                                           \
    680. 

  680.    CPUID_FIELD_DATA_LEVEL_5                                           \
    681. 

  681.    CPUID_FIELD_DATA_LEVEL_6                                           \
    682. 

  682.    CPUID_FIELD_DATA_LEVEL_7                                           \
    683. 

  683.    CPUID_FIELD_DATA_LEVEL_A                                           \
    684. 

  684.    CPUID_FIELD_DATA_LEVEL_B                                           \
    685. 

  685.    CPUID_FIELD_DATA_LEVEL_D                                           \
    686. 

  686.    CPUID_FIELD_DATA_LEVEL_400                                         \
    687. 

  687.    CPUID_FIELD_DATA_LEVEL_410                                         \
    688. 

  688.    CPUID_FIELD_DATA_LEVEL_80                                          \
    689. 

  689.    CPUID_FIELD_DATA_LEVEL_81                                          \
    690. 

  690.    CPUID_FIELD_DATA_LEVEL_8x                                          \
    691. 

  691.    CPUID_FIELD_DATA_LEVEL_81x                                         \
    692. 

  692.    INTEL_CPUID_FIELD_DATA                                             \
    693. 

  693.    AMD_CPUID_FIELD_DATA
    694. 

  694. 

  695. /*
    696. 

  696.  * Define all field and flag values as an enum.  The result is a full
    697. 

  697.  * set of values taken from the table above in the form:
    698. 

  698.  *
    699. 

  699.  * CPUID_FEATURE_<vendor>_ID<level><reg>_<name> == mask for feature
    700. 

  700.  * CPUID_<vendor>_ID<level><reg>_<name>_MASK    == mask for field
    701. 

  701.  * CPUID_<vendor>_ID<level><reg>_<name>_SHIFT   == offset of field
    702. 

  702.  *
    703. 

  703.  * e.g. - CPUID_FEATURE_COMMON_ID1EDX_FPU     = 0x1
    704. 

  704.  *      - CPUID_COMMON_ID88EAX_VIRT_BITS_MASK  = 0xff00
    705. 

  705.  *      - CPUID_COMMON_ID88EAX_VIRT_BITS_SHIFT = 8
    706. 

  706.  *
    707. 

  707.  * Note: The FEATURE/MASK definitions must use some gymnastics to get
    708. 

  708.  * around a warning when shifting left by 32.
    709. 

  709.  */
    710. 

  710. #define VMW_BIT_MASK(shift)  (((1 << (shift - 1)) << 1) - 1)
    711. 

  711. 

  712. #define FIELD(lvl, ecxIn, reg, vend, bitpos, size, name, s, c3)       \
    713. 

  713.    CPUID_##vend##_ID##lvl##reg##_##name##_SHIFT = bitpos,             \
    714. 

  714.    CPUID_##vend##_ID##lvl##reg##_##name##_MASK  =                     \
    715. 

  715.                       VMW_BIT_MASK(size) << bitpos,                   \
    716. 

  716.    CPUID_FEATURE_##vend##_ID##lvl##reg##_##name =                     \
    717. 

  717.       CPUID_##vend##_ID##lvl##reg##_##name##_MASK,                    \
    718. 

  718.    CPUID_INTERNAL_SHIFT_##name  = bitpos,                             \
    719. 

  719.    CPUID_INTERNAL_MASK_##name   = VMW_BIT_MASK(size) << bitpos,       \
    720. 

  720.    CPUID_INTERNAL_REG_##name    = CPUID_REG_##reg,                    \
    721. 

  721.    CPUID_INTERNAL_EAXIN_##name  = CPUID_LEVEL_VAL_##lvl,              \
    722. 

  722.    CPUID_INTERNAL_ECXIN_##name  = ecxIn,
    723. 

  723. 

  724. #define FLAG FIELD
    725. 

  725. 

  726. enum {
    727. 

  727.    /* Define data for every CPUID field we have */
    728. 

  728.    CPUID_FIELD_DATA
    729. 

  729. };
    730. 

  730. #undef VMW_BIT_MASK
    731. 

  731. #undef FIELD
    732. 

  732. #undef FLAG
    733. 

  733. 

  734. /* Level D subleaf 1 eax XSAVEOPT */
    735. 

  735. #define CPUID_COMMON_IDDsub1EAX_XSAVEOPT 1
    736. 

  736. 

  737. /*
    738. 

  738.  * Legal CPUID config file mask characters.  For a description of the
    739. 

  739.  * cpuid masking system, please see:
    740. 

  740.  *
    741. 

  741.  * http://vmweb.vmware.com/~mts/cgi-bin/view.cgi/Apps/CpuMigrationChecks
    742. 

  742.  */
    743. 

  743. 

  744. #define CPUID_MASK_HIDE_CHR    '0'
    745. 

  745. #define CPUID_MASK_HIDE_STR    "0"
    746. 

  746. #define CPUID_MASK_FORCE_CHR   '1'
    747. 

  747. #define CPUID_MASK_FORCE_STR   "1"
    748. 

  748. #define CPUID_MASK_PASS_CHR    '-'
    749. 

  749. #define CPUID_MASK_PASS_STR    "-"
    750. 

  750. #define CPUID_MASK_TRUE_CHR    'T'
    751. 

  751. #define CPUID_MASK_TRUE_STR    "T"
    752. 

  752. #define CPUID_MASK_FALSE_CHR   'F'
    753. 

  753. #define CPUID_MASK_FALSE_STR   "F"
    754. 

  754. #define CPUID_MASK_IGNORE_CHR  'X'
    755. 

  755. #define CPUID_MASK_IGNORE_STR  "X"
    756. 

  756. #define CPUID_MASK_HOST_CHR    'H'
    757. 

  757. #define CPUID_MASK_HOST_STR    "H"
    758. 

  758. #define CPUID_MASK_RSVD_CHR    'R'
    759. 

  759. #define CPUID_MASK_RSVD_STR    "R"
    760. 

  760. #define CPUID_MASK_INSTALL_CHR 'I'
    761. 

  761. #define CPUID_MASK_INSTALL_STR "I"
    762. 

  762. 

  763. /*
    764. 

  764.  * When LM is disabled, we overlay the following masks onto the
    765. 

  765.  * guest's default masks.  Any level that is not defined below should
    766. 

  766.  * be treated as all "-"s
    767. 

  767.  */
    768. 

  768. 

  769. #define CPT_ID1ECX_LM_DISABLED  "----:----:----:----:--0-:----:----:----"
    770. 

  770. #define CPT_ID81EDX_LM_DISABLED "--0-:----:----:----:----:----:----:----"
    771. 

  771. #define CPT_ID81ECX_LM_DISABLED "----:----:----:----:----:----:----:---0"
    772. 

  772. 

  773. #define CPT_GET_LM_DISABLED_MASK(lvl, reg)                                  \
    774. 

  774.    ((lvl == 1 && reg == CPUID_REG_ECX) ? CPT_ID1ECX_LM_DISABLED :           \
    775. 

  775.     (lvl == 0x80000001 && reg == CPUID_REG_ECX) ? CPT_ID81ECX_LM_DISABLED : \
    776. 

  776.     (lvl == 0x80000001 && reg == CPUID_REG_EDX) ? CPT_ID81EDX_LM_DISABLED : \
    777. 

  777.     NULL)
    778. 

  778. 

  779. /*
    780. 

  780.  * CPUID_MASK --
    781. 

  781.  * CPUID_SHIFT --
    782. 

  782.  * CPUID_ISSET --
    783. 

  783.  * CPUID_GET --
    784. 

  784.  * CPUID_SET --
    785. 

  785.  * CPUID_CLEAR --
    786. 

  786.  * CPUID_SETTO --
    787. 

  787.  *
    788. 

  788.  * Accessor macros for all CPUID consts/fields/flags.  Level and reg are not
    789. 

  789.  * required, but are used to force compile-time asserts which help verify that
    790. 

  790.  * the flag is being used on the right CPUID input and result register.
    791. 

  791.  *
    792. 

  792.  * Note: ASSERT_ON_COMPILE is duplicated rather than factored into its own
    793. 

  793.  * macro, because token concatenation does not work as expected if an input is
    794. 

  794.  * #defined (e.g. APIC) when macros are nested.  Also, compound statements
    795. 

  795.  * within parenthes is a GCC extension, so we must use runtime asserts with
    796. 

  796.  * other compilers.
    797. 

  797.  */
    798. 

  798. 

  799. #if defined(__GNUC__) && !defined(__clang__)
    800. 

  800. 

  801. #define CPUID_MASK(eaxIn, reg, flag)                                    \
    802. 

  802.    ({                                                                   \
    803. 

  803.       ASSERT_ON_COMPILE(eaxIn == CPUID_INTERNAL_EAXIN_##flag &&         \
    804. 

  804.               CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##flag);  \
    805. 

  805.       CPUID_INTERNAL_MASK_##flag;                                       \
    806. 

  806.    })
    807. 

  807. 

  808. #define CPUID_SHIFT(eaxIn, reg, flag)                                   \
    809. 

  809.    ({                                                                   \
    810. 

  810.       ASSERT_ON_COMPILE(eaxIn == CPUID_INTERNAL_EAXIN_##flag &&         \
    811. 

  811.               CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##flag);  \
    812. 

  812.       CPUID_INTERNAL_SHIFT_##flag;                                      \
    813. 

  813.    })
    814. 

  814. 

  815. #define CPUID_ISSET(eaxIn, reg, flag, data)                             \
    816. 

  816.    ({                                                                   \
    817. 

  817.       ASSERT_ON_COMPILE(eaxIn == CPUID_INTERNAL_EAXIN_##flag &&         \
    818. 

  818.               CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##flag);  \
    819. 

  819.       (((data) & CPUID_INTERNAL_MASK_##flag) != 0);                     \
    820. 

  820.    })
    821. 

  821. 

  822. #define CPUID_GET(eaxIn, reg, field, data)                              \
    823. 

  823.    ({                                                                   \
    824. 

  824.       ASSERT_ON_COMPILE(eaxIn == CPUID_INTERNAL_EAXIN_##field &&        \
    825. 

  825.               CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##field); \
    826. 

  826.       (((uint32)(data) & CPUID_INTERNAL_MASK_##field) >>                \
    827. 

  827.        CPUID_INTERNAL_SHIFT_##field);                                   \
    828. 

  828.    })
    829. 

  829. 

  830. #else
    831. 

  831. 

  832. /*
    833. 

  833.  * CPUIDCheck --
    834. 

  834.  *
    835. 

  835.  * Return val after verifying parameters.
    836. 

  836.  */
    837. 

  837. 

  838. static INLINE uint32
    839. 

  839. CPUIDCheck(uint32 eaxIn, uint32 eaxInCheck,
    840. 

  840.            CpuidReg reg, CpuidReg regCheck, uint32 val)
    841. 

  841. {
    842. 

  842.    ASSERT(eaxIn == eaxInCheck && reg == regCheck);
    843. 

  843.    return val;
    844. 

  844. }
    845. 

  845. 

  846. #define CPUID_MASK(eaxIn, reg, flag)                                    \
    847. 

  847.    CPUIDCheck((uint32)eaxIn, CPUID_INTERNAL_EAXIN_##flag,               \
    848. 

  848.               CPUID_REG_##reg, (CpuidReg)CPUID_INTERNAL_REG_##flag,     \
    849. 

  849.               CPUID_INTERNAL_MASK_##flag)
    850. 

  850. 

  851. #define CPUID_SHIFT(eaxIn, reg, flag)                                   \
    852. 

  852.    CPUIDCheck((uint32)eaxIn, CPUID_INTERNAL_EAXIN_##flag,               \
    853. 

  853.               CPUID_REG_##reg, (CpuidReg)CPUID_INTERNAL_REG_##flag,     \
    854. 

  854.               CPUID_INTERNAL_SHIFT_##flag)
    855. 

  855. 

  856. #define CPUID_ISSET(eaxIn, reg, flag, data)                             \
    857. 

  857.    (CPUIDCheck((uint32)eaxIn, CPUID_INTERNAL_EAXIN_##flag,              \
    858. 

  858.                CPUID_REG_##reg, (CpuidReg)CPUID_INTERNAL_REG_##flag,    \
    859. 

  859.                CPUID_INTERNAL_MASK_##flag & (data)) != 0)
    860. 

  860. 

  861. #define CPUID_GET(eaxIn, reg, field, data)                              \
    862. 

  862.    CPUIDCheck((uint32)eaxIn, CPUID_INTERNAL_EAXIN_##field,              \
    863. 

  863.               CPUID_REG_##reg, (CpuidReg)CPUID_INTERNAL_REG_##field,    \
    864. 

  864.               ((uint32)(data) & CPUID_INTERNAL_MASK_##field) >>         \
    865. 

  865.               CPUID_INTERNAL_SHIFT_##field)
    866. 

  866. 

  867. #endif
    868. 

  868. 

  869. 

  870. #define CPUID_SET(eaxIn, reg, flag, dataPtr)                            \
    871. 

  871.    do {                                                                 \
    872. 

  872.       ASSERT_ON_COMPILE(                                                \
    873. 

  873.          (uint32)eaxIn   == (uint32)CPUID_INTERNAL_EAXIN_##flag &&      \
    874. 

  874.          CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##flag);       \
    875. 

  875.       *(dataPtr) |= CPUID_INTERNAL_MASK_##flag;                         \
    876. 

  876.    } while (0)
    877. 

  877. 

  878. #define CPUID_CLEAR(eaxIn, reg, flag, dataPtr)                          \
    879. 

  879.    do {                                                                 \
    880. 

  880.       ASSERT_ON_COMPILE(                                                \
    881. 

  881.          (uint32)eaxIn   == (uint32)CPUID_INTERNAL_EAXIN_##flag &&      \
    882. 

  882.          CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##flag);       \
    883. 

  883.       *(dataPtr) &= ~CPUID_INTERNAL_MASK_##flag;                        \
    884. 

  884.    } while (0)
    885. 

  885. 

  886. #define CPUID_SETTO(eaxIn, reg, field, dataPtr, val)                    \
    887. 

  887.    do {                                                                 \
    888. 

  888.       uint32 _v = val;                                                  \
    889. 

  889.       uint32 *_d = dataPtr;                                             \
    890. 

  890.       ASSERT_ON_COMPILE(                                                \
    891. 

  891.          (uint32)eaxIn   == (uint32)CPUID_INTERNAL_EAXIN_##field &&     \
    892. 

  892.          CPUID_REG_##reg == (CpuidReg)CPUID_INTERNAL_REG_##field);      \
    893. 

  893.       *_d = (*_d & ~CPUID_INTERNAL_MASK_##field) |                      \
    894. 

  894.          (_v << CPUID_INTERNAL_SHIFT_##field);                          \
    895. 

  895.       ASSERT(_v == (*_d & CPUID_INTERNAL_MASK_##field) >>               \
    896. 

  896.              CPUID_INTERNAL_SHIFT_##field);                             \
    897. 

  897.    } while (0)
    898. 

  898. 

  899. #define CPUID_SETTO_SAFE(eaxIn, reg, field, dataPtr, val)               \
    900. 

  900.    do {                                                                 \
    901. 

  901.       uint32 _v = val &                …
    902.

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