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/drivers/ieee1394/raw1394.h

https://bitbucket.org/cresqo/cm7-p500-kernel
C Header | 191 lines | 118 code | 41 blank | 32 comment | 0 complexity | b70e79f123fe8a935806d8066b355bb9 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1#ifndef IEEE1394_RAW1394_H
  2#define IEEE1394_RAW1394_H
  3
  4/* header for the raw1394 API that is exported to user-space */
  5
  6#define RAW1394_KERNELAPI_VERSION 4
  7
  8/* state: opened */
  9#define RAW1394_REQ_INITIALIZE    1
 10
 11/* state: initialized */
 12#define RAW1394_REQ_LIST_CARDS    2
 13#define RAW1394_REQ_SET_CARD      3
 14
 15/* state: connected */
 16#define RAW1394_REQ_ASYNC_READ      100
 17#define RAW1394_REQ_ASYNC_WRITE     101
 18#define RAW1394_REQ_LOCK            102
 19#define RAW1394_REQ_LOCK64          103
 20#define RAW1394_REQ_ISO_SEND        104 /* removed ABI, now a no-op */
 21#define RAW1394_REQ_ASYNC_SEND      105
 22#define RAW1394_REQ_ASYNC_STREAM    106
 23
 24#define RAW1394_REQ_ISO_LISTEN      200 /* removed ABI, now a no-op */
 25#define RAW1394_REQ_FCP_LISTEN      201
 26#define RAW1394_REQ_RESET_BUS       202
 27#define RAW1394_REQ_GET_ROM         203
 28#define RAW1394_REQ_UPDATE_ROM      204
 29#define RAW1394_REQ_ECHO            205
 30#define RAW1394_REQ_MODIFY_ROM      206
 31
 32#define RAW1394_REQ_ARM_REGISTER    300
 33#define RAW1394_REQ_ARM_UNREGISTER  301
 34#define RAW1394_REQ_ARM_SET_BUF     302
 35#define RAW1394_REQ_ARM_GET_BUF     303
 36
 37#define RAW1394_REQ_RESET_NOTIFY    400
 38
 39#define RAW1394_REQ_PHYPACKET       500
 40
 41/* kernel to user */
 42#define RAW1394_REQ_BUS_RESET        10000
 43#define RAW1394_REQ_ISO_RECEIVE      10001
 44#define RAW1394_REQ_FCP_REQUEST      10002
 45#define RAW1394_REQ_ARM              10003
 46#define RAW1394_REQ_RAWISO_ACTIVITY  10004
 47
 48/* error codes */
 49#define RAW1394_ERROR_NONE        0
 50#define RAW1394_ERROR_COMPAT      (-1001)
 51#define RAW1394_ERROR_STATE_ORDER (-1002)
 52#define RAW1394_ERROR_GENERATION  (-1003)
 53#define RAW1394_ERROR_INVALID_ARG (-1004)
 54#define RAW1394_ERROR_MEMFAULT    (-1005)
 55#define RAW1394_ERROR_ALREADY     (-1006)
 56
 57#define RAW1394_ERROR_EXCESSIVE   (-1020)
 58#define RAW1394_ERROR_UNTIDY_LEN  (-1021)
 59
 60#define RAW1394_ERROR_SEND_ERROR  (-1100)
 61#define RAW1394_ERROR_ABORTED     (-1101)
 62#define RAW1394_ERROR_TIMEOUT     (-1102)
 63
 64/* arm_codes */
 65#define ARM_READ   1
 66#define ARM_WRITE  2
 67#define ARM_LOCK   4
 68
 69#define RAW1394_LONG_RESET  0
 70#define RAW1394_SHORT_RESET 1
 71
 72/* busresetnotify ... */
 73#define RAW1394_NOTIFY_OFF 0
 74#define RAW1394_NOTIFY_ON  1
 75
 76#include <asm/types.h>
 77
 78struct raw1394_request {
 79        __u32 type;
 80        __s32 error;
 81        __u32 misc;
 82
 83        __u32 generation;
 84        __u32 length;
 85
 86        __u64 address;
 87
 88        __u64 tag;
 89
 90        __u64 sendb;
 91        __u64 recvb;
 92};
 93
 94struct raw1394_khost_list {
 95        __u32 nodes;
 96        __u8 name[32];
 97};
 98
 99typedef struct arm_request {
100        __u16           destination_nodeid;
101        __u16           source_nodeid;
102        __u64           destination_offset;
103        __u8            tlabel;
104        __u8            tcode;
105        __u8            extended_transaction_code;
106        __u32           generation;
107        __u16           buffer_length;
108        __u8            __user *buffer;
109} *arm_request_t;
110
111typedef struct arm_response {
112        __s32           response_code;
113        __u16           buffer_length;
114        __u8            __user *buffer;
115} *arm_response_t;
116
117typedef struct arm_request_response {
118        struct arm_request  __user *request;
119        struct arm_response __user *response;
120} *arm_request_response_t;
121
122/* rawiso API */
123#include "ieee1394-ioctl.h"
124
125/* per-packet metadata embedded in the ringbuffer */
126/* must be identical to hpsb_iso_packet_info in iso.h! */
127struct raw1394_iso_packet_info {
128	__u32 offset;
129	__u16 len;
130	__u16 cycle;   /* recv only */
131	__u8  channel; /* recv only */
132	__u8  tag;
133	__u8  sy;
134};
135
136/* argument for RAW1394_ISO_RECV/XMIT_PACKETS ioctls */
137struct raw1394_iso_packets {
138	__u32 n_packets;
139	struct raw1394_iso_packet_info __user *infos;
140};
141
142struct raw1394_iso_config {
143	/* size of packet data buffer, in bytes (will be rounded up to PAGE_SIZE) */
144	__u32 data_buf_size;
145
146	/* # of packets to buffer */
147	__u32 buf_packets;
148
149	/* iso channel (set to -1 for multi-channel recv) */
150	__s32 channel;
151
152	/* xmit only - iso transmission speed */
153	__u8 speed;
154
155	/* The mode of the dma when receiving iso data. Must be supported by chip */
156	__u8 dma_mode;
157
158	/* max. latency of buffer, in packets (-1 if you don't care) */
159	__s32 irq_interval;
160};
161
162/* argument to RAW1394_ISO_XMIT/RECV_INIT and RAW1394_ISO_GET_STATUS */
163struct raw1394_iso_status {
164	/* current settings */
165	struct raw1394_iso_config config;
166
167	/* number of packets waiting to be filled with data (ISO transmission)
168	   or containing data received (ISO reception) */
169	__u32 n_packets;
170
171	/* approximate number of packets dropped due to overflow or
172	   underflow of the packet buffer (a value of zero guarantees
173	   that no packets have been dropped) */
174	__u32 overflows;
175
176	/* cycle number at which next packet will be transmitted;
177	   -1 if not known */
178	__s16 xmit_cycle;
179};
180
181/* argument to RAW1394_IOC_GET_CYCLE_TIMER ioctl */
182struct raw1394_cycle_timer {
183	/* contents of Isochronous Cycle Timer register,
184	   as in OHCI 1.1 clause 5.13 (also with non-OHCI hosts) */
185	__u32 cycle_timer;
186
187	/* local time in microseconds since Epoch,
188	   simultaneously read with cycle timer */
189	__u64 local_time;
190};
191#endif /* IEEE1394_RAW1394_H */