/drivers/i2c/busses/i2c-qup.c
C | 1200 lines | 980 code | 112 blank | 108 comment | 201 complexity | 29d444d34d14261e57140c7e61cde227 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18/*
19 * QUP driver for Qualcomm MSM platforms
20 *
21 */
22
23/* #define DEBUG */
24
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/init.h>
28#include <linux/i2c.h>
29#include <linux/interrupt.h>
30#include <linux/platform_device.h>
31#include <linux/delay.h>
32#include <linux/io.h>
33#include <linux/mutex.h>
34#include <linux/timer.h>
35#include <linux/slab.h>
36#include <mach/board.h>
37#include <linux/slab.h>
38#include <linux/pm_runtime.h>
39
40MODULE_LICENSE("GPL v2");
41MODULE_VERSION("0.2");
42MODULE_ALIAS("platform:i2c_qup");
43
44/* QUP Registers */
45enum {
46 QUP_CONFIG = 0x0,
47 QUP_STATE = 0x4,
48 QUP_IO_MODE = 0x8,
49 QUP_SW_RESET = 0xC,
50 QUP_OPERATIONAL = 0x18,
51 QUP_ERROR_FLAGS = 0x1C,
52 QUP_ERROR_FLAGS_EN = 0x20,
53 QUP_MX_READ_CNT = 0x208,
54 QUP_MX_INPUT_CNT = 0x200,
55 QUP_MX_WR_CNT = 0x100,
56 QUP_OUT_DEBUG = 0x108,
57 QUP_OUT_FIFO_CNT = 0x10C,
58 QUP_OUT_FIFO_BASE = 0x110,
59 QUP_IN_READ_CUR = 0x20C,
60 QUP_IN_DEBUG = 0x210,
61 QUP_IN_FIFO_CNT = 0x214,
62 QUP_IN_FIFO_BASE = 0x218,
63 QUP_I2C_CLK_CTL = 0x400,
64 QUP_I2C_STATUS = 0x404,
65};
66
67/* QUP States and reset values */
68enum {
69 QUP_RESET_STATE = 0,
70 QUP_RUN_STATE = 1U,
71 QUP_STATE_MASK = 3U,
72 QUP_PAUSE_STATE = 3U,
73 QUP_STATE_VALID = 1U << 2,
74 QUP_I2C_MAST_GEN = 1U << 4,
75 QUP_OPERATIONAL_RESET = 0xFF0,
76 QUP_I2C_STATUS_RESET = 0xFFFFFC,
77};
78
79/* QUP OPERATIONAL FLAGS */
80enum {
81 QUP_OUT_SVC_FLAG = 1U << 8,
82 QUP_IN_SVC_FLAG = 1U << 9,
83 QUP_MX_INPUT_DONE = 1U << 11,
84};
85
86/* I2C mini core related values */
87enum {
88 I2C_MINI_CORE = 2U << 8,
89 I2C_N_VAL = 0xF,
90
91};
92
93/* Packing Unpacking words in FIFOs , and IO modes*/
94enum {
95 QUP_WR_BLK_MODE = 1U << 10,
96 QUP_RD_BLK_MODE = 1U << 12,
97 QUP_UNPACK_EN = 1U << 14,
98 QUP_PACK_EN = 1U << 15,
99};
100
101/* QUP tags */
102enum {
103 QUP_OUT_NOP = 0,
104 QUP_OUT_START = 1U << 8,
105 QUP_OUT_DATA = 2U << 8,
106 QUP_OUT_STOP = 3U << 8,
107 QUP_OUT_REC = 4U << 8,
108 QUP_IN_DATA = 5U << 8,
109 QUP_IN_STOP = 6U << 8,
110 QUP_IN_NACK = 7U << 8,
111};
112
113/* Status, Error flags */
114enum {
115 I2C_STATUS_WR_BUFFER_FULL = 1U << 0,
116 I2C_STATUS_BUS_ACTIVE = 1U << 8,
117 I2C_STATUS_ERROR_MASK = 0x38000FC,
118 QUP_I2C_NACK_FLAG = 1U << 3,
119 QUP_IN_NOT_EMPTY = 1U << 5,
120 QUP_STATUS_ERROR_FLAGS = 0x7C,
121};
122
123struct qup_i2c_dev {
124 struct device *dev;
125 void __iomem *base; /* virtual */
126 void __iomem *gsbi; /* virtual */
127 int in_irq;
128 int out_irq;
129 int err_irq;
130 int num_irqs;
131 struct clk *clk;
132 struct clk *pclk;
133 struct i2c_adapter adapter;
134
135 struct i2c_msg *msg;
136 int pos;
137 int cnt;
138 int err;
139 int mode;
140 int clk_ctl;
141 int one_bit_t;
142 int out_fifo_sz;
143 int in_fifo_sz;
144 int out_blk_sz;
145 int in_blk_sz;
146 int wr_sz;
147 struct msm_i2c_platform_data *pdata;
148 int suspended;
149 int clk_state;
150 struct timer_list pwr_timer;
151 struct mutex mlock;
152 void *complete;
153};
154
155#ifdef DEBUG
156static void
157qup_print_status(struct qup_i2c_dev *dev)
158{
159 uint32_t val;
160 val = readl(dev->base+QUP_CONFIG);
161 dev_dbg(dev->dev, "Qup config is :0x%x\n", val);
162 val = readl(dev->base+QUP_STATE);
163 dev_dbg(dev->dev, "Qup state is :0x%x\n", val);
164 val = readl(dev->base+QUP_IO_MODE);
165 dev_dbg(dev->dev, "Qup mode is :0x%x\n", val);
166}
167#else
168static inline void qup_print_status(struct qup_i2c_dev *dev)
169{
170}
171#endif
172
173static irqreturn_t
174qup_i2c_interrupt(int irq, void *devid)
175{
176 struct qup_i2c_dev *dev = devid;
177 uint32_t status = readl(dev->base + QUP_I2C_STATUS);
178 uint32_t status1 = readl(dev->base + QUP_ERROR_FLAGS);
179 uint32_t op_flgs = readl(dev->base + QUP_OPERATIONAL);
180 int err = 0;
181
182 if (!dev->msg || !dev->complete) {
183 /* Clear Error interrupt if it's a level triggered interrupt*/
184 if (dev->num_irqs == 1) {
185 writel(QUP_RESET_STATE, dev->base+QUP_STATE);
186 /* Ensure that state is written before ISR exits */
187 dsb();
188 }
189 return IRQ_HANDLED;
190 }
191
192 if (status & I2C_STATUS_ERROR_MASK) {
193 dev_err(dev->dev, "QUP: I2C status flags :0x%x, irq:%d\n",
194 status, irq);
195 err = status;
196 /* Clear Error interrupt if it's a level triggered interrupt*/
197 if (dev->num_irqs == 1) {
198 writel(QUP_RESET_STATE, dev->base+QUP_STATE);
199 /* Ensure that state is written before ISR exits */
200 dsb();
201 }
202 goto intr_done;
203 }
204
205 if (status1 & 0x7F) {
206 dev_err(dev->dev, "QUP: QUP status flags :0x%x\n", status1);
207 err = -status1;
208 /* Clear Error interrupt if it's a level triggered interrupt*/
209 if (dev->num_irqs == 1) {
210 writel((status1 & QUP_STATUS_ERROR_FLAGS),
211 dev->base + QUP_ERROR_FLAGS);
212 /* Ensure that error flags are cleared before ISR
213 * exits
214 */
215 dsb();
216 }
217 goto intr_done;
218 }
219
220 if ((dev->num_irqs == 3) && (dev->msg->flags == I2C_M_RD)
221 && (irq == dev->out_irq))
222 return IRQ_HANDLED;
223 if (op_flgs & QUP_OUT_SVC_FLAG) {
224 writel(QUP_OUT_SVC_FLAG, dev->base + QUP_OPERATIONAL);
225 /* Ensure that service flag is acknowledged before ISR exits */
226 dsb();
227 }
228 if (dev->msg->flags == I2C_M_RD) {
229 if ((op_flgs & QUP_MX_INPUT_DONE) ||
230 (op_flgs & QUP_IN_SVC_FLAG)) {
231 writel(QUP_IN_SVC_FLAG, dev->base + QUP_OPERATIONAL);
232 /* Ensure that service flag is acknowledged before ISR
233 * exits
234 */
235 dsb();
236 } else
237 return IRQ_HANDLED;
238 }
239
240intr_done:
241 dev_dbg(dev->dev, "QUP intr= %d, i2c status=0x%x, qup status = 0x%x\n",
242 irq, status, status1);
243 qup_print_status(dev);
244 dev->err = err;
245 complete(dev->complete);
246 return IRQ_HANDLED;
247}
248
249static void
250qup_i2c_pwr_mgmt(struct qup_i2c_dev *dev, unsigned int state)
251{
252 dev->clk_state = state;
253 if (state != 0) {
254 clk_enable(dev->clk);
255 if (dev->pclk)
256 clk_enable(dev->pclk);
257 } else {
258 clk_disable(dev->clk);
259 if (dev->pclk)
260 clk_disable(dev->pclk);
261 }
262}
263
264static void
265qup_i2c_pwr_timer(unsigned long data)
266{
267 struct qup_i2c_dev *dev = (struct qup_i2c_dev *) data;
268 dev_dbg(dev->dev, "QUP_Power: Inactivity based power management\n");
269 if (dev->clk_state == 1)
270 qup_i2c_pwr_mgmt(dev, 0);
271}
272
273static int
274qup_i2c_poll_writeready(struct qup_i2c_dev *dev, int rem)
275{
276 uint32_t retries = 0;
277
278 while (retries != 2000) {
279 uint32_t status = readl(dev->base + QUP_I2C_STATUS);
280
281 if (!(status & I2C_STATUS_WR_BUFFER_FULL)) {
282 if (((dev->msg->flags & I2C_M_RD) || (rem == 0)) &&
283 !(status & I2C_STATUS_BUS_ACTIVE))
284 return 0;
285 else if ((dev->msg->flags == 0) && (rem > 0))
286 return 0;
287 else /* 1-bit delay before we check for bus busy */
288 udelay(dev->one_bit_t);
289 }
290 if (retries++ == 1000)
291 udelay(100);
292 }
293 qup_print_status(dev);
294 return -ETIMEDOUT;
295}
296
297static int
298qup_i2c_poll_state(struct qup_i2c_dev *dev, uint32_t state)
299{
300 uint32_t retries = 0;
301
302 dev_dbg(dev->dev, "Polling Status for state:0x%x\n", state);
303
304 while (retries != 2000) {
305 uint32_t status = readl(dev->base + QUP_STATE);
306
307 if ((status & (QUP_STATE_VALID | state)) ==
308 (QUP_STATE_VALID | state))
309 return 0;
310 else if (retries++ == 1000)
311 udelay(100);
312 }
313 return -ETIMEDOUT;
314}
315
316#ifdef DEBUG
317static void qup_verify_fifo(struct qup_i2c_dev *dev, uint32_t val,
318 uint32_t addr, int rdwr)
319{
320 if (rdwr)
321 dev_dbg(dev->dev, "RD:Wrote 0x%x to out_ff:0x%x\n", val, addr);
322 else
323 dev_dbg(dev->dev, "WR:Wrote 0x%x to out_ff:0x%x\n", val, addr);
324}
325#else
326static inline void qup_verify_fifo(struct qup_i2c_dev *dev, uint32_t val,
327 uint32_t addr, int rdwr)
328{
329}
330#endif
331
332static void
333qup_issue_read(struct qup_i2c_dev *dev, struct i2c_msg *msg, int *idx,
334 uint32_t carry_over)
335{
336 uint16_t addr = (msg->addr << 1) | 1;
337 /* QUP limit 256 bytes per read. By HW design, 0 in the 8-bit field
338 * is treated as 256 byte read.
339 */
340 uint16_t rd_len = ((dev->cnt == 256) ? 0 : dev->cnt);
341
342 if (*idx % 4) {
343 writel(carry_over | ((QUP_OUT_START | addr) << 16),
344 dev->base + QUP_OUT_FIFO_BASE);/* + (*idx-2)); */
345
346 qup_verify_fifo(dev, carry_over |
347 ((QUP_OUT_START | addr) << 16), (uint32_t)dev->base
348 + QUP_OUT_FIFO_BASE + (*idx - 2), 1);
349 writel((QUP_OUT_REC | rd_len),
350 dev->base + QUP_OUT_FIFO_BASE);/* + (*idx+2)); */
351
352 qup_verify_fifo(dev, (QUP_OUT_REC | rd_len),
353 (uint32_t)dev->base + QUP_OUT_FIFO_BASE + (*idx + 2), 1);
354 } else {
355 writel(((QUP_OUT_REC | rd_len) << 16) | QUP_OUT_START | addr,
356 dev->base + QUP_OUT_FIFO_BASE);/* + (*idx)); */
357
358 qup_verify_fifo(dev, QUP_OUT_REC << 16 | rd_len << 16 |
359 QUP_OUT_START | addr,
360 (uint32_t)dev->base + QUP_OUT_FIFO_BASE + (*idx), 1);
361 }
362 *idx += 4;
363}
364
365static void
366qup_issue_write(struct qup_i2c_dev *dev, struct i2c_msg *msg, int rem,
367 int *idx, uint32_t *carry_over)
368{
369 int entries = dev->cnt;
370 int empty_sl = dev->wr_sz - ((*idx) >> 1);
371 int i = 0;
372 uint32_t val = 0;
373 uint32_t last_entry = 0;
374 uint16_t addr = msg->addr << 1;
375
376 if (dev->pos == 0) {
377 if (*idx % 4) {
378 writel(*carry_over | ((QUP_OUT_START | addr) << 16),
379 dev->base + QUP_OUT_FIFO_BASE);
380
381 qup_verify_fifo(dev, *carry_over | QUP_OUT_DATA << 16 |
382 addr << 16, (uint32_t)dev->base +
383 QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
384 } else
385 val = QUP_OUT_START | addr;
386 *idx += 2;
387 i++;
388 entries++;
389 } else {
390 /* Avoid setp time issue by adding 1 NOP when number of bytes
391 * are more than FIFO/BLOCK size. setup time issue can't appear
392 * otherwise since next byte to be written will always be ready
393 */
394 val = (QUP_OUT_NOP | 1);
395 *idx += 2;
396 i++;
397 entries++;
398 }
399 if (entries > empty_sl)
400 entries = empty_sl;
401
402 for (; i < (entries - 1); i++) {
403 if (*idx % 4) {
404 writel(val | ((QUP_OUT_DATA |
405 msg->buf[dev->pos]) << 16),
406 dev->base + QUP_OUT_FIFO_BASE);
407
408 qup_verify_fifo(dev, val | QUP_OUT_DATA << 16 |
409 msg->buf[dev->pos] << 16, (uint32_t)dev->base +
410 QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
411 } else
412 val = QUP_OUT_DATA | msg->buf[dev->pos];
413 (*idx) += 2;
414 dev->pos++;
415 }
416 if (dev->pos < (msg->len - 1))
417 last_entry = QUP_OUT_DATA;
418 else if (rem > 1) /* not last array entry */
419 last_entry = QUP_OUT_DATA;
420 else
421 last_entry = QUP_OUT_STOP;
422 if ((*idx % 4) == 0) {
423 /*
424 * If read-start and read-command end up in different fifos, it
425 * may result in extra-byte being read due to extra-read cycle.
426 * Avoid that by inserting NOP as the last entry of fifo only
427 * if write command(s) leave 1 space in fifo.
428 */
429 if (rem > 1) {
430 struct i2c_msg *next = msg + 1;
431 if (next->addr == msg->addr && (next->flags | I2C_M_RD)
432 && *idx == ((dev->wr_sz*2) - 4)) {
433 writel(((last_entry | msg->buf[dev->pos]) |
434 ((1 | QUP_OUT_NOP) << 16)), dev->base +
435 QUP_OUT_FIFO_BASE);/* + (*idx) - 2); */
436 *idx += 2;
437 } else if (next->flags == 0 && dev->pos == msg->len - 1
438 && *idx < (dev->wr_sz*2)) {
439 /* Last byte of an intermittent write */
440 writel((last_entry | msg->buf[dev->pos]),
441 dev->base + QUP_OUT_FIFO_BASE);
442
443 qup_verify_fifo(dev,
444 last_entry | msg->buf[dev->pos],
445 (uint32_t)dev->base +
446 QUP_OUT_FIFO_BASE + (*idx), 0);
447 *idx += 2;
448 } else
449 *carry_over = (last_entry | msg->buf[dev->pos]);
450 } else {
451 writel((last_entry | msg->buf[dev->pos]),
452 dev->base + QUP_OUT_FIFO_BASE);/* + (*idx) - 2); */
453
454 qup_verify_fifo(dev, last_entry | msg->buf[dev->pos],
455 (uint32_t)dev->base + QUP_OUT_FIFO_BASE +
456 (*idx), 0);
457 }
458 } else {
459 writel(val | ((last_entry | msg->buf[dev->pos]) << 16),
460 dev->base + QUP_OUT_FIFO_BASE);/* + (*idx) - 2); */
461
462 qup_verify_fifo(dev, val | (last_entry << 16) |
463 (msg->buf[dev->pos] << 16), (uint32_t)dev->base +
464 QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
465 }
466
467 *idx += 2;
468 dev->pos++;
469 dev->cnt = msg->len - dev->pos;
470}
471
472static int
473qup_update_state(struct qup_i2c_dev *dev, uint32_t state)
474{
475 if (qup_i2c_poll_state(dev, 0) != 0)
476 return -EIO;
477 writel(state, dev->base + QUP_STATE);
478 if (qup_i2c_poll_state(dev, state) != 0)
479 return -EIO;
480 return 0;
481}
482
483static int
484qup_set_read_mode(struct qup_i2c_dev *dev, int rd_len)
485{
486 uint32_t wr_mode = (dev->wr_sz < dev->out_fifo_sz) ?
487 QUP_WR_BLK_MODE : 0;
488 if (rd_len > 256) {
489 dev_err(dev->dev, "HW doesn't support READs > 256 bytes\n");
490 return -EPROTONOSUPPORT;
491 }
492 if (rd_len <= dev->in_fifo_sz) {
493 writel(wr_mode | QUP_PACK_EN | QUP_UNPACK_EN,
494 dev->base + QUP_IO_MODE);
495 writel(rd_len, dev->base + QUP_MX_READ_CNT);
496 } else {
497 writel(wr_mode | QUP_RD_BLK_MODE |
498 QUP_PACK_EN | QUP_UNPACK_EN, dev->base + QUP_IO_MODE);
499 writel(rd_len, dev->base + QUP_MX_INPUT_CNT);
500 }
501 return 0;
502}
503
504static int
505qup_set_wr_mode(struct qup_i2c_dev *dev, int rem)
506{
507 int total_len = 0;
508 int ret = 0;
509 if (dev->msg->len >= (dev->out_fifo_sz - 1)) {
510 total_len = dev->msg->len + 1 +
511 (dev->msg->len/(dev->out_blk_sz-1));
512 writel(QUP_WR_BLK_MODE | QUP_PACK_EN | QUP_UNPACK_EN,
513 dev->base + QUP_IO_MODE);
514 dev->wr_sz = dev->out_blk_sz;
515 } else
516 writel(QUP_PACK_EN | QUP_UNPACK_EN,
517 dev->base + QUP_IO_MODE);
518
519 if (rem > 1) {
520 struct i2c_msg *next = dev->msg + 1;
521 if (next->addr == dev->msg->addr &&
522 next->flags == I2C_M_RD) {
523 ret = qup_set_read_mode(dev, next->len);
524 /* make sure read start & read command are in 1 blk */
525 if ((total_len % dev->out_blk_sz) ==
526 (dev->out_blk_sz - 1))
527 total_len += 3;
528 else
529 total_len += 2;
530 }
531 }
532 /* WRITE COUNT register valid/used only in block mode */
533 if (dev->wr_sz == dev->out_blk_sz)
534 writel(total_len, dev->base + QUP_MX_WR_CNT);
535 return ret;
536}
537
538static int
539qup_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
540{
541 DECLARE_COMPLETION_ONSTACK(complete);
542 struct qup_i2c_dev *dev = i2c_get_adapdata(adap);
543 int ret;
544 int rem = num;
545 long timeout;
546 int err;
547
548 del_timer_sync(&dev->pwr_timer);
549 mutex_lock(&dev->mlock);
550
551 if (dev->suspended) {
552 mutex_unlock(&dev->mlock);
553 return -EIO;
554 }
555
556 if (dev->clk_state == 0) {
557 if (dev->clk_ctl == 0) {
558 if (dev->pdata->src_clk_rate > 0)
559 clk_set_rate(dev->clk,
560 dev->pdata->src_clk_rate);
561 else
562 dev->pdata->src_clk_rate = 19200000;
563 }
564 qup_i2c_pwr_mgmt(dev, 1);
565 }
566 /* Initialize QUP registers during first transfer */
567 if (dev->clk_ctl == 0) {
568 int fs_div;
569 int hs_div;
570 uint32_t fifo_reg;
571
572 if (dev->gsbi) {
573 writel(0x2 << 4, dev->gsbi);
574 /* GSBI memory is not in the same 1K region as other
575 * QUP registers. dsb() here ensures that the GSBI
576 * register is updated in correct order and that the
577 * write has gone through before programming QUP core
578 * registers
579 */
580 dsb();
581 }
582
583 fs_div = ((dev->pdata->src_clk_rate
584 / dev->pdata->clk_freq) / 2) - 3;
585 hs_div = 3;
586 dev->clk_ctl = ((hs_div & 0x7) << 8) | (fs_div & 0xff);
587 fifo_reg = readl(dev->base + QUP_IO_MODE);
588 if (fifo_reg & 0x3)
589 dev->out_blk_sz = (fifo_reg & 0x3) * 16;
590 else
591 dev->out_blk_sz = 16;
592 if (fifo_reg & 0x60)
593 dev->in_blk_sz = ((fifo_reg & 0x60) >> 5) * 16;
594 else
595 dev->in_blk_sz = 16;
596 /*
597 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
598 * associated with each byte written/received
599 */
600 dev->out_blk_sz /= 2;
601 dev->in_blk_sz /= 2;
602 dev->out_fifo_sz = dev->out_blk_sz *
603 (2 << ((fifo_reg & 0x1C) >> 2));
604 dev->in_fifo_sz = dev->in_blk_sz *
605 (2 << ((fifo_reg & 0x380) >> 7));
606 dev_dbg(dev->dev, "QUP IN:bl:%d, ff:%d, OUT:bl:%d, ff:%d\n",
607 dev->in_blk_sz, dev->in_fifo_sz,
608 dev->out_blk_sz, dev->out_fifo_sz);
609 }
610
611 writel(1, dev->base + QUP_SW_RESET);
612 ret = qup_i2c_poll_state(dev, QUP_RESET_STATE);
613 if (ret) {
614 dev_err(dev->dev, "QUP Busy:Trying to recover\n");
615 goto out_err;
616 }
617
618 if (dev->num_irqs == 3) {
619 enable_irq(dev->in_irq);
620 enable_irq(dev->out_irq);
621 }
622 enable_irq(dev->err_irq);
623
624 /* Initialize QUP registers */
625 writel(0, dev->base + QUP_CONFIG);
626 writel(QUP_OPERATIONAL_RESET, dev->base + QUP_OPERATIONAL);
627 writel(QUP_STATUS_ERROR_FLAGS, dev->base + QUP_ERROR_FLAGS_EN);
628
629 writel(I2C_MINI_CORE | I2C_N_VAL, dev->base + QUP_CONFIG);
630
631 /* Initialize I2C mini core registers */
632 writel(0, dev->base + QUP_I2C_CLK_CTL);
633 writel(QUP_I2C_STATUS_RESET, dev->base + QUP_I2C_STATUS);
634
635 while (rem) {
636 bool filled = false;
637
638 dev->cnt = msgs->len;
639 dev->pos = 0;
640 dev->msg = msgs;
641
642 dev->wr_sz = dev->out_fifo_sz;
643 dev->err = 0;
644 dev->complete = &complete;
645
646 if (qup_i2c_poll_state(dev, QUP_I2C_MAST_GEN) != 0) {
647 ret = -EIO;
648 goto out_err;
649 }
650
651 qup_print_status(dev);
652 /* HW limits Read upto 256 bytes in 1 read without stop */
653 if (dev->msg->flags & I2C_M_RD) {
654 ret = qup_set_read_mode(dev, dev->cnt);
655 if (ret != 0)
656 goto out_err;
657 } else {
658 ret = qup_set_wr_mode(dev, rem);
659 if (ret != 0)
660 goto out_err;
661 /* Don't fill block till we get interrupt */
662 if (dev->wr_sz == dev->out_blk_sz)
663 filled = true;
664 }
665
666 err = qup_update_state(dev, QUP_RUN_STATE);
667 if (err < 0) {
668 ret = err;
669 goto out_err;
670 }
671
672 qup_print_status(dev);
673 writel(dev->clk_ctl, dev->base + QUP_I2C_CLK_CTL);
674 /* CLK_CTL register is not in the same 1K region as other QUP
675 * registers. Ensure that clock control is written before
676 * programming other QUP registers
677 */
678 dsb();
679
680 do {
681 int idx = 0;
682 uint32_t carry_over = 0;
683
684 /* Transition to PAUSE state only possible from RUN */
685 err = qup_update_state(dev, QUP_PAUSE_STATE);
686 if (err < 0) {
687 ret = err;
688 goto out_err;
689 }
690
691 qup_print_status(dev);
692 /* This operation is Write, check the next operation
693 * and decide mode
694 */
695 while (filled == false) {
696 if ((msgs->flags & I2C_M_RD) &&
697 (dev->cnt == msgs->len))
698 qup_issue_read(dev, msgs, &idx,
699 carry_over);
700 else if (!(msgs->flags & I2C_M_RD))
701 qup_issue_write(dev, msgs, rem, &idx,
702 &carry_over);
703 if (idx >= (dev->wr_sz << 1))
704 filled = true;
705 /* Start new message */
706 if (filled == false) {
707 if (msgs->flags & I2C_M_RD)
708 filled = true;
709 else if (rem > 1) {
710 /* Only combine operations with
711 * same address
712 */
713 struct i2c_msg *next = msgs + 1;
714 if (next->addr != msgs->addr ||
715 next->flags == 0)
716 filled = true;
717 else {
718 rem--;
719 msgs++;
720 dev->msg = msgs;
721 dev->pos = 0;
722 dev->cnt = msgs->len;
723 }
724 } else
725 filled = true;
726 }
727 }
728 err = qup_update_state(dev, QUP_RUN_STATE);
729 if (err < 0) {
730 ret = err;
731 goto out_err;
732 }
733 dev_dbg(dev->dev, "idx:%d, rem:%d, num:%d, mode:%d\n",
734 idx, rem, num, dev->mode);
735
736 qup_print_status(dev);
737 timeout = wait_for_completion_timeout(&complete, HZ);
738 if (!timeout) {
739 uint32_t istatus = readl(dev->base +
740 QUP_I2C_STATUS);
741 uint32_t qstatus = readl(dev->base +
742 QUP_ERROR_FLAGS);
743 uint32_t op_flgs = readl(dev->base +
744 QUP_OPERATIONAL);
745
746 dev_err(dev->dev, "Transaction timed out\n");
747 dev_err(dev->dev, "I2C Status: %x\n", istatus);
748 dev_err(dev->dev, "QUP Status: %x\n", qstatus);
749 dev_err(dev->dev, "OP Flags: %x\n", op_flgs);
750 writel(1, dev->base + QUP_SW_RESET);
751 /* Make sure that the write has gone through
752 * before returning from the function
753 */
754 dsb();
755 ret = -ETIMEDOUT;
756 goto out_err;
757 }
758 if (dev->err) {
759 if (dev->err > 0 &&
760 dev->err & QUP_I2C_NACK_FLAG)
761 dev_err(dev->dev,
762 "I2C slave addr:0x%x not connected\n",
763 dev->msg->addr);
764 else if (dev->err < 0) {
765 dev_err(dev->dev,
766 "QUP data xfer error %d\n", dev->err);
767 ret = dev->err;
768 goto out_err;
769 }
770 ret = -dev->err;
771 goto out_err;
772 }
773 if (dev->msg->flags & I2C_M_RD) {
774 int i;
775 uint32_t dval = 0;
776 for (i = 0; dev->pos < dev->msg->len; i++,
777 dev->pos++) {
778 uint32_t rd_status = readl(dev->base +
779 QUP_OPERATIONAL);
780 if (i % 2 == 0) {
781 if ((rd_status &
782 QUP_IN_NOT_EMPTY) == 0)
783 break;
784 dval = readl(dev->base +
785 QUP_IN_FIFO_BASE);
786 dev->msg->buf[dev->pos] =
787 dval & 0xFF;
788 } else
789 dev->msg->buf[dev->pos] =
790 ((dval & 0xFF0000) >>
791 16);
792 }
793 dev->cnt -= i;
794 } else
795 filled = false; /* refill output FIFO */
796 } while (dev->cnt > 0);
797 if (dev->cnt == 0) {
798 rem--;
799 msgs++;
800 if (rem) {
801 err = qup_update_state(dev, QUP_RESET_STATE);
802 if (err < 0) {
803 ret = err;
804 goto out_err;
805 }
806 }
807 }
808 /* Wait for I2C bus to be idle */
809 ret = qup_i2c_poll_writeready(dev, rem);
810 if (ret) {
811 dev_err(dev->dev,
812 "Error waiting for write ready\n");
813 goto out_err;
814 }
815 }
816
817 ret = num;
818 out_err:
819 disable_irq(dev->err_irq);
820 if (dev->num_irqs == 3) {
821 disable_irq(dev->in_irq);
822 disable_irq(dev->out_irq);
823 }
824 dev->complete = NULL;
825 dev->msg = NULL;
826 dev->pos = 0;
827 dev->err = 0;
828 dev->cnt = 0;
829 dev->pwr_timer.expires = jiffies + 3*HZ;
830 add_timer(&dev->pwr_timer);
831 mutex_unlock(&dev->mlock);
832 return ret;
833}
834
835static u32
836qup_i2c_func(struct i2c_adapter *adap)
837{
838 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
839}
840
841static const struct i2c_algorithm qup_i2c_algo = {
842 .master_xfer = qup_i2c_xfer,
843 .functionality = qup_i2c_func,
844};
845
846static int __devinit
847qup_i2c_probe(struct platform_device *pdev)
848{
849 struct qup_i2c_dev *dev;
850 struct resource *qup_mem, *gsbi_mem, *qup_io, *gsbi_io;
851 struct resource *in_irq, *out_irq, *err_irq;
852 struct clk *clk, *pclk;
853 int ret = 0;
854 struct msm_i2c_platform_data *pdata;
855 const char *qup_apps_clk_name = "qup_clk";
856
857 gsbi_mem = NULL;
858 dev_dbg(&pdev->dev, "qup_i2c_probe\n");
859
860 pdata = pdev->dev.platform_data;
861 if (!pdata) {
862 dev_err(&pdev->dev, "platform data not initialized\n");
863 return -ENOSYS;
864 }
865 qup_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
866 "qup_phys_addr");
867 if (!qup_mem) {
868 dev_err(&pdev->dev, "no qup mem resource?\n");
869 return -ENODEV;
870 }
871
872 /*
873 * We only have 1 interrupt for new hardware targets and in_irq,
874 * out_irq will be NULL for those platforms
875 */
876 in_irq = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
877 "qup_in_intr");
878
879 out_irq = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
880 "qup_out_intr");
881
882 err_irq = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
883 "qup_err_intr");
884 if (!err_irq) {
885 dev_err(&pdev->dev, "no error irq resource?\n");
886 return -ENODEV;
887 }
888
889 qup_io = request_mem_region(qup_mem->start, resource_size(qup_mem),
890 pdev->name);
891 if (!qup_io) {
892 dev_err(&pdev->dev, "QUP region already claimed\n");
893 return -EBUSY;
894 }
895 if (!pdata->use_gsbi_shared_mode) {
896 gsbi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
897 "gsbi_qup_i2c_addr");
898 if (!gsbi_mem) {
899 dev_err(&pdev->dev, "no gsbi mem resource?\n");
900 return -ENODEV;
901 }
902 gsbi_io = request_mem_region(gsbi_mem->start,
903 resource_size(gsbi_mem),
904 pdev->name);
905 if (!gsbi_io) {
906 dev_err(&pdev->dev, "GSBI region already claimed\n");
907 return -EBUSY;
908 }
909 }
910
911 if (pdata->clk != NULL)
912 qup_apps_clk_name = pdata->clk;
913
914 clk = clk_get(&pdev->dev, qup_apps_clk_name);
915 if (IS_ERR(clk)) {
916 dev_err(&pdev->dev, "Could not get clock\n");
917 ret = PTR_ERR(clk);
918 goto err_clk_get_failed;
919 }
920
921 if (pdata->pclk != NULL) {
922 pclk = clk_get(&pdev->dev, pdata->pclk);
923 if (IS_ERR(pclk)) {
924 dev_err(&pdev->dev, "Could not get pclock\n");
925 ret = PTR_ERR(pclk);
926 clk_put(clk);
927 goto err_clk_get_failed;
928 }
929 } else
930 pclk = NULL;
931
932 if (!(pdata->msm_i2c_config_gpio)) {
933 dev_err(&pdev->dev, "config_gpio function not initialized\n");
934 ret = -ENOSYS;
935 goto err_config_failed;
936 }
937
938 /* We support frequencies upto FAST Mode(400KHz) */
939 if (pdata->clk_freq <= 0 ||
940 pdata->clk_freq > 400000) {
941 dev_err(&pdev->dev, "clock frequency not supported\n");
942 ret = -EIO;
943 goto err_config_failed;
944 }
945
946 dev = kzalloc(sizeof(struct qup_i2c_dev), GFP_KERNEL);
947 if (!dev) {
948 ret = -ENOMEM;
949 goto err_alloc_dev_failed;
950 }
951
952 dev->dev = &pdev->dev;
953 if (in_irq)
954 dev->in_irq = in_irq->start;
955 if (out_irq)
956 dev->out_irq = out_irq->start;
957 dev->err_irq = err_irq->start;
958 if (in_irq && out_irq)
959 dev->num_irqs = 3;
960 else
961 dev->num_irqs = 1;
962 dev->clk = clk;
963 dev->pclk = pclk;
964 dev->base = ioremap(qup_mem->start, resource_size(qup_mem));
965 if (!dev->base) {
966 ret = -ENOMEM;
967 goto err_ioremap_failed;
968 }
969
970 /* Configure GSBI block to use I2C functionality */
971 if (gsbi_mem) {
972 dev->gsbi = ioremap(gsbi_mem->start, resource_size(gsbi_mem));
973 if (!dev->gsbi) {
974 ret = -ENOMEM;
975 goto err_gsbi_failed;
976 }
977 }
978
979 platform_set_drvdata(pdev, dev);
980
981 dev->one_bit_t = USEC_PER_SEC/pdata->clk_freq;
982 dev->pdata = pdata;
983 dev->clk_ctl = 0;
984
985 /*
986 * We use num_irqs to also indicate if we got 3 interrupts or just 1.
987 * If we have just 1, we use err_irq as the general purpose irq
988 * and handle the changes in ISR accordingly
989 * Per Hardware guidelines, if we have 3 interrupts, they are always
990 * edge triggering, and if we have 1, it's always level-triggering
991 */
992 if (dev->num_irqs == 3) {
993 ret = request_irq(dev->in_irq, qup_i2c_interrupt,
994 IRQF_TRIGGER_RISING, "qup_in_intr", dev);
995 if (ret) {
996 dev_err(&pdev->dev, "request_in_irq failed\n");
997 goto err_request_irq_failed;
998 }
999 /*
1000 * We assume out_irq exists if in_irq does since platform
1001 * configuration either has 3 interrupts assigned to QUP or 1
1002 */
1003 ret = request_irq(dev->out_irq, qup_i2c_interrupt,
1004 IRQF_TRIGGER_RISING, "qup_out_intr", dev);
1005 if (ret) {
1006 dev_err(&pdev->dev, "request_out_irq failed\n");
1007 free_irq(dev->in_irq, dev);
1008 goto err_request_irq_failed;
1009 }
1010 ret = request_irq(dev->err_irq, qup_i2c_interrupt,
1011 IRQF_TRIGGER_RISING, "qup_err_intr", dev);
1012 if (ret) {
1013 dev_err(&pdev->dev, "request_err_irq failed\n");
1014 free_irq(dev->out_irq, dev);
1015 free_irq(dev->in_irq, dev);
1016 goto err_request_irq_failed;
1017 }
1018 } else {
1019 ret = request_irq(dev->err_irq, qup_i2c_interrupt,
1020 IRQF_TRIGGER_HIGH, "qup_err_intr", dev);
1021 if (ret) {
1022 dev_err(&pdev->dev, "request_err_irq failed\n");
1023 goto err_request_irq_failed;
1024 }
1025 }
1026 disable_irq(dev->err_irq);
1027 if (dev->num_irqs == 3) {
1028 disable_irq(dev->in_irq);
1029 disable_irq(dev->out_irq);
1030 }
1031 i2c_set_adapdata(&dev->adapter, dev);
1032 dev->adapter.algo = &qup_i2c_algo;
1033 strlcpy(dev->adapter.name,
1034 "QUP I2C adapter",
1035 sizeof(dev->adapter.name));
1036 dev->adapter.nr = pdev->id;
1037 pdata->msm_i2c_config_gpio(dev->adapter.nr, 1);
1038
1039 dev->suspended = 0;
1040 mutex_init(&dev->mlock);
1041 dev->clk_state = 0;
1042 setup_timer(&dev->pwr_timer, qup_i2c_pwr_timer, (unsigned long) dev);
1043
1044 pm_runtime_set_active(&pdev->dev);
1045 pm_runtime_enable(&pdev->dev);
1046
1047 ret = i2c_add_numbered_adapter(&dev->adapter);
1048 if (ret) {
1049 dev_err(&pdev->dev, "i2c_add_adapter failed\n");
1050 if (dev->num_irqs == 3) {
1051 free_irq(dev->out_irq, dev);
1052 free_irq(dev->in_irq, dev);
1053 }
1054 free_irq(dev->err_irq, dev);
1055 } else
1056 return 0;
1057
1058
1059err_request_irq_failed:
1060 if (dev->gsbi)
1061 iounmap(dev->gsbi);
1062err_gsbi_failed:
1063 iounmap(dev->base);
1064err_ioremap_failed:
1065 kfree(dev);
1066err_alloc_dev_failed:
1067err_config_failed:
1068 clk_put(clk);
1069 if (pclk)
1070 clk_put(pclk);
1071err_clk_get_failed:
1072 if (gsbi_mem)
1073 release_mem_region(gsbi_mem->start, resource_size(gsbi_mem));
1074 release_mem_region(qup_mem->start, resource_size(qup_mem));
1075 return ret;
1076}
1077
1078static int __devexit
1079qup_i2c_remove(struct platform_device *pdev)
1080{
1081 struct qup_i2c_dev *dev = platform_get_drvdata(pdev);
1082 struct resource *qup_mem, *gsbi_mem;
1083
1084 /* Grab mutex to ensure ongoing transaction is over */
1085 mutex_lock(&dev->mlock);
1086 dev->suspended = 1;
1087 mutex_unlock(&dev->mlock);
1088 mutex_destroy(&dev->mlock);
1089 del_timer_sync(&dev->pwr_timer);
1090 if (dev->clk_state != 0)
1091 qup_i2c_pwr_mgmt(dev, 0);
1092 platform_set_drvdata(pdev, NULL);
1093 if (dev->num_irqs == 3) {
1094 free_irq(dev->out_irq, dev);
1095 free_irq(dev->in_irq, dev);
1096 }
1097 free_irq(dev->err_irq, dev);
1098 i2c_del_adapter(&dev->adapter);
1099 clk_put(dev->clk);
1100 if (dev->pclk)
1101 clk_put(dev->pclk);
1102 if (dev->gsbi)
1103 iounmap(dev->gsbi);
1104 iounmap(dev->base);
1105
1106 pm_runtime_disable(&pdev->dev);
1107
1108 kfree(dev);
1109 if (!(dev->pdata->use_gsbi_shared_mode)) {
1110 gsbi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1111 "gsbi_qup_i2c_addr");
1112 release_mem_region(gsbi_mem->start, resource_size(gsbi_mem));
1113 }
1114 qup_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1115 "qup_phys_addr");
1116 release_mem_region(qup_mem->start, resource_size(qup_mem));
1117 return 0;
1118}
1119
1120#ifdef CONFIG_PM
1121static int qup_i2c_suspend(struct device *device)
1122{
1123 struct platform_device *pdev = to_platform_device(device);
1124 struct qup_i2c_dev *dev = platform_get_drvdata(pdev);
1125
1126 /* Grab mutex to ensure ongoing transaction is over */
1127 mutex_lock(&dev->mlock);
1128 dev->suspended = 1;
1129 mutex_unlock(&dev->mlock);
1130 del_timer_sync(&dev->pwr_timer);
1131 if (dev->clk_state != 0)
1132 qup_i2c_pwr_mgmt(dev, 0);
1133 return 0;
1134}
1135
1136static int qup_i2c_resume(struct device *device)
1137{
1138 struct platform_device *pdev = to_platform_device(device);
1139 struct qup_i2c_dev *dev = platform_get_drvdata(pdev);
1140 dev->suspended = 0;
1141 return 0;
1142}
1143#endif /* CONFIG_PM */
1144
1145#ifdef CONFIG_PM_RUNTIME
1146static int i2c_qup_runtime_idle(struct device *dev)
1147{
1148 dev_dbg(dev, "pm_runtime: idle...\n");
1149 return 0;
1150}
1151
1152static int i2c_qup_runtime_suspend(struct device *dev)
1153{
1154 dev_dbg(dev, "pm_runtime: suspending...\n");
1155 return 0;
1156}
1157
1158static int i2c_qup_runtime_resume(struct device *dev)
1159{
1160 dev_dbg(dev, "pm_runtime: resuming...\n");
1161 return 0;
1162}
1163#endif
1164
1165static const struct dev_pm_ops i2c_qup_dev_pm_ops = {
1166 SET_SYSTEM_SLEEP_PM_OPS(
1167 qup_i2c_suspend,
1168 qup_i2c_resume
1169 )
1170 SET_RUNTIME_PM_OPS(
1171 i2c_qup_runtime_suspend,
1172 i2c_qup_runtime_resume,
1173 i2c_qup_runtime_idle
1174 )
1175};
1176
1177static struct platform_driver qup_i2c_driver = {
1178 .probe = qup_i2c_probe,
1179 .remove = __devexit_p(qup_i2c_remove),
1180 .driver = {
1181 .name = "qup_i2c",
1182 .owner = THIS_MODULE,
1183 .pm = &i2c_qup_dev_pm_ops,
1184 },
1185};
1186
1187/* QUP may be needed to bring up other drivers */
1188static int __init
1189qup_i2c_init_driver(void)
1190{
1191 return platform_driver_register(&qup_i2c_driver);
1192}
1193arch_initcall(qup_i2c_init_driver);
1194
1195static void __exit qup_i2c_exit_driver(void)
1196{
1197 platform_driver_unregister(&qup_i2c_driver);
1198}
1199module_exit(qup_i2c_exit_driver);
1200