/drivers/gpu/msm/g12_reg.h
C Header | 97 lines | 63 code | 6 blank | 28 comment | 0 complexity | 93061683551688d418a123da5793c319 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/* Copyright (c) 2002,2007-2010, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#ifndef _G12_REG_H
30#define _G12_REG_H
31
32#define REG_VGC_IRQSTATUS__MH_MASK 0x00000001L
33#define REG_VGC_IRQSTATUS__G2D_MASK 0x00000002L
34#define REG_VGC_IRQSTATUS__FIFO_MASK 0x00000004L
35
36#define MH_INTERRUPT_MASK__AXI_READ_ERROR 0x00000001L
37#define MH_INTERRUPT_MASK__AXI_WRITE_ERROR 0x00000002L
38#define MH_INTERRUPT_MASK__MMU_PAGE_FAULT 0x00000004L
39
40#define MH_ARBITER_CONFIG__SAME_PAGE_GRANULARITY__SHIFT 0x00000006
41#define MH_ARBITER_CONFIG__L1_ARB_ENABLE__SHIFT 0x00000007
42#define MH_ARBITER_CONFIG__L1_ARB_HOLD_ENABLE__SHIFT 0x00000008
43#define MH_ARBITER_CONFIG__L2_ARB_CONTROL__SHIFT 0x00000009
44#define MH_ARBITER_CONFIG__PAGE_SIZE__SHIFT 0x0000000a
45#define MH_ARBITER_CONFIG__TC_REORDER_ENABLE__SHIFT 0x0000000d
46#define MH_ARBITER_CONFIG__TC_ARB_HOLD_ENABLE__SHIFT 0x0000000e
47#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT_ENABLE__SHIFT 0x0000000f
48#define MH_ARBITER_CONFIG__IN_FLIGHT_LIMIT__SHIFT 0x00000010
49#define MH_ARBITER_CONFIG__CP_CLNT_ENABLE__SHIFT 0x00000016
50#define MH_ARBITER_CONFIG__VGT_CLNT_ENABLE__SHIFT 0x00000017
51#define MH_ARBITER_CONFIG__TC_CLNT_ENABLE__SHIFT 0x00000018
52#define MH_ARBITER_CONFIG__RB_CLNT_ENABLE__SHIFT 0x00000019
53#define MH_ARBITER_CONFIG__PA_CLNT_ENABLE__SHIFT 0x0000001a
54
55#define MH_MMU_CONFIG__RB_W_CLNT_BEHAVIOR__SHIFT 0x00000004
56#define MH_MMU_CONFIG__CP_W_CLNT_BEHAVIOR__SHIFT 0x00000006
57#define MH_MMU_CONFIG__CP_R0_CLNT_BEHAVIOR__SHIFT 0x00000008
58#define MH_MMU_CONFIG__CP_R1_CLNT_BEHAVIOR__SHIFT 0x0000000a
59#define MH_MMU_CONFIG__CP_R2_CLNT_BEHAVIOR__SHIFT 0x0000000c
60#define MH_MMU_CONFIG__CP_R3_CLNT_BEHAVIOR__SHIFT 0x0000000e
61#define MH_MMU_CONFIG__CP_R4_CLNT_BEHAVIOR__SHIFT 0x00000010
62#define MH_MMU_CONFIG__VGT_R0_CLNT_BEHAVIOR__SHIFT 0x00000012
63#define MH_MMU_CONFIG__VGT_R1_CLNT_BEHAVIOR__SHIFT 0x00000014
64#define MH_MMU_CONFIG__TC_R_CLNT_BEHAVIOR__SHIFT 0x00000016
65#define MH_MMU_CONFIG__PA_W_CLNT_BEHAVIOR__SHIFT 0x00000018
66
67#define ADDR_MH_ARBITER_CONFIG 0x0A40
68#define ADDR_MH_INTERRUPT_CLEAR 0x0A44
69#define ADDR_MH_INTERRUPT_MASK 0x0A42
70#define ADDR_MH_INTERRUPT_STATUS 0x0A43
71#define ADDR_MH_AXI_ERROR 0x0A45
72#define ADDR_MH_AXI_HALT_CONTROL 0x0A50
73#define ADDR_MH_CLNT_INTF_CTRL_CONFIG1 0x0A54
74#define ADDR_MH_CLNT_INTF_CTRL_CONFIG2 0x0A55
75#define ADDR_MH_MMU_CONFIG 0x0040
76#define ADDR_MH_MMU_INVALIDATE 0x0045
77#define ADDR_MH_MMU_MPU_BASE 0x0046
78#define ADDR_MH_MMU_MPU_END 0x0047
79#define ADDR_MH_MMU_PT_BASE 0x0042
80#define ADDR_MH_MMU_TRAN_ERROR 0x0044
81#define ADDR_MH_MMU_VA_RANGE 0x0041
82#define ADDR_VGC_MH_READ_ADDR 0x0510
83#define ADDR_VGC_MH_DATA_ADDR 0x0518
84#define ADDR_MH_MMU_PAGE_FAULT 0x0043
85#define ADDR_VGC_COMMANDSTREAM 0x0000
86#define ADDR_VGC_IRQENABLE 0x0438
87#define ADDR_VGC_IRQSTATUS 0x0418
88#define ADDR_VGC_IRQ_ACTIVE_CNT 0x04E0
89#define ADDR_VGC_MMUCOMMANDSTREAM 0x03FC
90#define ADDR_VGV3_CONTROL 0x0070
91#define ADDR_VGV3_LAST 0x007F
92#define ADDR_VGV3_MODE 0x0071
93#define ADDR_VGV3_NEXTADDR 0x0075
94#define ADDR_VGV3_NEXTCMD 0x0076
95#define ADDR_VGV3_WRITEADDR 0x0072
96
97#endif /* _G12_REG_H */